s3c24x0_i2c.c 8.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2002
  4. * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
  5. */
  6. #include <common.h>
  7. #include <errno.h>
  8. #include <dm.h>
  9. #include <fdtdec.h>
  10. #if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
  11. #include <log.h>
  12. #include <asm/arch/clk.h>
  13. #include <asm/arch/cpu.h>
  14. #include <asm/arch/pinmux.h>
  15. #else
  16. #include <asm/arch/s3c24x0_cpu.h>
  17. #endif
  18. #include <asm/global_data.h>
  19. #include <asm/io.h>
  20. #include <i2c.h>
  21. #include "s3c24x0_i2c.h"
  22. #ifndef CONFIG_SYS_I2C_S3C24X0_SLAVE
  23. #define SYS_I2C_S3C24X0_SLAVE_ADDR 0
  24. #else
  25. #define SYS_I2C_S3C24X0_SLAVE_ADDR CONFIG_SYS_I2C_S3C24X0_SLAVE
  26. #endif
  27. DECLARE_GLOBAL_DATA_PTR;
  28. /*
  29. * Wait til the byte transfer is completed.
  30. *
  31. * @param i2c- pointer to the appropriate i2c register bank.
  32. * @return I2C_OK, if transmission was ACKED
  33. * I2C_NACK, if transmission was NACKED
  34. * I2C_NOK_TIMEOUT, if transaction did not complete in I2C_TIMEOUT_MS
  35. */
  36. static int WaitForXfer(struct s3c24x0_i2c *i2c)
  37. {
  38. ulong start_time = get_timer(0);
  39. do {
  40. if (readl(&i2c->iiccon) & I2CCON_IRPND)
  41. return (readl(&i2c->iicstat) & I2CSTAT_NACK) ?
  42. I2C_NACK : I2C_OK;
  43. } while (get_timer(start_time) < I2C_TIMEOUT_MS);
  44. return I2C_NOK_TOUT;
  45. }
  46. static void read_write_byte(struct s3c24x0_i2c *i2c)
  47. {
  48. clrbits_le32(&i2c->iiccon, I2CCON_IRPND);
  49. }
  50. static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd)
  51. {
  52. ulong freq, pres = 16, div;
  53. #if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
  54. freq = get_i2c_clk();
  55. #else
  56. freq = get_PCLK();
  57. #endif
  58. /* calculate prescaler and divisor values */
  59. if ((freq / pres / (16 + 1)) > speed)
  60. /* set prescaler to 512 */
  61. pres = 512;
  62. div = 0;
  63. while ((freq / pres / (div + 1)) > speed)
  64. div++;
  65. /* set prescaler, divisor according to freq, also set ACKGEN, IRQ */
  66. writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->iiccon);
  67. /* init to SLAVE REVEIVE and set slaveaddr */
  68. writel(0, &i2c->iicstat);
  69. writel(slaveadd, &i2c->iicadd);
  70. /* program Master Transmit (and implicit STOP) */
  71. writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
  72. }
  73. static int s3c24x0_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
  74. {
  75. struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
  76. i2c_bus->clock_frequency = speed;
  77. i2c_ch_init(i2c_bus->regs, i2c_bus->clock_frequency,
  78. SYS_I2C_S3C24X0_SLAVE_ADDR);
  79. return 0;
  80. }
  81. /*
  82. * cmd_type is 0 for write, 1 for read.
  83. *
  84. * addr_len can take any value from 0-255, it is only limited
  85. * by the char, we could make it larger if needed. If it is
  86. * 0 we skip the address write cycle.
  87. */
  88. static int i2c_transfer(struct s3c24x0_i2c *i2c,
  89. unsigned char cmd_type,
  90. unsigned char chip,
  91. unsigned char addr[],
  92. unsigned char addr_len,
  93. unsigned char data[],
  94. unsigned short data_len)
  95. {
  96. int i = 0, result;
  97. ulong start_time = get_timer(0);
  98. if (data == 0 || data_len == 0) {
  99. /*Don't support data transfer of no length or to address 0 */
  100. debug("i2c_transfer: bad call\n");
  101. return I2C_NOK;
  102. }
  103. while (readl(&i2c->iicstat) & I2CSTAT_BSY) {
  104. if (get_timer(start_time) > I2C_TIMEOUT_MS)
  105. return I2C_NOK_TOUT;
  106. }
  107. writel(readl(&i2c->iiccon) | I2CCON_ACKGEN, &i2c->iiccon);
  108. /* Get the slave chip address going */
  109. writel(chip, &i2c->iicds);
  110. if ((cmd_type == I2C_WRITE) || (addr && addr_len))
  111. writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
  112. &i2c->iicstat);
  113. else
  114. writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP,
  115. &i2c->iicstat);
  116. /* Wait for chip address to transmit. */
  117. result = WaitForXfer(i2c);
  118. if (result != I2C_OK)
  119. goto bailout;
  120. /* If register address needs to be transmitted - do it now. */
  121. if (addr && addr_len) {
  122. while ((i < addr_len) && (result == I2C_OK)) {
  123. writel(addr[i++], &i2c->iicds);
  124. read_write_byte(i2c);
  125. result = WaitForXfer(i2c);
  126. }
  127. i = 0;
  128. if (result != I2C_OK)
  129. goto bailout;
  130. }
  131. switch (cmd_type) {
  132. case I2C_WRITE:
  133. while ((i < data_len) && (result == I2C_OK)) {
  134. writel(data[i++], &i2c->iicds);
  135. read_write_byte(i2c);
  136. result = WaitForXfer(i2c);
  137. }
  138. break;
  139. case I2C_READ:
  140. if (addr && addr_len) {
  141. /*
  142. * Register address has been sent, now send slave chip
  143. * address again to start the actual read transaction.
  144. */
  145. writel(chip, &i2c->iicds);
  146. /* Generate a re-START. */
  147. writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP,
  148. &i2c->iicstat);
  149. read_write_byte(i2c);
  150. result = WaitForXfer(i2c);
  151. if (result != I2C_OK)
  152. goto bailout;
  153. }
  154. while ((i < data_len) && (result == I2C_OK)) {
  155. /* disable ACK for final READ */
  156. if (i == data_len - 1)
  157. writel(readl(&i2c->iiccon)
  158. & ~I2CCON_ACKGEN,
  159. &i2c->iiccon);
  160. read_write_byte(i2c);
  161. result = WaitForXfer(i2c);
  162. data[i++] = readl(&i2c->iicds);
  163. }
  164. if (result == I2C_NACK)
  165. result = I2C_OK; /* Normal terminated read. */
  166. break;
  167. default:
  168. debug("i2c_transfer: bad call\n");
  169. result = I2C_NOK;
  170. break;
  171. }
  172. bailout:
  173. /* Send STOP. */
  174. writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
  175. read_write_byte(i2c);
  176. return result;
  177. }
  178. static int s3c24x0_i2c_probe(struct udevice *dev, uint chip, uint chip_flags)
  179. {
  180. struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
  181. uchar buf[1];
  182. int ret;
  183. buf[0] = 0;
  184. /*
  185. * What is needed is to send the chip address and verify that the
  186. * address was <ACK>ed (i.e. there was a chip at that address which
  187. * drove the data line low).
  188. */
  189. ret = i2c_transfer(i2c_bus->regs, I2C_READ, chip << 1, 0, 0, buf, 1);
  190. return ret != I2C_OK;
  191. }
  192. static int s3c24x0_do_msg(struct s3c24x0_i2c_bus *i2c_bus, struct i2c_msg *msg,
  193. int seq)
  194. {
  195. struct s3c24x0_i2c *i2c = i2c_bus->regs;
  196. bool is_read = msg->flags & I2C_M_RD;
  197. uint status;
  198. uint addr;
  199. int ret, i;
  200. if (!seq)
  201. setbits_le32(&i2c->iiccon, I2CCON_ACKGEN);
  202. /* Get the slave chip address going */
  203. addr = msg->addr << 1;
  204. writel(addr, &i2c->iicds);
  205. status = I2C_TXRX_ENA | I2C_START_STOP;
  206. if (is_read)
  207. status |= I2C_MODE_MR;
  208. else
  209. status |= I2C_MODE_MT;
  210. writel(status, &i2c->iicstat);
  211. if (seq)
  212. read_write_byte(i2c);
  213. /* Wait for chip address to transmit */
  214. ret = WaitForXfer(i2c);
  215. if (ret)
  216. goto err;
  217. if (is_read) {
  218. for (i = 0; !ret && i < msg->len; i++) {
  219. /* disable ACK for final READ */
  220. if (i == msg->len - 1)
  221. clrbits_le32(&i2c->iiccon, I2CCON_ACKGEN);
  222. read_write_byte(i2c);
  223. ret = WaitForXfer(i2c);
  224. msg->buf[i] = readl(&i2c->iicds);
  225. }
  226. if (ret == I2C_NACK)
  227. ret = I2C_OK; /* Normal terminated read */
  228. } else {
  229. for (i = 0; !ret && i < msg->len; i++) {
  230. writel(msg->buf[i], &i2c->iicds);
  231. read_write_byte(i2c);
  232. ret = WaitForXfer(i2c);
  233. }
  234. }
  235. err:
  236. return ret;
  237. }
  238. static int s3c24x0_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
  239. int nmsgs)
  240. {
  241. struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
  242. struct s3c24x0_i2c *i2c = i2c_bus->regs;
  243. ulong start_time;
  244. int ret, i;
  245. start_time = get_timer(0);
  246. while (readl(&i2c->iicstat) & I2CSTAT_BSY) {
  247. if (get_timer(start_time) > I2C_TIMEOUT_MS) {
  248. debug("Timeout\n");
  249. return -ETIMEDOUT;
  250. }
  251. }
  252. for (ret = 0, i = 0; !ret && i < nmsgs; i++)
  253. ret = s3c24x0_do_msg(i2c_bus, &msg[i], i);
  254. /* Send STOP */
  255. writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
  256. read_write_byte(i2c);
  257. return ret ? -EREMOTEIO : 0;
  258. }
  259. static int s3c_i2c_of_to_plat(struct udevice *dev)
  260. {
  261. const void *blob = gd->fdt_blob;
  262. struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
  263. int node;
  264. node = dev_of_offset(dev);
  265. i2c_bus->regs = dev_read_addr_ptr(dev);
  266. i2c_bus->id = pinmux_decode_periph_id(blob, node);
  267. i2c_bus->clock_frequency =
  268. dev_read_u32_default(dev, "clock-frequency",
  269. I2C_SPEED_STANDARD_RATE);
  270. i2c_bus->node = node;
  271. i2c_bus->bus_num = dev_seq(dev);
  272. exynos_pinmux_config(i2c_bus->id, 0);
  273. i2c_bus->active = true;
  274. return 0;
  275. }
  276. static const struct dm_i2c_ops s3c_i2c_ops = {
  277. .xfer = s3c24x0_i2c_xfer,
  278. .probe_chip = s3c24x0_i2c_probe,
  279. .set_bus_speed = s3c24x0_i2c_set_bus_speed,
  280. };
  281. static const struct udevice_id s3c_i2c_ids[] = {
  282. { .compatible = "samsung,s3c2440-i2c" },
  283. { }
  284. };
  285. U_BOOT_DRIVER(i2c_s3c) = {
  286. .name = "i2c_s3c",
  287. .id = UCLASS_I2C,
  288. .of_match = s3c_i2c_ids,
  289. .of_to_plat = s3c_i2c_of_to_plat,
  290. .priv_auto = sizeof(struct s3c24x0_i2c_bus),
  291. .ops = &s3c_i2c_ops,
  292. };