rcar_i2c.c 9.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * drivers/i2c/rcar_i2c.c
  4. *
  5. * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
  6. *
  7. * Clock configuration based on Linux i2c-rcar.c:
  8. * Copyright (C) 2014-15 Wolfram Sang <wsa@sang-engineering.com>
  9. * Copyright (C) 2011-2015 Renesas Electronics Corporation
  10. * Copyright (C) 2012-14 Renesas Solutions Corp.
  11. * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
  12. */
  13. #include <common.h>
  14. #include <clk.h>
  15. #include <dm.h>
  16. #include <i2c.h>
  17. #include <asm/io.h>
  18. #include <wait_bit.h>
  19. #include <dm/device_compat.h>
  20. #include <linux/bitops.h>
  21. #include <linux/delay.h>
  22. #define RCAR_I2C_ICSCR 0x00 /* slave ctrl */
  23. #define RCAR_I2C_ICMCR 0x04 /* master ctrl */
  24. #define RCAR_I2C_ICMCR_MDBS BIT(7) /* non-fifo mode switch */
  25. #define RCAR_I2C_ICMCR_FSCL BIT(6) /* override SCL pin */
  26. #define RCAR_I2C_ICMCR_FSDA BIT(5) /* override SDA pin */
  27. #define RCAR_I2C_ICMCR_OBPC BIT(4) /* override pins */
  28. #define RCAR_I2C_ICMCR_MIE BIT(3) /* master if enable */
  29. #define RCAR_I2C_ICMCR_TSBE BIT(2)
  30. #define RCAR_I2C_ICMCR_FSB BIT(1) /* force stop bit */
  31. #define RCAR_I2C_ICMCR_ESG BIT(0) /* enable start bit gen */
  32. #define RCAR_I2C_ICSSR 0x08 /* slave status */
  33. #define RCAR_I2C_ICMSR 0x0c /* master status */
  34. #define RCAR_I2C_ICMSR_MASK 0x7f
  35. #define RCAR_I2C_ICMSR_MNR BIT(6) /* Nack */
  36. #define RCAR_I2C_ICMSR_MAL BIT(5) /* Arbitration lost */
  37. #define RCAR_I2C_ICMSR_MST BIT(4) /* Stop */
  38. #define RCAR_I2C_ICMSR_MDE BIT(3)
  39. #define RCAR_I2C_ICMSR_MDT BIT(2)
  40. #define RCAR_I2C_ICMSR_MDR BIT(1)
  41. #define RCAR_I2C_ICMSR_MAT BIT(0)
  42. #define RCAR_I2C_ICSIER 0x10 /* slave irq enable */
  43. #define RCAR_I2C_ICMIER 0x14 /* master irq enable */
  44. #define RCAR_I2C_ICCCR 0x18 /* clock dividers */
  45. #define RCAR_I2C_ICCCR_SCGD_OFF 3
  46. #define RCAR_I2C_ICSAR 0x1c /* slave address */
  47. #define RCAR_I2C_ICMAR 0x20 /* master address */
  48. #define RCAR_I2C_ICRXD_ICTXD 0x24 /* data port */
  49. /*
  50. * First Bit Setup Cycle (Gen3).
  51. * Defines 1st bit delay between SDA and SCL.
  52. */
  53. #define RCAR_I2C_ICFBSCR 0x38
  54. #define RCAR_I2C_ICFBSCR_TCYC17 0x0f /* 17*Tcyc */
  55. enum rcar_i2c_type {
  56. RCAR_I2C_TYPE_GEN2,
  57. RCAR_I2C_TYPE_GEN3,
  58. };
  59. struct rcar_i2c_priv {
  60. void __iomem *base;
  61. struct clk clk;
  62. u32 intdelay;
  63. u32 icccr;
  64. enum rcar_i2c_type type;
  65. };
  66. static int rcar_i2c_finish(struct udevice *dev)
  67. {
  68. struct rcar_i2c_priv *priv = dev_get_priv(dev);
  69. int ret;
  70. ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMSR, RCAR_I2C_ICMSR_MST,
  71. true, 10, true);
  72. writel(0, priv->base + RCAR_I2C_ICSSR);
  73. writel(0, priv->base + RCAR_I2C_ICMSR);
  74. writel(0, priv->base + RCAR_I2C_ICMCR);
  75. return ret;
  76. }
  77. static int rcar_i2c_recover(struct udevice *dev)
  78. {
  79. struct rcar_i2c_priv *priv = dev_get_priv(dev);
  80. u32 mcr = RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_OBPC;
  81. u32 mcra = mcr | RCAR_I2C_ICMCR_FSDA;
  82. int i;
  83. u32 mstat;
  84. /* Send 9 SCL pulses */
  85. for (i = 0; i < 9; i++) {
  86. writel(mcra | RCAR_I2C_ICMCR_FSCL, priv->base + RCAR_I2C_ICMCR);
  87. udelay(5);
  88. writel(mcra, priv->base + RCAR_I2C_ICMCR);
  89. udelay(5);
  90. }
  91. /* Send stop condition */
  92. udelay(5);
  93. writel(mcra, priv->base + RCAR_I2C_ICMCR);
  94. udelay(5);
  95. writel(mcr, priv->base + RCAR_I2C_ICMCR);
  96. udelay(5);
  97. writel(mcr | RCAR_I2C_ICMCR_FSCL, priv->base + RCAR_I2C_ICMCR);
  98. udelay(5);
  99. writel(mcra | RCAR_I2C_ICMCR_FSCL, priv->base + RCAR_I2C_ICMCR);
  100. udelay(5);
  101. mstat = readl(priv->base + RCAR_I2C_ICMSR);
  102. return mstat & RCAR_I2C_ICMCR_FSDA ? -EBUSY : 0;
  103. }
  104. static int rcar_i2c_set_addr(struct udevice *dev, u8 chip, u8 read)
  105. {
  106. struct rcar_i2c_priv *priv = dev_get_priv(dev);
  107. u32 mask = RCAR_I2C_ICMSR_MAT |
  108. (read ? RCAR_I2C_ICMSR_MDR : RCAR_I2C_ICMSR_MDE);
  109. int ret;
  110. writel(0, priv->base + RCAR_I2C_ICMIER);
  111. writel(RCAR_I2C_ICMCR_MDBS, priv->base + RCAR_I2C_ICMCR);
  112. writel(0, priv->base + RCAR_I2C_ICMSR);
  113. writel(priv->icccr, priv->base + RCAR_I2C_ICCCR);
  114. /* Wait for the bus */
  115. ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMCR,
  116. RCAR_I2C_ICMCR_FSDA, false, 2, true);
  117. if (ret) {
  118. if (rcar_i2c_recover(dev)) {
  119. dev_err(dev, "Bus busy, aborting\n");
  120. return ret;
  121. }
  122. }
  123. writel((chip << 1) | read, priv->base + RCAR_I2C_ICMAR);
  124. /* Reset */
  125. writel(RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_MIE | RCAR_I2C_ICMCR_ESG,
  126. priv->base + RCAR_I2C_ICMCR);
  127. /* Clear Status */
  128. writel(0, priv->base + RCAR_I2C_ICMSR);
  129. ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMSR, mask,
  130. true, 100, true);
  131. if (ret)
  132. return ret;
  133. /* Check NAK */
  134. if (readl(priv->base + RCAR_I2C_ICMSR) & RCAR_I2C_ICMSR_MNR)
  135. return -EREMOTEIO;
  136. return 0;
  137. }
  138. static int rcar_i2c_read_common(struct udevice *dev, struct i2c_msg *msg)
  139. {
  140. struct rcar_i2c_priv *priv = dev_get_priv(dev);
  141. u32 icmcr = RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_MIE;
  142. int i, ret = -EREMOTEIO;
  143. for (i = 0; i < msg->len; i++) {
  144. if (msg->len - 1 == i)
  145. icmcr |= RCAR_I2C_ICMCR_FSB;
  146. writel(icmcr, priv->base + RCAR_I2C_ICMCR);
  147. writel((u32)~RCAR_I2C_ICMSR_MDR, priv->base + RCAR_I2C_ICMSR);
  148. ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMSR,
  149. RCAR_I2C_ICMSR_MDR, true, 100, true);
  150. if (ret)
  151. return ret;
  152. msg->buf[i] = readl(priv->base + RCAR_I2C_ICRXD_ICTXD) & 0xff;
  153. }
  154. writel((u32)~RCAR_I2C_ICMSR_MDR, priv->base + RCAR_I2C_ICMSR);
  155. return rcar_i2c_finish(dev);
  156. }
  157. static int rcar_i2c_write_common(struct udevice *dev, struct i2c_msg *msg)
  158. {
  159. struct rcar_i2c_priv *priv = dev_get_priv(dev);
  160. u32 icmcr = RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_MIE;
  161. int i, ret = -EREMOTEIO;
  162. for (i = 0; i < msg->len; i++) {
  163. writel(msg->buf[i], priv->base + RCAR_I2C_ICRXD_ICTXD);
  164. writel(icmcr, priv->base + RCAR_I2C_ICMCR);
  165. writel((u32)~RCAR_I2C_ICMSR_MDE, priv->base + RCAR_I2C_ICMSR);
  166. ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMSR,
  167. RCAR_I2C_ICMSR_MDE, true, 100, true);
  168. if (ret)
  169. return ret;
  170. }
  171. writel((u32)~RCAR_I2C_ICMSR_MDE, priv->base + RCAR_I2C_ICMSR);
  172. icmcr |= RCAR_I2C_ICMCR_FSB;
  173. writel(icmcr, priv->base + RCAR_I2C_ICMCR);
  174. return rcar_i2c_finish(dev);
  175. }
  176. static int rcar_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs)
  177. {
  178. int ret;
  179. for (; nmsgs > 0; nmsgs--, msg++) {
  180. ret = rcar_i2c_set_addr(dev, msg->addr, !!(msg->flags & I2C_M_RD));
  181. if (ret)
  182. return ret;
  183. if (msg->flags & I2C_M_RD)
  184. ret = rcar_i2c_read_common(dev, msg);
  185. else
  186. ret = rcar_i2c_write_common(dev, msg);
  187. if (ret)
  188. return ret;
  189. }
  190. return 0;
  191. }
  192. static int rcar_i2c_probe_chip(struct udevice *dev, uint addr, uint flags)
  193. {
  194. struct rcar_i2c_priv *priv = dev_get_priv(dev);
  195. int ret;
  196. /* Ignore address 0, slave address */
  197. if (addr == 0)
  198. return -EINVAL;
  199. ret = rcar_i2c_set_addr(dev, addr, 1);
  200. writel(0, priv->base + RCAR_I2C_ICMSR);
  201. return ret;
  202. }
  203. static int rcar_i2c_set_speed(struct udevice *dev, uint bus_freq_hz)
  204. {
  205. struct rcar_i2c_priv *priv = dev_get_priv(dev);
  206. u32 scgd, cdf, round, ick, sum, scl;
  207. unsigned long rate;
  208. /*
  209. * calculate SCL clock
  210. * see
  211. * ICCCR
  212. *
  213. * ick = clkp / (1 + CDF)
  214. * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
  215. *
  216. * ick : I2C internal clock < 20 MHz
  217. * ticf : I2C SCL falling time
  218. * tr : I2C SCL rising time
  219. * intd : LSI internal delay
  220. * clkp : peripheral_clk
  221. * F[] : integer up-valuation
  222. */
  223. rate = clk_get_rate(&priv->clk);
  224. cdf = rate / 20000000;
  225. if (cdf >= 8) {
  226. dev_err(dev, "Input clock %lu too high\n", rate);
  227. return -EIO;
  228. }
  229. ick = rate / (cdf + 1);
  230. /*
  231. * it is impossible to calculate large scale
  232. * number on u32. separate it
  233. *
  234. * F[(ticf + tr + intd) * ick] with sum = (ticf + tr + intd)
  235. * = F[sum * ick / 1000000000]
  236. * = F[(ick / 1000000) * sum / 1000]
  237. */
  238. sum = 35 + 200 + priv->intdelay;
  239. round = (ick + 500000) / 1000000 * sum;
  240. round = (round + 500) / 1000;
  241. /*
  242. * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
  243. *
  244. * Calculation result (= SCL) should be less than
  245. * bus_speed for hardware safety
  246. *
  247. * We could use something along the lines of
  248. * div = ick / (bus_speed + 1) + 1;
  249. * scgd = (div - 20 - round + 7) / 8;
  250. * scl = ick / (20 + (scgd * 8) + round);
  251. * (not fully verified) but that would get pretty involved
  252. */
  253. for (scgd = 0; scgd < 0x40; scgd++) {
  254. scl = ick / (20 + (scgd * 8) + round);
  255. if (scl <= bus_freq_hz)
  256. goto scgd_find;
  257. }
  258. dev_err(dev, "it is impossible to calculate best SCL\n");
  259. return -EIO;
  260. scgd_find:
  261. dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n",
  262. scl, bus_freq_hz, clk_get_rate(&priv->clk), round, cdf, scgd);
  263. priv->icccr = (scgd << RCAR_I2C_ICCCR_SCGD_OFF) | cdf;
  264. writel(priv->icccr, priv->base + RCAR_I2C_ICCCR);
  265. if (priv->type == RCAR_I2C_TYPE_GEN3) {
  266. /* Set SCL/SDA delay */
  267. writel(RCAR_I2C_ICFBSCR_TCYC17, priv->base + RCAR_I2C_ICFBSCR);
  268. }
  269. return 0;
  270. }
  271. static int rcar_i2c_probe(struct udevice *dev)
  272. {
  273. struct rcar_i2c_priv *priv = dev_get_priv(dev);
  274. int ret;
  275. priv->base = dev_read_addr_ptr(dev);
  276. priv->intdelay = dev_read_u32_default(dev,
  277. "i2c-scl-internal-delay-ns", 5);
  278. priv->type = dev_get_driver_data(dev);
  279. ret = clk_get_by_index(dev, 0, &priv->clk);
  280. if (ret)
  281. return ret;
  282. ret = clk_enable(&priv->clk);
  283. if (ret)
  284. return ret;
  285. /* reset slave mode */
  286. writel(0, priv->base + RCAR_I2C_ICSIER);
  287. writel(0, priv->base + RCAR_I2C_ICSAR);
  288. writel(0, priv->base + RCAR_I2C_ICSCR);
  289. writel(0, priv->base + RCAR_I2C_ICSSR);
  290. /* reset master mode */
  291. writel(0, priv->base + RCAR_I2C_ICMIER);
  292. writel(0, priv->base + RCAR_I2C_ICMCR);
  293. writel(0, priv->base + RCAR_I2C_ICMSR);
  294. writel(0, priv->base + RCAR_I2C_ICMAR);
  295. ret = rcar_i2c_set_speed(dev, I2C_SPEED_STANDARD_RATE);
  296. if (ret)
  297. clk_disable(&priv->clk);
  298. return ret;
  299. }
  300. static const struct dm_i2c_ops rcar_i2c_ops = {
  301. .xfer = rcar_i2c_xfer,
  302. .probe_chip = rcar_i2c_probe_chip,
  303. .set_bus_speed = rcar_i2c_set_speed,
  304. };
  305. static const struct udevice_id rcar_i2c_ids[] = {
  306. { .compatible = "renesas,rcar-gen2-i2c", .data = RCAR_I2C_TYPE_GEN2 },
  307. { .compatible = "renesas,rcar-gen3-i2c", .data = RCAR_I2C_TYPE_GEN3 },
  308. { }
  309. };
  310. U_BOOT_DRIVER(i2c_rcar) = {
  311. .name = "i2c_rcar",
  312. .id = UCLASS_I2C,
  313. .of_match = rcar_i2c_ids,
  314. .probe = rcar_i2c_probe,
  315. .priv_auto = sizeof(struct rcar_i2c_priv),
  316. .ops = &rcar_i2c_ops,
  317. };