ocores_i2c.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * ocores-i2c.c: I2C bus driver for OpenCores I2C controller
  4. * (https://opencores.org/projects/i2c)
  5. *
  6. * (C) Copyright Peter Korsgaard <peter@korsgaard.com>
  7. *
  8. * Copyright (C) 2020 SiFive, Inc.
  9. * Pragnesh Patel <pragnesh.patel@sifive.com>
  10. *
  11. * Support for the GRLIB port of the controller by
  12. * Andreas Larsson <andreas@gaisler.com>
  13. */
  14. #include <common.h>
  15. #include <asm/global_data.h>
  16. #include <asm/io.h>
  17. #include <clk.h>
  18. #include <dm.h>
  19. #include <dm/device_compat.h>
  20. #include <i2c.h>
  21. #include <linux/io.h>
  22. #include <linux/compat.h>
  23. #include <linux/log2.h>
  24. #include <linux/delay.h>
  25. /* registers */
  26. #define OCI2C_PRELOW 0
  27. #define OCI2C_PREHIGH 1
  28. #define OCI2C_CONTROL 2
  29. #define OCI2C_DATA 3
  30. #define OCI2C_CMD 4 /* write only */
  31. #define OCI2C_STATUS 4 /* read only, same address as OCI2C_CMD */
  32. #define OCI2C_CTRL_IEN 0x40
  33. #define OCI2C_CTRL_EN 0x80
  34. #define OCI2C_CMD_START 0x91
  35. #define OCI2C_CMD_STOP 0x41
  36. #define OCI2C_CMD_READ 0x21
  37. #define OCI2C_CMD_WRITE 0x11
  38. #define OCI2C_CMD_READ_ACK 0x21
  39. #define OCI2C_CMD_READ_NACK 0x29
  40. #define OCI2C_CMD_IACK 0x01
  41. #define OCI2C_STAT_IF 0x01
  42. #define OCI2C_STAT_TIP 0x02
  43. #define OCI2C_STAT_ARBLOST 0x20
  44. #define OCI2C_STAT_BUSY 0x40
  45. #define OCI2C_STAT_NACK 0x80
  46. #define STATE_DONE 0
  47. #define STATE_START 1
  48. #define STATE_WRITE 2
  49. #define STATE_READ 3
  50. #define STATE_ERROR 4
  51. #define TYPE_OCORES 0
  52. #define TYPE_GRLIB 1
  53. #define OCORES_FLAG_BROKEN_IRQ BIT(1) /* Broken IRQ for FU540-C000 SoC */
  54. struct ocores_i2c_bus {
  55. void __iomem *base;
  56. u32 reg_shift;
  57. u32 reg_io_width;
  58. unsigned long flags;
  59. struct i2c_msg *msg;
  60. int pos;
  61. int nmsgs;
  62. int state; /* see STATE_ */
  63. struct clk clk;
  64. int ip_clk_khz;
  65. int bus_clk_khz;
  66. void (*setreg)(struct ocores_i2c_bus *i2c, int reg, u8 value);
  67. u8 (*getreg)(struct ocores_i2c_bus *i2c, int reg);
  68. };
  69. DECLARE_GLOBAL_DATA_PTR;
  70. /* Boolean attribute values */
  71. enum {
  72. FALSE = 0,
  73. TRUE,
  74. };
  75. static void oc_setreg_8(struct ocores_i2c_bus *i2c, int reg, u8 value)
  76. {
  77. writeb(value, i2c->base + (reg << i2c->reg_shift));
  78. }
  79. static void oc_setreg_16(struct ocores_i2c_bus *i2c, int reg, u8 value)
  80. {
  81. writew(value, i2c->base + (reg << i2c->reg_shift));
  82. }
  83. static void oc_setreg_32(struct ocores_i2c_bus *i2c, int reg, u8 value)
  84. {
  85. writel(value, i2c->base + (reg << i2c->reg_shift));
  86. }
  87. static void oc_setreg_16be(struct ocores_i2c_bus *i2c, int reg, u8 value)
  88. {
  89. out_be16(i2c->base + (reg << i2c->reg_shift), value);
  90. }
  91. static void oc_setreg_32be(struct ocores_i2c_bus *i2c, int reg, u8 value)
  92. {
  93. out_be32(i2c->base + (reg << i2c->reg_shift), value);
  94. }
  95. static inline u8 oc_getreg_8(struct ocores_i2c_bus *i2c, int reg)
  96. {
  97. return readb(i2c->base + (reg << i2c->reg_shift));
  98. }
  99. static inline u8 oc_getreg_16(struct ocores_i2c_bus *i2c, int reg)
  100. {
  101. return readw(i2c->base + (reg << i2c->reg_shift));
  102. }
  103. static inline u8 oc_getreg_32(struct ocores_i2c_bus *i2c, int reg)
  104. {
  105. return readl(i2c->base + (reg << i2c->reg_shift));
  106. }
  107. static inline u8 oc_getreg_16be(struct ocores_i2c_bus *i2c, int reg)
  108. {
  109. return in_be16(i2c->base + (reg << i2c->reg_shift));
  110. }
  111. static inline u8 oc_getreg_32be(struct ocores_i2c_bus *i2c, int reg)
  112. {
  113. return in_be32(i2c->base + (reg << i2c->reg_shift));
  114. }
  115. static inline void oc_setreg(struct ocores_i2c_bus *i2c, int reg, u8 value)
  116. {
  117. i2c->setreg(i2c, reg, value);
  118. }
  119. static inline u8 oc_getreg(struct ocores_i2c_bus *i2c, int reg)
  120. {
  121. return i2c->getreg(i2c, reg);
  122. }
  123. static inline u8 i2c_8bit_addr_from_msg(const struct i2c_msg *msg)
  124. {
  125. return (msg->addr << 1) | (msg->flags & I2C_M_RD ? 1 : 0);
  126. }
  127. static void ocores_process(struct ocores_i2c_bus *i2c, u8 stat)
  128. {
  129. struct i2c_msg *msg = i2c->msg;
  130. if (i2c->state == STATE_DONE || i2c->state == STATE_ERROR) {
  131. /* stop has been sent */
  132. oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
  133. return;
  134. }
  135. /* error? */
  136. if (stat & OCI2C_STAT_ARBLOST) {
  137. i2c->state = STATE_ERROR;
  138. oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
  139. return;
  140. }
  141. if (i2c->state == STATE_START || i2c->state == STATE_WRITE) {
  142. i2c->state =
  143. (msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE;
  144. if (stat & OCI2C_STAT_NACK) {
  145. i2c->state = STATE_ERROR;
  146. oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
  147. return;
  148. }
  149. } else {
  150. msg->buf[i2c->pos++] = oc_getreg(i2c, OCI2C_DATA);
  151. }
  152. /* end of msg? */
  153. if (i2c->pos == msg->len) {
  154. i2c->nmsgs--;
  155. i2c->msg++;
  156. i2c->pos = 0;
  157. msg = i2c->msg;
  158. if (i2c->nmsgs) { /* end? */
  159. /* send start? */
  160. if (!(msg->flags & I2C_M_NOSTART)) {
  161. u8 addr = i2c_8bit_addr_from_msg(msg);
  162. i2c->state = STATE_START;
  163. oc_setreg(i2c, OCI2C_DATA, addr);
  164. oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);
  165. return;
  166. }
  167. i2c->state = (msg->flags & I2C_M_RD)
  168. ? STATE_READ : STATE_WRITE;
  169. } else {
  170. i2c->state = STATE_DONE;
  171. oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
  172. return;
  173. }
  174. }
  175. if (i2c->state == STATE_READ) {
  176. oc_setreg(i2c, OCI2C_CMD, i2c->pos == (msg->len - 1) ?
  177. OCI2C_CMD_READ_NACK : OCI2C_CMD_READ_ACK);
  178. } else {
  179. oc_setreg(i2c, OCI2C_DATA, msg->buf[i2c->pos++]);
  180. oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_WRITE);
  181. }
  182. }
  183. static irqreturn_t ocores_isr(int irq, void *dev_id)
  184. {
  185. struct ocores_i2c_bus *i2c = dev_id;
  186. u8 stat = oc_getreg(i2c, OCI2C_STATUS);
  187. if (i2c->flags & OCORES_FLAG_BROKEN_IRQ) {
  188. if ((stat & OCI2C_STAT_IF) && !(stat & OCI2C_STAT_BUSY))
  189. return IRQ_NONE;
  190. } else if (!(stat & OCI2C_STAT_IF)) {
  191. return IRQ_NONE;
  192. }
  193. ocores_process(i2c, stat);
  194. return IRQ_HANDLED;
  195. }
  196. /**
  197. * Wait until something change in a given register
  198. * @i2c: ocores I2C device instance
  199. * @reg: register to query
  200. * @mask: bitmask to apply on register value
  201. * @val: expected result
  202. * @msec: timeout in msec
  203. *
  204. * Timeout is necessary to avoid to stay here forever when the chip
  205. * does not answer correctly.
  206. *
  207. * Return: 0 on success, -ETIMEDOUT on timeout
  208. */
  209. static int ocores_wait(struct ocores_i2c_bus *i2c,
  210. int reg, u8 mask, u8 val,
  211. const unsigned long msec)
  212. {
  213. u32 count = 0;
  214. while (1) {
  215. u8 status = oc_getreg(i2c, reg);
  216. if ((status & mask) == val)
  217. break;
  218. udelay(1);
  219. count += 1;
  220. if (count == (1000 * msec))
  221. return -ETIMEDOUT;
  222. }
  223. return 0;
  224. }
  225. /**
  226. * Wait until is possible to process some data
  227. * @i2c: ocores I2C device instance
  228. *
  229. * Used when the device is in polling mode (interrupts disabled).
  230. *
  231. * Return: 0 on success, -ETIMEDOUT on timeout
  232. */
  233. static int ocores_poll_wait(struct ocores_i2c_bus *i2c)
  234. {
  235. u8 mask;
  236. int err;
  237. if (i2c->state == STATE_DONE || i2c->state == STATE_ERROR) {
  238. /* transfer is over */
  239. mask = OCI2C_STAT_BUSY;
  240. } else {
  241. /* on going transfer */
  242. mask = OCI2C_STAT_TIP;
  243. /*
  244. * We wait for the data to be transferred (8bit),
  245. * then we start polling on the ACK/NACK bit
  246. */
  247. udelay((8 * 1000) / i2c->bus_clk_khz);
  248. }
  249. /*
  250. * once we are here we expect to get the expected result immediately
  251. * so if after 1ms we timeout then something is broken.
  252. */
  253. err = ocores_wait(i2c, OCI2C_STATUS, mask, 0, 1);
  254. if (err)
  255. debug("%s: STATUS timeout, bit 0x%x did not clear in 1ms\n",
  256. __func__, mask);
  257. return err;
  258. }
  259. /**
  260. * It handles an IRQ-less transfer
  261. * @i2c: ocores I2C device instance
  262. *
  263. * Even if IRQ are disabled, the I2C OpenCore IP behavior is exactly the same
  264. * (only that IRQ are not produced). This means that we can re-use entirely
  265. * ocores_isr(), we just add our polling code around it.
  266. *
  267. * It can run in atomic context
  268. */
  269. static void ocores_process_polling(struct ocores_i2c_bus *i2c)
  270. {
  271. while (1) {
  272. irqreturn_t ret;
  273. int err;
  274. err = ocores_poll_wait(i2c);
  275. if (err) {
  276. i2c->state = STATE_ERROR;
  277. break; /* timeout */
  278. }
  279. ret = ocores_isr(-1, i2c);
  280. if (ret == IRQ_NONE) {
  281. break; /* all messages have been transferred */
  282. } else {
  283. if (i2c->flags & OCORES_FLAG_BROKEN_IRQ)
  284. if (i2c->state == STATE_DONE)
  285. break;
  286. }
  287. }
  288. }
  289. static int ocores_xfer_core(struct ocores_i2c_bus *i2c,
  290. struct i2c_msg *msgs, int num, bool polling)
  291. {
  292. u8 ctrl;
  293. ctrl = oc_getreg(i2c, OCI2C_CONTROL);
  294. if (polling)
  295. oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~OCI2C_CTRL_IEN);
  296. i2c->msg = msgs;
  297. i2c->pos = 0;
  298. i2c->nmsgs = num;
  299. i2c->state = STATE_START;
  300. oc_setreg(i2c, OCI2C_DATA, i2c_8bit_addr_from_msg(i2c->msg));
  301. oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);
  302. if (polling)
  303. ocores_process_polling(i2c);
  304. return (i2c->state == STATE_DONE) ? num : -EIO;
  305. }
  306. static int ocores_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs)
  307. {
  308. struct ocores_i2c_bus *bus = dev_get_priv(dev);
  309. int ret;
  310. debug("i2c_xfer: %d messages\n", nmsgs);
  311. ret = ocores_xfer_core(bus, msg, nmsgs, 1);
  312. if (ret != nmsgs) {
  313. debug("i2c_write: error sending\n");
  314. return -EREMOTEIO;
  315. }
  316. return 0;
  317. }
  318. static int ocores_i2c_enable_clk(struct udevice *dev)
  319. {
  320. struct ocores_i2c_bus *bus = dev_get_priv(dev);
  321. ulong clk_rate;
  322. int ret;
  323. ret = clk_get_by_index(dev, 0, &bus->clk);
  324. if (ret)
  325. return -EINVAL;
  326. ret = clk_enable(&bus->clk);
  327. if (ret)
  328. return ret;
  329. clk_rate = clk_get_rate(&bus->clk);
  330. if (!clk_rate)
  331. return -EINVAL;
  332. bus->ip_clk_khz = clk_rate / 1000;
  333. clk_free(&bus->clk);
  334. return 0;
  335. }
  336. static int ocores_init(struct udevice *dev, struct ocores_i2c_bus *bus)
  337. {
  338. int prescale;
  339. int diff;
  340. u8 ctrl = oc_getreg(bus, OCI2C_CONTROL);
  341. /* make sure the device is disabled */
  342. ctrl &= ~(OCI2C_CTRL_EN | OCI2C_CTRL_IEN);
  343. oc_setreg(bus, OCI2C_CONTROL, ctrl);
  344. prescale = (bus->ip_clk_khz / (5 * bus->bus_clk_khz)) - 1;
  345. prescale = clamp(prescale, 0, 0xffff);
  346. diff = bus->ip_clk_khz / (5 * (prescale + 1)) - bus->bus_clk_khz;
  347. if (abs(diff) > bus->bus_clk_khz / 10) {
  348. debug("Unsupported clock settings: core: %d KHz, bus: %d KHz\n",
  349. bus->ip_clk_khz, bus->bus_clk_khz);
  350. return -EINVAL;
  351. }
  352. oc_setreg(bus, OCI2C_PRELOW, prescale & 0xff);
  353. oc_setreg(bus, OCI2C_PREHIGH, prescale >> 8);
  354. /* Init the device */
  355. oc_setreg(bus, OCI2C_CMD, OCI2C_CMD_IACK);
  356. oc_setreg(bus, OCI2C_CONTROL, ctrl | OCI2C_CTRL_EN);
  357. return 0;
  358. }
  359. /*
  360. * Read and write functions for the GRLIB port of the controller. Registers are
  361. * 32-bit big endian and the PRELOW and PREHIGH registers are merged into one
  362. * register. The subsequent registers have their offsets decreased accordingly.
  363. */
  364. static u8 oc_getreg_grlib(struct ocores_i2c_bus *i2c, int reg)
  365. {
  366. u32 rd;
  367. int rreg = reg;
  368. if (reg != OCI2C_PRELOW)
  369. rreg--;
  370. rd = in_be32(i2c->base + (rreg << i2c->reg_shift));
  371. if (reg == OCI2C_PREHIGH)
  372. return (u8)(rd >> 8);
  373. else
  374. return (u8)rd;
  375. }
  376. static void oc_setreg_grlib(struct ocores_i2c_bus *i2c, int reg, u8 value)
  377. {
  378. u32 curr, wr;
  379. int rreg = reg;
  380. if (reg != OCI2C_PRELOW)
  381. rreg--;
  382. if (reg == OCI2C_PRELOW || reg == OCI2C_PREHIGH) {
  383. curr = in_be32(i2c->base + (rreg << i2c->reg_shift));
  384. if (reg == OCI2C_PRELOW)
  385. wr = (curr & 0xff00) | value;
  386. else
  387. wr = (((u32)value) << 8) | (curr & 0xff);
  388. } else {
  389. wr = value;
  390. }
  391. out_be32(i2c->base + (rreg << i2c->reg_shift), wr);
  392. }
  393. static int ocores_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
  394. {
  395. int prescale;
  396. int diff;
  397. struct ocores_i2c_bus *bus = dev_get_priv(dev);
  398. /* speed in Khz */
  399. speed = speed / 1000;
  400. prescale = (bus->ip_clk_khz / (5 * speed)) - 1;
  401. prescale = clamp(prescale, 0, 0xffff);
  402. diff = bus->ip_clk_khz / (5 * (prescale + 1)) - speed;
  403. if (abs(diff) > speed / 10) {
  404. debug("Unsupported clock settings: core: %d KHz, bus: %d KHz\n",
  405. bus->ip_clk_khz, speed);
  406. return -EINVAL;
  407. }
  408. oc_setreg(bus, OCI2C_PRELOW, prescale & 0xff);
  409. oc_setreg(bus, OCI2C_PREHIGH, prescale >> 8);
  410. bus->bus_clk_khz = speed;
  411. return 0;
  412. }
  413. int ocores_i2c_get_bus_speed(struct udevice *dev)
  414. {
  415. struct ocores_i2c_bus *bus = dev_get_priv(dev);
  416. return (bus->bus_clk_khz * 1000);
  417. }
  418. static const struct dm_i2c_ops ocores_i2c_ops = {
  419. .xfer = ocores_i2c_xfer,
  420. .set_bus_speed = ocores_i2c_set_bus_speed,
  421. .get_bus_speed = ocores_i2c_get_bus_speed,
  422. };
  423. static int ocores_i2c_probe(struct udevice *dev)
  424. {
  425. struct ocores_i2c_bus *bus = dev_get_priv(dev);
  426. bool clock_frequency_present;
  427. u32 val;
  428. u32 clock_frequency_khz;
  429. int ret;
  430. bus->base = (void __iomem *)devfdt_get_addr(dev);
  431. if (dev_read_u32(dev, "reg-shift", &bus->reg_shift)) {
  432. /* no 'reg-shift', check for deprecated 'regstep' */
  433. ret = dev_read_u32(dev, "regstep", &val);
  434. if (ret) {
  435. dev_err(dev,
  436. "missing both reg-shift and regstep property: %d\n", ret);
  437. return -EINVAL;
  438. } else {
  439. bus->reg_shift = ilog2(val);
  440. dev_warn(dev,
  441. "regstep property deprecated, use reg-shift\n");
  442. }
  443. }
  444. if (dev_read_u32(dev, "clock-frequency", &val)) {
  445. bus->bus_clk_khz = 100;
  446. clock_frequency_present = FALSE;
  447. } else {
  448. bus->bus_clk_khz = val / 1000;
  449. clock_frequency_khz = val / 1000;
  450. clock_frequency_present = TRUE;
  451. }
  452. ret = ocores_i2c_enable_clk(dev);
  453. if (ret)
  454. return ret;
  455. if (bus->ip_clk_khz == 0) {
  456. if (dev_read_u32(dev, "opencores,ip-clock-frequency", &val)) {
  457. if (!clock_frequency_present) {
  458. dev_err(dev,
  459. "Missing required parameter 'opencores,ip-clock-frequency'\n");
  460. clk_disable(&bus->clk);
  461. return -ENODEV;
  462. }
  463. bus->ip_clk_khz = clock_frequency_khz;
  464. dev_warn(dev,
  465. "Deprecated usage of the 'clock-frequency' property, please update to 'opencores,ip-clock-frequency'\n");
  466. } else {
  467. bus->ip_clk_khz = val / 1000;
  468. if (clock_frequency_present)
  469. bus->bus_clk_khz = clock_frequency_khz;
  470. }
  471. }
  472. bus->reg_io_width = dev_read_u32_default(dev, "reg-io-width", 1);
  473. if (dev_get_driver_data(dev) == TYPE_GRLIB) {
  474. debug("GRLIB variant of i2c-ocores\n");
  475. bus->setreg = oc_setreg_grlib;
  476. bus->getreg = oc_getreg_grlib;
  477. }
  478. if (!bus->setreg || !bus->getreg) {
  479. bool be = (cpu_to_be32(0x12345678) == 0x12345678);
  480. switch (bus->reg_io_width) {
  481. case 1:
  482. bus->setreg = oc_setreg_8;
  483. bus->getreg = oc_getreg_8;
  484. break;
  485. case 2:
  486. bus->setreg = be ? oc_setreg_16be : oc_setreg_16;
  487. bus->getreg = be ? oc_getreg_16be : oc_getreg_16;
  488. break;
  489. case 4:
  490. bus->setreg = be ? oc_setreg_32be : oc_setreg_32;
  491. bus->getreg = be ? oc_getreg_32be : oc_getreg_32;
  492. break;
  493. default:
  494. debug("Unsupported I/O width (%d)\n",
  495. bus->reg_io_width);
  496. ret = -EINVAL;
  497. goto err_clk;
  498. }
  499. }
  500. /*
  501. * Set OCORES_FLAG_BROKEN_IRQ to enable workaround for
  502. * FU540-C000 SoC in polling mode.
  503. * Since the SoC does have an interrupt, its DT has an interrupt
  504. * property - But this should be bypassed as the IRQ logic in this
  505. * SoC is broken.
  506. */
  507. if (device_is_compatible(dev, "sifive,fu540-c000-i2c"))
  508. bus->flags |= OCORES_FLAG_BROKEN_IRQ;
  509. ret = ocores_init(dev, bus);
  510. if (ret)
  511. goto err_clk;
  512. return 0;
  513. err_clk:
  514. clk_disable(&bus->clk);
  515. return ret;
  516. }
  517. static const struct udevice_id ocores_i2c_ids[] = {
  518. { .compatible = "opencores,i2c-ocores", .data = TYPE_OCORES },
  519. { .compatible = "aeroflexgaisler,i2cmst", .data = TYPE_GRLIB },
  520. { .compatible = "sifive,fu540-c000-i2c" },
  521. { .compatible = "sifive,i2c0" },
  522. { }
  523. };
  524. U_BOOT_DRIVER(i2c_ocores) = {
  525. .name = "i2c_ocores",
  526. .id = UCLASS_I2C,
  527. .of_match = ocores_i2c_ids,
  528. .probe = ocores_i2c_probe,
  529. .priv_auto = sizeof(struct ocores_i2c_bus),
  530. .ops = &ocores_i2c_ops,
  531. };