mvtwsi.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Driver for the TWSI (i2c) controller found on the Marvell
  4. * orion5x and kirkwood SoC families.
  5. *
  6. * Author: Albert Aribaud <albert.u.boot@aribaud.net>
  7. * Copyright (c) 2010 Albert Aribaud.
  8. */
  9. #include <common.h>
  10. #include <i2c.h>
  11. #include <log.h>
  12. #include <asm/global_data.h>
  13. #include <linux/delay.h>
  14. #include <linux/errno.h>
  15. #include <asm/io.h>
  16. #include <linux/bitops.h>
  17. #include <linux/compat.h>
  18. #if CONFIG_IS_ENABLED(DM_I2C)
  19. #include <dm.h>
  20. #endif
  21. DECLARE_GLOBAL_DATA_PTR;
  22. /*
  23. * Include a file that will provide CONFIG_I2C_MVTWSI_BASE*, and possibly other
  24. * settings
  25. */
  26. #if !CONFIG_IS_ENABLED(DM_I2C)
  27. #if defined(CONFIG_ARCH_ORION5X)
  28. #include <asm/arch/orion5x.h>
  29. #elif (defined(CONFIG_ARCH_KIRKWOOD) || defined(CONFIG_ARCH_MVEBU))
  30. #include <asm/arch/soc.h>
  31. #elif defined(CONFIG_ARCH_SUNXI)
  32. #include <asm/arch/i2c.h>
  33. #else
  34. #error Driver mvtwsi not supported by SoC or board
  35. #endif
  36. #endif /* CONFIG_DM_I2C */
  37. /*
  38. * On SUNXI, we get CONFIG_SYS_TCLK from this include, so we want to
  39. * always have it.
  40. */
  41. #if CONFIG_IS_ENABLED(DM_I2C) && defined(CONFIG_ARCH_SUNXI)
  42. #include <asm/arch/i2c.h>
  43. #endif
  44. /*
  45. * TWSI register structure
  46. */
  47. #ifdef CONFIG_ARCH_SUNXI
  48. struct mvtwsi_registers {
  49. u32 slave_address;
  50. u32 xtnd_slave_addr;
  51. u32 data;
  52. u32 control;
  53. u32 status;
  54. u32 baudrate;
  55. u32 soft_reset;
  56. u32 debug; /* Dummy field for build compatibility with mvebu */
  57. };
  58. #else
  59. struct mvtwsi_registers {
  60. u32 slave_address;
  61. u32 data;
  62. u32 control;
  63. union {
  64. u32 status; /* When reading */
  65. u32 baudrate; /* When writing */
  66. };
  67. u32 xtnd_slave_addr;
  68. u32 reserved0[2];
  69. u32 soft_reset;
  70. u32 reserved1[27];
  71. u32 debug;
  72. };
  73. #endif
  74. #if CONFIG_IS_ENABLED(DM_I2C)
  75. struct mvtwsi_i2c_dev {
  76. /* TWSI Register base for the device */
  77. struct mvtwsi_registers *base;
  78. /* Number of the device (determined from cell-index property) */
  79. int index;
  80. /* The I2C slave address for the device */
  81. u8 slaveadd;
  82. /* The configured I2C speed in Hz */
  83. uint speed;
  84. /* The current length of a clock period (depending on speed) */
  85. uint tick;
  86. };
  87. #endif /* CONFIG_DM_I2C */
  88. /*
  89. * enum mvtwsi_ctrl_register_fields - Bit masks for flags in the control
  90. * register
  91. */
  92. enum mvtwsi_ctrl_register_fields {
  93. /* Acknowledge bit */
  94. MVTWSI_CONTROL_ACK = 0x00000004,
  95. /* Interrupt flag */
  96. MVTWSI_CONTROL_IFLG = 0x00000008,
  97. /* Stop bit */
  98. MVTWSI_CONTROL_STOP = 0x00000010,
  99. /* Start bit */
  100. MVTWSI_CONTROL_START = 0x00000020,
  101. /* I2C enable */
  102. MVTWSI_CONTROL_TWSIEN = 0x00000040,
  103. /* Interrupt enable */
  104. MVTWSI_CONTROL_INTEN = 0x00000080,
  105. };
  106. /*
  107. * On sun6i and newer, IFLG is a write-clear bit, which is cleared by writing 1;
  108. * on other platforms, it is a normal r/w bit, which is cleared by writing 0.
  109. */
  110. #if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6)
  111. #define MVTWSI_CONTROL_CLEAR_IFLG 0x00000008
  112. #else
  113. #define MVTWSI_CONTROL_CLEAR_IFLG 0x00000000
  114. #endif
  115. /*
  116. * enum mvstwsi_status_values - Possible values of I2C controller's status
  117. * register
  118. *
  119. * Only those statuses expected in normal master operation on
  120. * non-10-bit-address devices are specified.
  121. *
  122. * Every status that's unexpected during normal operation (bus errors,
  123. * arbitration losses, missing ACKs...) is passed back to the caller as an error
  124. * code.
  125. */
  126. enum mvstwsi_status_values {
  127. /* START condition transmitted */
  128. MVTWSI_STATUS_START = 0x08,
  129. /* Repeated START condition transmitted */
  130. MVTWSI_STATUS_REPEATED_START = 0x10,
  131. /* Address + write bit transmitted, ACK received */
  132. MVTWSI_STATUS_ADDR_W_ACK = 0x18,
  133. /* Data transmitted, ACK received */
  134. MVTWSI_STATUS_DATA_W_ACK = 0x28,
  135. /* Address + read bit transmitted, ACK received */
  136. MVTWSI_STATUS_ADDR_R_ACK = 0x40,
  137. /* Address + read bit transmitted, ACK not received */
  138. MVTWSI_STATUS_ADDR_R_NAK = 0x48,
  139. /* Data received, ACK transmitted */
  140. MVTWSI_STATUS_DATA_R_ACK = 0x50,
  141. /* Data received, ACK not transmitted */
  142. MVTWSI_STATUS_DATA_R_NAK = 0x58,
  143. /* No relevant status */
  144. MVTWSI_STATUS_IDLE = 0xF8,
  145. };
  146. /*
  147. * enum mvstwsi_ack_flags - Determine whether a read byte should be
  148. * acknowledged or not.
  149. */
  150. enum mvtwsi_ack_flags {
  151. /* Send NAK after received byte */
  152. MVTWSI_READ_NAK = 0,
  153. /* Send ACK after received byte */
  154. MVTWSI_READ_ACK = 1,
  155. };
  156. /*
  157. * calc_tick() - Calculate the duration of a clock cycle from the I2C speed
  158. *
  159. * @speed: The speed in Hz to calculate the clock cycle duration for.
  160. * @return The duration of a clock cycle in ns.
  161. */
  162. inline uint calc_tick(uint speed)
  163. {
  164. /* One tick = the duration of a period at the specified speed in ns (we
  165. * add 100 ns to be on the safe side) */
  166. return (1000000000u / speed) + 100;
  167. }
  168. #if !CONFIG_IS_ENABLED(DM_I2C)
  169. /*
  170. * twsi_get_base() - Get controller register base for specified adapter
  171. *
  172. * @adap: Adapter to get the register base for.
  173. * @return Register base for the specified adapter.
  174. */
  175. static struct mvtwsi_registers *twsi_get_base(struct i2c_adapter *adap)
  176. {
  177. switch (adap->hwadapnr) {
  178. #ifdef CONFIG_I2C_MVTWSI_BASE0
  179. case 0:
  180. return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE0;
  181. #endif
  182. #ifdef CONFIG_I2C_MVTWSI_BASE1
  183. case 1:
  184. return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE1;
  185. #endif
  186. #ifdef CONFIG_I2C_MVTWSI_BASE2
  187. case 2:
  188. return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE2;
  189. #endif
  190. #ifdef CONFIG_I2C_MVTWSI_BASE3
  191. case 3:
  192. return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE3;
  193. #endif
  194. #ifdef CONFIG_I2C_MVTWSI_BASE4
  195. case 4:
  196. return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE4;
  197. #endif
  198. #ifdef CONFIG_I2C_MVTWSI_BASE5
  199. case 5:
  200. return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE5;
  201. #endif
  202. default:
  203. printf("Missing mvtwsi controller %d base\n", adap->hwadapnr);
  204. break;
  205. }
  206. return NULL;
  207. }
  208. #endif
  209. /*
  210. * enum mvtwsi_error_class - types of I2C errors
  211. */
  212. enum mvtwsi_error_class {
  213. /* The controller returned a different status than expected */
  214. MVTWSI_ERROR_WRONG_STATUS = 0x01,
  215. /* The controller timed out */
  216. MVTWSI_ERROR_TIMEOUT = 0x02,
  217. };
  218. /*
  219. * mvtwsi_error() - Build I2C return code from error information
  220. *
  221. * For debugging purposes, this function packs some information of an occurred
  222. * error into a return code. These error codes are returned from I2C API
  223. * functions (i2c_{read,write}, dm_i2c_{read,write}, etc.).
  224. *
  225. * @ec: The error class of the error (enum mvtwsi_error_class).
  226. * @lc: The last value of the control register.
  227. * @ls: The last value of the status register.
  228. * @es: The expected value of the status register.
  229. * @return The generated error code.
  230. */
  231. inline uint mvtwsi_error(uint ec, uint lc, uint ls, uint es)
  232. {
  233. return ((ec << 24) & 0xFF000000)
  234. | ((lc << 16) & 0x00FF0000)
  235. | ((ls << 8) & 0x0000FF00)
  236. | (es & 0xFF);
  237. }
  238. /*
  239. * twsi_wait() - Wait for I2C bus interrupt flag and check status, or time out.
  240. *
  241. * @return Zero if status is as expected, or a non-zero code if either a time
  242. * out occurred, or the status was not the expected one.
  243. */
  244. static int twsi_wait(struct mvtwsi_registers *twsi, int expected_status,
  245. uint tick)
  246. {
  247. int control, status;
  248. int timeout = 1000;
  249. do {
  250. control = readl(&twsi->control);
  251. if (control & MVTWSI_CONTROL_IFLG) {
  252. /*
  253. * On Armada 38x it seems that the controller works as
  254. * if it first set the MVTWSI_CONTROL_IFLAG in the
  255. * control register and only after that it changed the
  256. * status register.
  257. * This sometimes caused weird bugs which only appeared
  258. * on selected I2C speeds and even then only sometimes.
  259. * We therefore add here a simple ndealy(100), which
  260. * seems to fix this weird bug.
  261. */
  262. ndelay(100);
  263. status = readl(&twsi->status);
  264. if (status == expected_status)
  265. return 0;
  266. else
  267. return mvtwsi_error(
  268. MVTWSI_ERROR_WRONG_STATUS,
  269. control, status, expected_status);
  270. }
  271. ndelay(tick); /* One clock cycle */
  272. } while (timeout--);
  273. status = readl(&twsi->status);
  274. return mvtwsi_error(MVTWSI_ERROR_TIMEOUT, control, status,
  275. expected_status);
  276. }
  277. /*
  278. * twsi_start() - Assert a START condition on the bus.
  279. *
  280. * This function is used in both single I2C transactions and inside
  281. * back-to-back transactions (repeated starts).
  282. *
  283. * @twsi: The MVTWSI register structure to use.
  284. * @expected_status: The I2C bus status expected to be asserted after the
  285. * operation completion.
  286. * @tick: The duration of a clock cycle at the current I2C speed.
  287. * @return Zero if status is as expected, or a non-zero code if either a time
  288. * out occurred or the status was not the expected one.
  289. */
  290. static int twsi_start(struct mvtwsi_registers *twsi, int expected_status,
  291. uint tick)
  292. {
  293. /* Assert START */
  294. writel(MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_START |
  295. MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
  296. /* Wait for controller to process START */
  297. return twsi_wait(twsi, expected_status, tick);
  298. }
  299. /*
  300. * twsi_send() - Send a byte on the I2C bus.
  301. *
  302. * The byte may be part of an address byte or data.
  303. *
  304. * @twsi: The MVTWSI register structure to use.
  305. * @byte: The byte to send.
  306. * @expected_status: The I2C bus status expected to be asserted after the
  307. * operation completion.
  308. * @tick: The duration of a clock cycle at the current I2C speed.
  309. * @return Zero if status is as expected, or a non-zero code if either a time
  310. * out occurred or the status was not the expected one.
  311. */
  312. static int twsi_send(struct mvtwsi_registers *twsi, u8 byte,
  313. int expected_status, uint tick)
  314. {
  315. /* Write byte to data register for sending */
  316. writel(byte, &twsi->data);
  317. /* Clear any pending interrupt -- that will cause sending */
  318. writel(MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_CLEAR_IFLG,
  319. &twsi->control);
  320. /* Wait for controller to receive byte, and check ACK */
  321. return twsi_wait(twsi, expected_status, tick);
  322. }
  323. /*
  324. * twsi_recv() - Receive a byte on the I2C bus.
  325. *
  326. * The static variable mvtwsi_control_flags controls whether we ack or nak.
  327. *
  328. * @twsi: The MVTWSI register structure to use.
  329. * @byte: The byte to send.
  330. * @ack_flag: Flag that determines whether the received byte should
  331. * be acknowledged by the controller or not (sent ACK/NAK).
  332. * @tick: The duration of a clock cycle at the current I2C speed.
  333. * @return Zero if status is as expected, or a non-zero code if either a time
  334. * out occurred or the status was not the expected one.
  335. */
  336. static int twsi_recv(struct mvtwsi_registers *twsi, u8 *byte, int ack_flag,
  337. uint tick)
  338. {
  339. int expected_status, status, control;
  340. /* Compute expected status based on passed ACK flag */
  341. expected_status = ack_flag ? MVTWSI_STATUS_DATA_R_ACK :
  342. MVTWSI_STATUS_DATA_R_NAK;
  343. /* Acknowledge *previous state*, and launch receive */
  344. control = MVTWSI_CONTROL_TWSIEN;
  345. control |= ack_flag == MVTWSI_READ_ACK ? MVTWSI_CONTROL_ACK : 0;
  346. writel(control | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
  347. /* Wait for controller to receive byte, and assert ACK or NAK */
  348. status = twsi_wait(twsi, expected_status, tick);
  349. /* If we did receive the expected byte, store it */
  350. if (status == 0)
  351. *byte = readl(&twsi->data);
  352. return status;
  353. }
  354. /*
  355. * twsi_stop() - Assert a STOP condition on the bus.
  356. *
  357. * This function is also used to force the bus back to idle state (SDA =
  358. * SCL = 1).
  359. *
  360. * @twsi: The MVTWSI register structure to use.
  361. * @tick: The duration of a clock cycle at the current I2C speed.
  362. * @return Zero if the operation succeeded, or a non-zero code if a time out
  363. * occurred.
  364. */
  365. static int twsi_stop(struct mvtwsi_registers *twsi, uint tick)
  366. {
  367. int control, stop_status;
  368. int status = 0;
  369. int timeout = 1000;
  370. /* Assert STOP */
  371. control = MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_STOP;
  372. writel(control | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
  373. /* Wait for IDLE; IFLG won't rise, so we can't use twsi_wait() */
  374. do {
  375. stop_status = readl(&twsi->status);
  376. if (stop_status == MVTWSI_STATUS_IDLE)
  377. break;
  378. ndelay(tick); /* One clock cycle */
  379. } while (timeout--);
  380. control = readl(&twsi->control);
  381. if (stop_status != MVTWSI_STATUS_IDLE)
  382. status = mvtwsi_error(MVTWSI_ERROR_TIMEOUT,
  383. control, status, MVTWSI_STATUS_IDLE);
  384. return status;
  385. }
  386. /*
  387. * twsi_calc_freq() - Compute I2C frequency depending on m and n parameters.
  388. *
  389. * @n: Parameter 'n' for the frequency calculation algorithm.
  390. * @m: Parameter 'm' for the frequency calculation algorithm.
  391. * @return The I2C frequency corresponding to the passed m and n parameters.
  392. */
  393. static uint twsi_calc_freq(const int n, const int m)
  394. {
  395. #ifdef CONFIG_ARCH_SUNXI
  396. return CONFIG_SYS_TCLK / (10 * (m + 1) * (1 << n));
  397. #else
  398. return CONFIG_SYS_TCLK / (10 * (m + 1) * (2 << n));
  399. #endif
  400. }
  401. /*
  402. * twsi_reset() - Reset the I2C controller.
  403. *
  404. * Resetting the controller also resets the baud rate and slave address, hence
  405. * they must be re-established after the reset.
  406. *
  407. * @twsi: The MVTWSI register structure to use.
  408. */
  409. static void twsi_reset(struct mvtwsi_registers *twsi)
  410. {
  411. /* Reset controller */
  412. writel(0, &twsi->soft_reset);
  413. /* Wait 2 ms -- this is what the Marvell LSP does */
  414. udelay(20000);
  415. }
  416. /*
  417. * __twsi_i2c_set_bus_speed() - Set the speed of the I2C controller.
  418. *
  419. * This function sets baud rate to the highest possible value that does not
  420. * exceed the requested rate.
  421. *
  422. * @twsi: The MVTWSI register structure to use.
  423. * @requested_speed: The desired frequency the controller should run at
  424. * in Hz.
  425. * @return The actual frequency the controller was configured to.
  426. */
  427. static uint __twsi_i2c_set_bus_speed(struct mvtwsi_registers *twsi,
  428. uint requested_speed)
  429. {
  430. uint tmp_speed, highest_speed, n, m;
  431. uint baud = 0x44; /* Baud rate after controller reset */
  432. highest_speed = 0;
  433. /* Successively try m, n combinations, and use the combination
  434. * resulting in the largest speed that's not above the requested
  435. * speed */
  436. for (n = 0; n < 8; n++) {
  437. for (m = 0; m < 16; m++) {
  438. tmp_speed = twsi_calc_freq(n, m);
  439. if ((tmp_speed <= requested_speed) &&
  440. (tmp_speed > highest_speed)) {
  441. highest_speed = tmp_speed;
  442. baud = (m << 3) | n;
  443. }
  444. }
  445. }
  446. writel(baud, &twsi->baudrate);
  447. /* Wait for controller for one tick */
  448. #if CONFIG_IS_ENABLED(DM_I2C)
  449. ndelay(calc_tick(highest_speed));
  450. #else
  451. ndelay(10000);
  452. #endif
  453. return highest_speed;
  454. }
  455. /*
  456. * __twsi_i2c_init() - Initialize the I2C controller.
  457. *
  458. * @twsi: The MVTWSI register structure to use.
  459. * @speed: The initial frequency the controller should run at
  460. * in Hz.
  461. * @slaveadd: The I2C address to be set for the I2C master.
  462. * @actual_speed: A output parameter that receives the actual frequency
  463. * in Hz the controller was set to by the function.
  464. * @return Zero if the operation succeeded, or a non-zero code if a time out
  465. * occurred.
  466. */
  467. static void __twsi_i2c_init(struct mvtwsi_registers *twsi, int speed,
  468. int slaveadd, uint *actual_speed)
  469. {
  470. uint tmp_speed;
  471. /* Reset controller */
  472. twsi_reset(twsi);
  473. /* Set speed */
  474. tmp_speed = __twsi_i2c_set_bus_speed(twsi, speed);
  475. if (actual_speed)
  476. *actual_speed = tmp_speed;
  477. /* Set slave address; even though we don't use it */
  478. writel(slaveadd, &twsi->slave_address);
  479. writel(0, &twsi->xtnd_slave_addr);
  480. /* Assert STOP, but don't care for the result */
  481. #if CONFIG_IS_ENABLED(DM_I2C)
  482. (void) twsi_stop(twsi, calc_tick(*actual_speed));
  483. #else
  484. (void) twsi_stop(twsi, 10000);
  485. #endif
  486. }
  487. /*
  488. * i2c_begin() - Start a I2C transaction.
  489. *
  490. * Begin a I2C transaction with a given expected start status and chip address.
  491. * A START is asserted, and the address byte is sent to the I2C controller. The
  492. * expected address status will be derived from the direction bit (bit 0) of
  493. * the address byte.
  494. *
  495. * @twsi: The MVTWSI register structure to use.
  496. * @expected_start_status: The I2C status the controller is expected to
  497. * assert after the address byte was sent.
  498. * @addr: The address byte to be sent.
  499. * @tick: The duration of a clock cycle at the current
  500. * I2C speed.
  501. * @return Zero if the operation succeeded, or a non-zero code if a time out or
  502. * unexpected I2C status occurred.
  503. */
  504. static int i2c_begin(struct mvtwsi_registers *twsi, int expected_start_status,
  505. u8 addr, uint tick)
  506. {
  507. int status, expected_addr_status;
  508. /* Compute the expected address status from the direction bit in
  509. * the address byte */
  510. if (addr & 1) /* Reading */
  511. expected_addr_status = MVTWSI_STATUS_ADDR_R_ACK;
  512. else /* Writing */
  513. expected_addr_status = MVTWSI_STATUS_ADDR_W_ACK;
  514. /* Assert START */
  515. status = twsi_start(twsi, expected_start_status, tick);
  516. /* Send out the address if the start went well */
  517. if (status == 0)
  518. status = twsi_send(twsi, addr, expected_addr_status, tick);
  519. /* Return 0, or the status of the first failure */
  520. return status;
  521. }
  522. /*
  523. * __twsi_i2c_probe_chip() - Probe the given I2C chip address.
  524. *
  525. * This function begins a I2C read transaction, does a dummy read and NAKs; if
  526. * the procedure succeeds, the chip is considered to be present.
  527. *
  528. * @twsi: The MVTWSI register structure to use.
  529. * @chip: The chip address to probe.
  530. * @tick: The duration of a clock cycle at the current I2C speed.
  531. * @return Zero if the operation succeeded, or a non-zero code if a time out or
  532. * unexpected I2C status occurred.
  533. */
  534. static int __twsi_i2c_probe_chip(struct mvtwsi_registers *twsi, uchar chip,
  535. uint tick)
  536. {
  537. u8 dummy_byte;
  538. int status;
  539. /* Begin i2c read */
  540. status = i2c_begin(twsi, MVTWSI_STATUS_START, (chip << 1) | 1, tick);
  541. /* Dummy read was accepted: receive byte, but NAK it. */
  542. if (status == 0)
  543. status = twsi_recv(twsi, &dummy_byte, MVTWSI_READ_NAK, tick);
  544. /* Stop transaction */
  545. twsi_stop(twsi, tick);
  546. /* Return 0, or the status of the first failure */
  547. return status;
  548. }
  549. /*
  550. * __twsi_i2c_read() - Read data from a I2C chip.
  551. *
  552. * This function begins a I2C write transaction, and transmits the address
  553. * bytes; then begins a I2C read transaction, and receives the data bytes.
  554. *
  555. * NOTE: Some devices want a stop right before the second start, while some
  556. * will choke if it is there. Since deciding this is not yet supported in
  557. * higher level APIs, we need to make a decision here, and for the moment that
  558. * will be a repeated start without a preceding stop.
  559. *
  560. * @twsi: The MVTWSI register structure to use.
  561. * @chip: The chip address to read from.
  562. * @addr: The address bytes to send.
  563. * @alen: The length of the address bytes in bytes.
  564. * @data: The buffer to receive the data read from the chip (has to have
  565. * a size of at least 'length' bytes).
  566. * @length: The amount of data to be read from the chip in bytes.
  567. * @tick: The duration of a clock cycle at the current I2C speed.
  568. * @return Zero if the operation succeeded, or a non-zero code if a time out or
  569. * unexpected I2C status occurred.
  570. */
  571. static int __twsi_i2c_read(struct mvtwsi_registers *twsi, uchar chip,
  572. u8 *addr, int alen, uchar *data, int length,
  573. uint tick)
  574. {
  575. int status = 0;
  576. int stop_status;
  577. int expected_start = MVTWSI_STATUS_START;
  578. if (alen > 0) {
  579. /* Begin i2c write to send the address bytes */
  580. status = i2c_begin(twsi, expected_start, (chip << 1), tick);
  581. /* Send address bytes */
  582. while ((status == 0) && alen--)
  583. status = twsi_send(twsi, addr[alen],
  584. MVTWSI_STATUS_DATA_W_ACK, tick);
  585. /* Send repeated STARTs after the initial START */
  586. expected_start = MVTWSI_STATUS_REPEATED_START;
  587. }
  588. /* Begin i2c read to receive data bytes */
  589. if (status == 0)
  590. status = i2c_begin(twsi, expected_start, (chip << 1) | 1, tick);
  591. /* Receive actual data bytes; set NAK if we if we have nothing more to
  592. * read */
  593. while ((status == 0) && length--)
  594. status = twsi_recv(twsi, data++,
  595. length > 0 ?
  596. MVTWSI_READ_ACK : MVTWSI_READ_NAK, tick);
  597. /* Stop transaction */
  598. stop_status = twsi_stop(twsi, tick);
  599. /* Return 0, or the status of the first failure */
  600. return status != 0 ? status : stop_status;
  601. }
  602. /*
  603. * __twsi_i2c_write() - Send data to a I2C chip.
  604. *
  605. * This function begins a I2C write transaction, and transmits the address
  606. * bytes; then begins a new I2C write transaction, and sends the data bytes.
  607. *
  608. * @twsi: The MVTWSI register structure to use.
  609. * @chip: The chip address to read from.
  610. * @addr: The address bytes to send.
  611. * @alen: The length of the address bytes in bytes.
  612. * @data: The buffer containing the data to be sent to the chip.
  613. * @length: The length of data to be sent to the chip in bytes.
  614. * @tick: The duration of a clock cycle at the current I2C speed.
  615. * @return Zero if the operation succeeded, or a non-zero code if a time out or
  616. * unexpected I2C status occurred.
  617. */
  618. static int __twsi_i2c_write(struct mvtwsi_registers *twsi, uchar chip,
  619. u8 *addr, int alen, uchar *data, int length,
  620. uint tick)
  621. {
  622. int status, stop_status;
  623. /* Begin i2c write to send first the address bytes, then the
  624. * data bytes */
  625. status = i2c_begin(twsi, MVTWSI_STATUS_START, (chip << 1), tick);
  626. /* Send address bytes */
  627. while ((status == 0) && (alen-- > 0))
  628. status = twsi_send(twsi, addr[alen], MVTWSI_STATUS_DATA_W_ACK,
  629. tick);
  630. /* Send data bytes */
  631. while ((status == 0) && (length-- > 0))
  632. status = twsi_send(twsi, *(data++), MVTWSI_STATUS_DATA_W_ACK,
  633. tick);
  634. /* Stop transaction */
  635. stop_status = twsi_stop(twsi, tick);
  636. /* Return 0, or the status of the first failure */
  637. return status != 0 ? status : stop_status;
  638. }
  639. #if !CONFIG_IS_ENABLED(DM_I2C)
  640. static void twsi_i2c_init(struct i2c_adapter *adap, int speed,
  641. int slaveadd)
  642. {
  643. struct mvtwsi_registers *twsi = twsi_get_base(adap);
  644. __twsi_i2c_init(twsi, speed, slaveadd, NULL);
  645. }
  646. static uint twsi_i2c_set_bus_speed(struct i2c_adapter *adap,
  647. uint requested_speed)
  648. {
  649. struct mvtwsi_registers *twsi = twsi_get_base(adap);
  650. __twsi_i2c_set_bus_speed(twsi, requested_speed);
  651. return 0;
  652. }
  653. static int twsi_i2c_probe(struct i2c_adapter *adap, uchar chip)
  654. {
  655. struct mvtwsi_registers *twsi = twsi_get_base(adap);
  656. return __twsi_i2c_probe_chip(twsi, chip, 10000);
  657. }
  658. static int twsi_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
  659. int alen, uchar *data, int length)
  660. {
  661. struct mvtwsi_registers *twsi = twsi_get_base(adap);
  662. u8 addr_bytes[4];
  663. addr_bytes[0] = (addr >> 0) & 0xFF;
  664. addr_bytes[1] = (addr >> 8) & 0xFF;
  665. addr_bytes[2] = (addr >> 16) & 0xFF;
  666. addr_bytes[3] = (addr >> 24) & 0xFF;
  667. return __twsi_i2c_read(twsi, chip, addr_bytes, alen, data, length,
  668. 10000);
  669. }
  670. static int twsi_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
  671. int alen, uchar *data, int length)
  672. {
  673. struct mvtwsi_registers *twsi = twsi_get_base(adap);
  674. u8 addr_bytes[4];
  675. addr_bytes[0] = (addr >> 0) & 0xFF;
  676. addr_bytes[1] = (addr >> 8) & 0xFF;
  677. addr_bytes[2] = (addr >> 16) & 0xFF;
  678. addr_bytes[3] = (addr >> 24) & 0xFF;
  679. return __twsi_i2c_write(twsi, chip, addr_bytes, alen, data, length,
  680. 10000);
  681. }
  682. #ifdef CONFIG_I2C_MVTWSI_BASE0
  683. U_BOOT_I2C_ADAP_COMPLETE(twsi0, twsi_i2c_init, twsi_i2c_probe,
  684. twsi_i2c_read, twsi_i2c_write,
  685. twsi_i2c_set_bus_speed,
  686. CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
  687. #endif
  688. #ifdef CONFIG_I2C_MVTWSI_BASE1
  689. U_BOOT_I2C_ADAP_COMPLETE(twsi1, twsi_i2c_init, twsi_i2c_probe,
  690. twsi_i2c_read, twsi_i2c_write,
  691. twsi_i2c_set_bus_speed,
  692. CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 1)
  693. #endif
  694. #ifdef CONFIG_I2C_MVTWSI_BASE2
  695. U_BOOT_I2C_ADAP_COMPLETE(twsi2, twsi_i2c_init, twsi_i2c_probe,
  696. twsi_i2c_read, twsi_i2c_write,
  697. twsi_i2c_set_bus_speed,
  698. CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 2)
  699. #endif
  700. #ifdef CONFIG_I2C_MVTWSI_BASE3
  701. U_BOOT_I2C_ADAP_COMPLETE(twsi3, twsi_i2c_init, twsi_i2c_probe,
  702. twsi_i2c_read, twsi_i2c_write,
  703. twsi_i2c_set_bus_speed,
  704. CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 3)
  705. #endif
  706. #ifdef CONFIG_I2C_MVTWSI_BASE4
  707. U_BOOT_I2C_ADAP_COMPLETE(twsi4, twsi_i2c_init, twsi_i2c_probe,
  708. twsi_i2c_read, twsi_i2c_write,
  709. twsi_i2c_set_bus_speed,
  710. CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 4)
  711. #endif
  712. #ifdef CONFIG_I2C_MVTWSI_BASE5
  713. U_BOOT_I2C_ADAP_COMPLETE(twsi5, twsi_i2c_init, twsi_i2c_probe,
  714. twsi_i2c_read, twsi_i2c_write,
  715. twsi_i2c_set_bus_speed,
  716. CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 5)
  717. #endif
  718. #else /* CONFIG_DM_I2C */
  719. static int mvtwsi_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
  720. u32 chip_flags)
  721. {
  722. struct mvtwsi_i2c_dev *dev = dev_get_priv(bus);
  723. return __twsi_i2c_probe_chip(dev->base, chip_addr, dev->tick);
  724. }
  725. static int mvtwsi_i2c_set_bus_speed(struct udevice *bus, uint speed)
  726. {
  727. struct mvtwsi_i2c_dev *dev = dev_get_priv(bus);
  728. dev->speed = __twsi_i2c_set_bus_speed(dev->base, speed);
  729. dev->tick = calc_tick(dev->speed);
  730. return 0;
  731. }
  732. static int mvtwsi_i2c_of_to_plat(struct udevice *bus)
  733. {
  734. struct mvtwsi_i2c_dev *dev = dev_get_priv(bus);
  735. dev->base = dev_read_addr_ptr(bus);
  736. if (!dev->base)
  737. return -ENOMEM;
  738. dev->index = fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus),
  739. "cell-index", -1);
  740. dev->slaveadd = fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus),
  741. "u-boot,i2c-slave-addr", 0x0);
  742. dev->speed = dev_read_u32_default(bus, "clock-frequency",
  743. I2C_SPEED_STANDARD_RATE);
  744. return 0;
  745. }
  746. static void twsi_disable_i2c_slave(struct mvtwsi_registers *twsi)
  747. {
  748. clrbits_le32(&twsi->debug, BIT(18));
  749. }
  750. static int mvtwsi_i2c_bind(struct udevice *bus)
  751. {
  752. struct mvtwsi_registers *twsi = dev_read_addr_ptr(bus);
  753. /* Disable the hidden slave in i2c0 of these platforms */
  754. if ((IS_ENABLED(CONFIG_ARMADA_38X) ||
  755. IS_ENABLED(CONFIG_ARCH_KIRKWOOD) ||
  756. IS_ENABLED(CONFIG_ARMADA_8K)) && !dev_seq(bus))
  757. twsi_disable_i2c_slave(twsi);
  758. return 0;
  759. }
  760. static int mvtwsi_i2c_probe(struct udevice *bus)
  761. {
  762. struct mvtwsi_i2c_dev *dev = dev_get_priv(bus);
  763. uint actual_speed;
  764. __twsi_i2c_init(dev->base, dev->speed, dev->slaveadd, &actual_speed);
  765. dev->speed = actual_speed;
  766. dev->tick = calc_tick(dev->speed);
  767. return 0;
  768. }
  769. static int mvtwsi_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
  770. {
  771. struct mvtwsi_i2c_dev *dev = dev_get_priv(bus);
  772. struct i2c_msg *dmsg, *omsg, dummy;
  773. memset(&dummy, 0, sizeof(struct i2c_msg));
  774. /* We expect either two messages (one with an offset and one with the
  775. * actual data) or one message (just data or offset/data combined) */
  776. if (nmsgs > 2 || nmsgs == 0) {
  777. debug("%s: Only one or two messages are supported.", __func__);
  778. return -1;
  779. }
  780. omsg = nmsgs == 1 ? &dummy : msg;
  781. dmsg = nmsgs == 1 ? msg : msg + 1;
  782. if (dmsg->flags & I2C_M_RD)
  783. return __twsi_i2c_read(dev->base, dmsg->addr, omsg->buf,
  784. omsg->len, dmsg->buf, dmsg->len,
  785. dev->tick);
  786. else
  787. return __twsi_i2c_write(dev->base, dmsg->addr, omsg->buf,
  788. omsg->len, dmsg->buf, dmsg->len,
  789. dev->tick);
  790. }
  791. static const struct dm_i2c_ops mvtwsi_i2c_ops = {
  792. .xfer = mvtwsi_i2c_xfer,
  793. .probe_chip = mvtwsi_i2c_probe_chip,
  794. .set_bus_speed = mvtwsi_i2c_set_bus_speed,
  795. };
  796. static const struct udevice_id mvtwsi_i2c_ids[] = {
  797. { .compatible = "marvell,mv64xxx-i2c", },
  798. { .compatible = "marvell,mv78230-i2c", },
  799. { .compatible = "allwinner,sun6i-a31-i2c", },
  800. { /* sentinel */ }
  801. };
  802. U_BOOT_DRIVER(i2c_mvtwsi) = {
  803. .name = "i2c_mvtwsi",
  804. .id = UCLASS_I2C,
  805. .of_match = mvtwsi_i2c_ids,
  806. .bind = mvtwsi_i2c_bind,
  807. .probe = mvtwsi_i2c_probe,
  808. .of_to_plat = mvtwsi_i2c_of_to_plat,
  809. .priv_auto = sizeof(struct mvtwsi_i2c_dev),
  810. .ops = &mvtwsi_i2c_ops,
  811. };
  812. #endif /* CONFIG_DM_I2C */