mv_i2c.h 2.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2011
  4. * Marvell Inc, <www.marvell.com>
  5. */
  6. #ifndef _MV_I2C_H_
  7. #define _MV_I2C_H_
  8. extern void i2c_clk_enable(void);
  9. /* Shall the current transfer have a start/stop condition? */
  10. #define I2C_COND_NORMAL 0
  11. #define I2C_COND_START 1
  12. #define I2C_COND_STOP 2
  13. /* Shall the current transfer be ack/nacked or being waited for it? */
  14. #define I2C_ACKNAK_WAITACK 1
  15. #define I2C_ACKNAK_SENDACK 2
  16. #define I2C_ACKNAK_SENDNAK 4
  17. /* Specify who shall transfer the data (master or slave) */
  18. #define I2C_READ 0
  19. #define I2C_WRITE 1
  20. #define I2C_ICR_INIT (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE)
  21. #define I2C_ISR_INIT 0x7FF
  22. /* ----- Control register bits ---------------------------------------- */
  23. #define ICR_START 0x1 /* start bit */
  24. #define ICR_STOP 0x2 /* stop bit */
  25. #define ICR_ACKNAK 0x4 /* send ACK(0) or NAK(1) */
  26. #define ICR_TB 0x8 /* transfer byte bit */
  27. #define ICR_MA 0x10 /* master abort */
  28. #define ICR_SCLE 0x20 /* master clock enable, mona SCLEA */
  29. #define ICR_IUE 0x40 /* unit enable */
  30. #define ICR_GCD 0x80 /* general call disable */
  31. #define ICR_ITEIE 0x100 /* enable tx interrupts */
  32. #define ICR_IRFIE 0x200 /* enable rx interrupts, mona: DRFIE */
  33. #define ICR_BEIE 0x400 /* enable bus error ints */
  34. #define ICR_SSDIE 0x800 /* slave STOP detected int enable */
  35. #define ICR_ALDIE 0x1000 /* enable arbitration interrupt */
  36. #define ICR_SADIE 0x2000 /* slave address detected int enable */
  37. #define ICR_UR 0x4000 /* unit reset */
  38. #ifdef CONFIG_ARMADA_3700
  39. #define ICR_SM 0x00000 /* Standard Mode */
  40. #define ICR_FM 0x10000 /* Fast Mode */
  41. #define ICR_MODE_MASK 0x30000 /* Mode mask */
  42. #else
  43. #define ICR_SM 0x00000 /* Standard Mode */
  44. #define ICR_FM 0x08000 /* Fast Mode */
  45. #define ICR_MODE_MASK 0x18000 /* Mode mask */
  46. #endif
  47. /* ----- Status register bits ----------------------------------------- */
  48. #define ISR_RWM 0x1 /* read/write mode */
  49. #define ISR_ACKNAK 0x2 /* ack/nak status */
  50. #define ISR_UB 0x4 /* unit busy */
  51. #define ISR_IBB 0x8 /* bus busy */
  52. #define ISR_SSD 0x10 /* slave stop detected */
  53. #define ISR_ALD 0x20 /* arbitration loss detected */
  54. #define ISR_ITE 0x40 /* tx buffer empty */
  55. #define ISR_IRF 0x80 /* rx buffer full */
  56. #define ISR_GCAD 0x100 /* general call address detected */
  57. #define ISR_SAD 0x200 /* slave address detected */
  58. #define ISR_BED 0x400 /* bus error no ACK/NAK */
  59. #endif