mv_i2c.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2000
  4. * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
  5. *
  6. * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  7. * Marius Groeger <mgroeger@sysgo.de>
  8. *
  9. * (C) Copyright 2003 Pengutronix e.K.
  10. * Robert Schwebel <r.schwebel@pengutronix.de>
  11. *
  12. * (C) Copyright 2011 Marvell Inc.
  13. * Lei Wen <leiwen@marvell.com>
  14. *
  15. * Back ported to the 8xx platform (from the 8260 platform) by
  16. * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
  17. */
  18. #include <common.h>
  19. #include <dm.h>
  20. #include <i2c.h>
  21. #include <log.h>
  22. #include <asm/io.h>
  23. #include <linux/delay.h>
  24. #include "mv_i2c.h"
  25. /* All transfers are described by this data structure */
  26. struct mv_i2c_msg {
  27. u8 condition;
  28. u8 acknack;
  29. u8 direction;
  30. u8 data;
  31. };
  32. #ifdef CONFIG_ARMADA_3700
  33. /* Armada 3700 has no padding between the registers */
  34. struct mv_i2c {
  35. u32 ibmr;
  36. u32 idbr;
  37. u32 icr;
  38. u32 isr;
  39. u32 isar;
  40. };
  41. #else
  42. struct mv_i2c {
  43. u32 ibmr;
  44. u32 pad0;
  45. u32 idbr;
  46. u32 pad1;
  47. u32 icr;
  48. u32 pad2;
  49. u32 isr;
  50. u32 pad3;
  51. u32 isar;
  52. };
  53. #endif
  54. /*
  55. * Dummy implementation that can be overwritten by a board
  56. * specific function
  57. */
  58. __weak void i2c_clk_enable(void)
  59. {
  60. }
  61. /*
  62. * i2c_reset: - reset the host controller
  63. *
  64. */
  65. static void i2c_reset(struct mv_i2c *base)
  66. {
  67. u32 icr_mode;
  68. /* Save bus mode (standard or fast speed) for later use */
  69. icr_mode = readl(&base->icr) & ICR_MODE_MASK;
  70. writel(readl(&base->icr) & ~ICR_IUE, &base->icr); /* disable unit */
  71. writel(readl(&base->icr) | ICR_UR, &base->icr); /* reset the unit */
  72. udelay(100);
  73. writel(readl(&base->icr) & ~ICR_IUE, &base->icr); /* disable unit */
  74. i2c_clk_enable();
  75. writel(CONFIG_SYS_I2C_SLAVE, &base->isar); /* set our slave address */
  76. /* set control reg values */
  77. writel(I2C_ICR_INIT | icr_mode, &base->icr);
  78. writel(I2C_ISR_INIT, &base->isr); /* set clear interrupt bits */
  79. writel(readl(&base->icr) | ICR_IUE, &base->icr); /* enable unit */
  80. udelay(100);
  81. }
  82. /*
  83. * i2c_isr_set_cleared: - wait until certain bits of the I2C status register
  84. * are set and cleared
  85. *
  86. * @return: 1 in case of success, 0 means timeout (no match within 10 ms).
  87. */
  88. static int i2c_isr_set_cleared(struct mv_i2c *base, unsigned long set_mask,
  89. unsigned long cleared_mask)
  90. {
  91. int timeout = 1000, isr;
  92. do {
  93. isr = readl(&base->isr);
  94. udelay(10);
  95. if (timeout-- < 0)
  96. return 0;
  97. } while (((isr & set_mask) != set_mask)
  98. || ((isr & cleared_mask) != 0));
  99. return 1;
  100. }
  101. /*
  102. * i2c_transfer: - Transfer one byte over the i2c bus
  103. *
  104. * This function can tranfer a byte over the i2c bus in both directions.
  105. * It is used by the public API functions.
  106. *
  107. * @return: 0: transfer successful
  108. * -1: message is empty
  109. * -2: transmit timeout
  110. * -3: ACK missing
  111. * -4: receive timeout
  112. * -5: illegal parameters
  113. * -6: bus is busy and couldn't be aquired
  114. */
  115. static int i2c_transfer(struct mv_i2c *base, struct mv_i2c_msg *msg)
  116. {
  117. int ret;
  118. if (!msg)
  119. goto transfer_error_msg_empty;
  120. switch (msg->direction) {
  121. case I2C_WRITE:
  122. /* check if bus is not busy */
  123. if (!i2c_isr_set_cleared(base, 0, ISR_IBB))
  124. goto transfer_error_bus_busy;
  125. /* start transmission */
  126. writel(readl(&base->icr) & ~ICR_START, &base->icr);
  127. writel(readl(&base->icr) & ~ICR_STOP, &base->icr);
  128. writel(msg->data, &base->idbr);
  129. if (msg->condition == I2C_COND_START)
  130. writel(readl(&base->icr) | ICR_START, &base->icr);
  131. if (msg->condition == I2C_COND_STOP)
  132. writel(readl(&base->icr) | ICR_STOP, &base->icr);
  133. if (msg->acknack == I2C_ACKNAK_SENDNAK)
  134. writel(readl(&base->icr) | ICR_ACKNAK, &base->icr);
  135. if (msg->acknack == I2C_ACKNAK_SENDACK)
  136. writel(readl(&base->icr) & ~ICR_ACKNAK, &base->icr);
  137. writel(readl(&base->icr) & ~ICR_ALDIE, &base->icr);
  138. writel(readl(&base->icr) | ICR_TB, &base->icr);
  139. /* transmit register empty? */
  140. if (!i2c_isr_set_cleared(base, ISR_ITE, 0))
  141. goto transfer_error_transmit_timeout;
  142. /* clear 'transmit empty' state */
  143. writel(readl(&base->isr) | ISR_ITE, &base->isr);
  144. /* wait for ACK from slave */
  145. if (msg->acknack == I2C_ACKNAK_WAITACK)
  146. if (!i2c_isr_set_cleared(base, 0, ISR_ACKNAK))
  147. goto transfer_error_ack_missing;
  148. break;
  149. case I2C_READ:
  150. /* check if bus is not busy */
  151. if (!i2c_isr_set_cleared(base, 0, ISR_IBB))
  152. goto transfer_error_bus_busy;
  153. /* start receive */
  154. writel(readl(&base->icr) & ~ICR_START, &base->icr);
  155. writel(readl(&base->icr) & ~ICR_STOP, &base->icr);
  156. if (msg->condition == I2C_COND_START)
  157. writel(readl(&base->icr) | ICR_START, &base->icr);
  158. if (msg->condition == I2C_COND_STOP)
  159. writel(readl(&base->icr) | ICR_STOP, &base->icr);
  160. if (msg->acknack == I2C_ACKNAK_SENDNAK)
  161. writel(readl(&base->icr) | ICR_ACKNAK, &base->icr);
  162. if (msg->acknack == I2C_ACKNAK_SENDACK)
  163. writel(readl(&base->icr) & ~ICR_ACKNAK, &base->icr);
  164. writel(readl(&base->icr) & ~ICR_ALDIE, &base->icr);
  165. writel(readl(&base->icr) | ICR_TB, &base->icr);
  166. /* receive register full? */
  167. if (!i2c_isr_set_cleared(base, ISR_IRF, 0))
  168. goto transfer_error_receive_timeout;
  169. msg->data = readl(&base->idbr);
  170. /* clear 'receive empty' state */
  171. writel(readl(&base->isr) | ISR_IRF, &base->isr);
  172. break;
  173. default:
  174. goto transfer_error_illegal_param;
  175. }
  176. return 0;
  177. transfer_error_msg_empty:
  178. debug("i2c_transfer: error: 'msg' is empty\n");
  179. ret = -1;
  180. goto i2c_transfer_finish;
  181. transfer_error_transmit_timeout:
  182. debug("i2c_transfer: error: transmit timeout\n");
  183. ret = -2;
  184. goto i2c_transfer_finish;
  185. transfer_error_ack_missing:
  186. debug("i2c_transfer: error: ACK missing\n");
  187. ret = -3;
  188. goto i2c_transfer_finish;
  189. transfer_error_receive_timeout:
  190. debug("i2c_transfer: error: receive timeout\n");
  191. ret = -4;
  192. goto i2c_transfer_finish;
  193. transfer_error_illegal_param:
  194. debug("i2c_transfer: error: illegal parameters\n");
  195. ret = -5;
  196. goto i2c_transfer_finish;
  197. transfer_error_bus_busy:
  198. debug("i2c_transfer: error: bus is busy\n");
  199. ret = -6;
  200. goto i2c_transfer_finish;
  201. i2c_transfer_finish:
  202. debug("i2c_transfer: ISR: 0x%04x\n", readl(&base->isr));
  203. i2c_reset(base);
  204. return ret;
  205. }
  206. static int __i2c_read(struct mv_i2c *base, uchar chip, u8 *addr, int alen,
  207. uchar *buffer, int len)
  208. {
  209. struct mv_i2c_msg msg;
  210. debug("i2c_read(chip=0x%02x, addr=0x%02x, alen=0x%02x, "
  211. "len=0x%02x)\n", chip, *addr, alen, len);
  212. if (len == 0) {
  213. printf("reading zero byte is invalid\n");
  214. return -EINVAL;
  215. }
  216. i2c_reset(base);
  217. /* dummy chip address write */
  218. debug("i2c_read: dummy chip address write\n");
  219. msg.condition = I2C_COND_START;
  220. msg.acknack = I2C_ACKNAK_WAITACK;
  221. msg.direction = I2C_WRITE;
  222. msg.data = (chip << 1);
  223. msg.data &= 0xFE;
  224. if (i2c_transfer(base, &msg))
  225. return -1;
  226. /*
  227. * send memory address bytes;
  228. * alen defines how much bytes we have to send.
  229. */
  230. while (--alen >= 0) {
  231. debug("i2c_read: send address byte %02x (alen=%d)\n",
  232. *addr, alen);
  233. msg.condition = I2C_COND_NORMAL;
  234. msg.acknack = I2C_ACKNAK_WAITACK;
  235. msg.direction = I2C_WRITE;
  236. msg.data = addr[alen];
  237. if (i2c_transfer(base, &msg))
  238. return -1;
  239. }
  240. /* start read sequence */
  241. debug("i2c_read: start read sequence\n");
  242. msg.condition = I2C_COND_START;
  243. msg.acknack = I2C_ACKNAK_WAITACK;
  244. msg.direction = I2C_WRITE;
  245. msg.data = (chip << 1);
  246. msg.data |= 0x01;
  247. if (i2c_transfer(base, &msg))
  248. return -1;
  249. /* read bytes; send NACK at last byte */
  250. while (len--) {
  251. if (len == 0) {
  252. msg.condition = I2C_COND_STOP;
  253. msg.acknack = I2C_ACKNAK_SENDNAK;
  254. } else {
  255. msg.condition = I2C_COND_NORMAL;
  256. msg.acknack = I2C_ACKNAK_SENDACK;
  257. }
  258. msg.direction = I2C_READ;
  259. msg.data = 0x00;
  260. if (i2c_transfer(base, &msg))
  261. return -1;
  262. *buffer = msg.data;
  263. debug("i2c_read: reading byte (%p)=0x%02x\n",
  264. buffer, *buffer);
  265. buffer++;
  266. }
  267. i2c_reset(base);
  268. return 0;
  269. }
  270. static int __i2c_write(struct mv_i2c *base, uchar chip, u8 *addr, int alen,
  271. uchar *buffer, int len)
  272. {
  273. struct mv_i2c_msg msg;
  274. debug("i2c_write(chip=0x%02x, addr=0x%02x, alen=0x%02x, "
  275. "len=0x%02x)\n", chip, *addr, alen, len);
  276. i2c_reset(base);
  277. /* chip address write */
  278. debug("i2c_write: chip address write\n");
  279. msg.condition = I2C_COND_START;
  280. msg.acknack = I2C_ACKNAK_WAITACK;
  281. msg.direction = I2C_WRITE;
  282. msg.data = (chip << 1);
  283. msg.data &= 0xFE;
  284. if (i2c_transfer(base, &msg))
  285. return -1;
  286. /*
  287. * send memory address bytes;
  288. * alen defines how much bytes we have to send.
  289. */
  290. while (--alen >= 0) {
  291. debug("i2c_read: send address byte %02x (alen=%d)\n",
  292. *addr, alen);
  293. msg.condition = I2C_COND_NORMAL;
  294. msg.acknack = I2C_ACKNAK_WAITACK;
  295. msg.direction = I2C_WRITE;
  296. msg.data = addr[alen];
  297. if (i2c_transfer(base, &msg))
  298. return -1;
  299. }
  300. /* write bytes; send NACK at last byte */
  301. while (len--) {
  302. debug("i2c_write: writing byte (%p)=0x%02x\n",
  303. buffer, *buffer);
  304. if (len == 0)
  305. msg.condition = I2C_COND_STOP;
  306. else
  307. msg.condition = I2C_COND_NORMAL;
  308. msg.acknack = I2C_ACKNAK_WAITACK;
  309. msg.direction = I2C_WRITE;
  310. msg.data = *(buffer++);
  311. if (i2c_transfer(base, &msg))
  312. return -1;
  313. }
  314. i2c_reset(base);
  315. return 0;
  316. }
  317. #if !CONFIG_IS_ENABLED(DM_I2C)
  318. static struct mv_i2c *base_glob;
  319. static void i2c_board_init(struct mv_i2c *base)
  320. {
  321. #ifdef CONFIG_SYS_I2C_INIT_BOARD
  322. u32 icr;
  323. /*
  324. * call board specific i2c bus reset routine before accessing the
  325. * environment, which might be in a chip on that bus. For details
  326. * about this problem see doc/I2C_Edge_Conditions.
  327. *
  328. * disable I2C controller first, otherwhise it thinks we want to
  329. * talk to the slave port...
  330. */
  331. icr = readl(&base->icr);
  332. writel(readl(&base->icr) & ~(ICR_SCLE | ICR_IUE), &base->icr);
  333. i2c_init_board();
  334. writel(icr, &base->icr);
  335. #endif
  336. }
  337. #ifdef CONFIG_I2C_MULTI_BUS
  338. static unsigned long i2c_regs[CONFIG_MV_I2C_NUM] = CONFIG_MV_I2C_REG;
  339. static unsigned int bus_initialized[CONFIG_MV_I2C_NUM];
  340. static unsigned int current_bus;
  341. int i2c_set_bus_num(unsigned int bus)
  342. {
  343. if ((bus < 0) || (bus >= CONFIG_MV_I2C_NUM)) {
  344. printf("Bad bus: %d\n", bus);
  345. return -1;
  346. }
  347. base_glob = (struct mv_i2c *)i2c_regs[bus];
  348. current_bus = bus;
  349. if (!bus_initialized[current_bus]) {
  350. i2c_board_init(base_glob);
  351. bus_initialized[current_bus] = 1;
  352. }
  353. return 0;
  354. }
  355. unsigned int i2c_get_bus_num(void)
  356. {
  357. return current_bus;
  358. }
  359. #endif
  360. /* API Functions */
  361. void i2c_init(int speed, int slaveaddr)
  362. {
  363. u32 val;
  364. #ifdef CONFIG_I2C_MULTI_BUS
  365. current_bus = 0;
  366. base_glob = (struct mv_i2c *)i2c_regs[current_bus];
  367. #else
  368. base_glob = (struct mv_i2c *)CONFIG_MV_I2C_REG;
  369. #endif
  370. if (speed > I2C_SPEED_STANDARD_RATE)
  371. val = ICR_FM;
  372. else
  373. val = ICR_SM;
  374. clrsetbits_le32(&base_glob->icr, ICR_MODE_MASK, val);
  375. i2c_board_init(base_glob);
  376. }
  377. static int __i2c_probe_chip(struct mv_i2c *base, uchar chip)
  378. {
  379. struct mv_i2c_msg msg;
  380. i2c_reset(base);
  381. msg.condition = I2C_COND_START;
  382. msg.acknack = I2C_ACKNAK_WAITACK;
  383. msg.direction = I2C_WRITE;
  384. msg.data = (chip << 1) + 1;
  385. if (i2c_transfer(base, &msg))
  386. return -1;
  387. msg.condition = I2C_COND_STOP;
  388. msg.acknack = I2C_ACKNAK_SENDNAK;
  389. msg.direction = I2C_READ;
  390. msg.data = 0x00;
  391. if (i2c_transfer(base, &msg))
  392. return -1;
  393. return 0;
  394. }
  395. /*
  396. * i2c_probe: - Test if a chip answers for a given i2c address
  397. *
  398. * @chip: address of the chip which is searched for
  399. * @return: 0 if a chip was found, -1 otherwhise
  400. */
  401. int i2c_probe(uchar chip)
  402. {
  403. return __i2c_probe_chip(base_glob, chip);
  404. }
  405. /*
  406. * i2c_read: - Read multiple bytes from an i2c device
  407. *
  408. * The higher level routines take into account that this function is only
  409. * called with len < page length of the device (see configuration file)
  410. *
  411. * @chip: address of the chip which is to be read
  412. * @addr: i2c data address within the chip
  413. * @alen: length of the i2c data address (1..2 bytes)
  414. * @buffer: where to write the data
  415. * @len: how much byte do we want to read
  416. * @return: 0 in case of success
  417. */
  418. int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
  419. {
  420. u8 addr_bytes[4];
  421. addr_bytes[0] = (addr >> 0) & 0xFF;
  422. addr_bytes[1] = (addr >> 8) & 0xFF;
  423. addr_bytes[2] = (addr >> 16) & 0xFF;
  424. addr_bytes[3] = (addr >> 24) & 0xFF;
  425. return __i2c_read(base_glob, chip, addr_bytes, alen, buffer, len);
  426. }
  427. /*
  428. * i2c_write: - Write multiple bytes to an i2c device
  429. *
  430. * The higher level routines take into account that this function is only
  431. * called with len < page length of the device (see configuration file)
  432. *
  433. * @chip: address of the chip which is to be written
  434. * @addr: i2c data address within the chip
  435. * @alen: length of the i2c data address (1..2 bytes)
  436. * @buffer: where to find the data to be written
  437. * @len: how much byte do we want to read
  438. * @return: 0 in case of success
  439. */
  440. int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
  441. {
  442. u8 addr_bytes[4];
  443. addr_bytes[0] = (addr >> 0) & 0xFF;
  444. addr_bytes[1] = (addr >> 8) & 0xFF;
  445. addr_bytes[2] = (addr >> 16) & 0xFF;
  446. addr_bytes[3] = (addr >> 24) & 0xFF;
  447. return __i2c_write(base_glob, chip, addr_bytes, alen, buffer, len);
  448. }
  449. #else /* CONFIG_DM_I2C */
  450. struct mv_i2c_priv {
  451. struct mv_i2c *base;
  452. };
  453. static int mv_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
  454. {
  455. struct mv_i2c_priv *i2c = dev_get_priv(bus);
  456. struct i2c_msg *dmsg, *omsg, dummy;
  457. memset(&dummy, 0, sizeof(struct i2c_msg));
  458. /*
  459. * We expect either two messages (one with an offset and one with the
  460. * actual data) or one message (just data or offset/data combined)
  461. */
  462. if (nmsgs > 2 || nmsgs == 0) {
  463. debug("%s: Only one or two messages are supported.", __func__);
  464. return -1;
  465. }
  466. omsg = nmsgs == 1 ? &dummy : msg;
  467. dmsg = nmsgs == 1 ? msg : msg + 1;
  468. if (dmsg->flags & I2C_M_RD)
  469. return __i2c_read(i2c->base, dmsg->addr, omsg->buf,
  470. omsg->len, dmsg->buf, dmsg->len);
  471. else
  472. return __i2c_write(i2c->base, dmsg->addr, omsg->buf,
  473. omsg->len, dmsg->buf, dmsg->len);
  474. }
  475. static int mv_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
  476. {
  477. struct mv_i2c_priv *priv = dev_get_priv(bus);
  478. u32 val;
  479. if (speed > I2C_SPEED_STANDARD_RATE)
  480. val = ICR_FM;
  481. else
  482. val = ICR_SM;
  483. clrsetbits_le32(&priv->base->icr, ICR_MODE_MASK, val);
  484. return 0;
  485. }
  486. static int mv_i2c_probe(struct udevice *bus)
  487. {
  488. struct mv_i2c_priv *priv = dev_get_priv(bus);
  489. priv->base = dev_read_addr_ptr(bus);
  490. return 0;
  491. }
  492. static const struct dm_i2c_ops mv_i2c_ops = {
  493. .xfer = mv_i2c_xfer,
  494. .set_bus_speed = mv_i2c_set_bus_speed,
  495. };
  496. static const struct udevice_id mv_i2c_ids[] = {
  497. { .compatible = "marvell,armada-3700-i2c" },
  498. { }
  499. };
  500. U_BOOT_DRIVER(i2c_mv) = {
  501. .name = "i2c_mv",
  502. .id = UCLASS_I2C,
  503. .of_match = mv_i2c_ids,
  504. .probe = mv_i2c_probe,
  505. .priv_auto = sizeof(struct mv_i2c_priv),
  506. .ops = &mv_i2c_ops,
  507. };
  508. #endif /* CONFIG_DM_I2C */