lpc32xx_i2c.c 9.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * LPC32xx I2C interface driver
  4. *
  5. * (C) Copyright 2014-2015 DENX Software Engineering GmbH
  6. * Written-by: Albert ARIBAUD - 3ADEV <albert.aribaud@3adev.fr>
  7. */
  8. #include <common.h>
  9. #include <log.h>
  10. #include <asm/io.h>
  11. #include <i2c.h>
  12. #include <linux/errno.h>
  13. #include <asm/arch/clk.h>
  14. #include <asm/arch/i2c.h>
  15. #include <dm.h>
  16. #include <mapmem.h>
  17. /*
  18. * Provide default speed and slave if target did not
  19. */
  20. #if !defined(CONFIG_SYS_I2C_LPC32XX_SPEED)
  21. #define CONFIG_SYS_I2C_LPC32XX_SPEED 350000
  22. #endif
  23. #if !defined(CONFIG_SYS_I2C_LPC32XX_SLAVE)
  24. #define CONFIG_SYS_I2C_LPC32XX_SLAVE 0
  25. #endif
  26. /* TX register fields */
  27. #define LPC32XX_I2C_TX_START 0x00000100
  28. #define LPC32XX_I2C_TX_STOP 0x00000200
  29. /* Control register values */
  30. #define LPC32XX_I2C_SOFT_RESET 0x00000100
  31. /* Status register values */
  32. #define LPC32XX_I2C_STAT_TFF 0x00000400
  33. #define LPC32XX_I2C_STAT_RFE 0x00000200
  34. #define LPC32XX_I2C_STAT_NAI 0x00000004
  35. #define LPC32XX_I2C_STAT_TDI 0x00000001
  36. #if !CONFIG_IS_ENABLED(DM_I2C)
  37. static struct lpc32xx_i2c_base *lpc32xx_i2c[] = {
  38. (struct lpc32xx_i2c_base *)I2C1_BASE,
  39. (struct lpc32xx_i2c_base *)I2C2_BASE,
  40. (struct lpc32xx_i2c_base *)(USB_BASE + 0x300)
  41. };
  42. #endif
  43. /* Set I2C bus speed */
  44. static unsigned int __i2c_set_bus_speed(struct lpc32xx_i2c_base *base,
  45. unsigned int speed, unsigned int chip)
  46. {
  47. int half_period;
  48. if (speed == 0)
  49. return -EINVAL;
  50. /* OTG I2C clock source and CLK registers are different */
  51. if (chip == 2) {
  52. half_period = (get_periph_clk_rate() / speed) / 2;
  53. if (half_period > 0xFF)
  54. return -EINVAL;
  55. } else {
  56. half_period = (get_hclk_clk_rate() / speed) / 2;
  57. if (half_period > 0x3FF)
  58. return -EINVAL;
  59. }
  60. writel(half_period, &base->clk_hi);
  61. writel(half_period, &base->clk_lo);
  62. return 0;
  63. }
  64. /* I2C init called by cmd_i2c when doing 'i2c reset'. */
  65. static void __i2c_init(struct lpc32xx_i2c_base *base,
  66. int requested_speed, int slaveadd, unsigned int chip)
  67. {
  68. /* soft reset (auto-clears) */
  69. writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl);
  70. /* set HI and LO periods for half of the default speed */
  71. __i2c_set_bus_speed(base, requested_speed, chip);
  72. }
  73. /* I2C probe called by cmd_i2c when doing 'i2c probe'. */
  74. static int __i2c_probe_chip(struct lpc32xx_i2c_base *base, u8 dev)
  75. {
  76. int stat;
  77. /* Soft-reset the controller */
  78. writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl);
  79. while (readl(&base->ctrl) & LPC32XX_I2C_SOFT_RESET)
  80. ;
  81. /* Addre slave for write with start before and stop after */
  82. writel((dev<<1) | LPC32XX_I2C_TX_START | LPC32XX_I2C_TX_STOP,
  83. &base->tx);
  84. /* wait for end of transation */
  85. while (!((stat = readl(&base->stat)) & LPC32XX_I2C_STAT_TDI))
  86. ;
  87. /* was there no acknowledge? */
  88. return (stat & LPC32XX_I2C_STAT_NAI) ? -1 : 0;
  89. }
  90. /*
  91. * I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c
  92. * Begin write, send address byte(s), begin read, receive data bytes, end.
  93. */
  94. static int __i2c_read(struct lpc32xx_i2c_base *base, u8 dev, uint addr,
  95. int alen, u8 *data, int length)
  96. {
  97. int stat, wlen;
  98. /* Soft-reset the controller */
  99. writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl);
  100. while (readl(&base->ctrl) & LPC32XX_I2C_SOFT_RESET)
  101. ;
  102. /* do we need to write an address at all? */
  103. if (alen) {
  104. /* Address slave in write mode */
  105. writel((dev<<1) | LPC32XX_I2C_TX_START, &base->tx);
  106. /* write address bytes */
  107. while (alen--) {
  108. /* compute address byte + stop for the last one */
  109. int a = (addr >> (8 * alen)) & 0xff;
  110. if (!alen)
  111. a |= LPC32XX_I2C_TX_STOP;
  112. /* Send address byte */
  113. writel(a, &base->tx);
  114. }
  115. /* wait for end of transation */
  116. while (!((stat = readl(&base->stat)) & LPC32XX_I2C_STAT_TDI))
  117. ;
  118. /* clear end-of-transaction flag */
  119. writel(1, &base->stat);
  120. }
  121. /* do we have to read data at all? */
  122. if (length) {
  123. /* Address slave in read mode */
  124. writel(1 | (dev<<1) | LPC32XX_I2C_TX_START, &base->tx);
  125. wlen = length;
  126. /* get data */
  127. while (length | wlen) {
  128. /* read status for TFF and RFE */
  129. stat = readl(&base->stat);
  130. /* must we, can we write a trigger byte? */
  131. if ((wlen > 0)
  132. & (!(stat & LPC32XX_I2C_STAT_TFF))) {
  133. wlen--;
  134. /* write trigger byte + stop if last */
  135. writel(wlen ? 0 :
  136. LPC32XX_I2C_TX_STOP, &base->tx);
  137. }
  138. /* must we, can we read a data byte? */
  139. if ((length > 0)
  140. & (!(stat & LPC32XX_I2C_STAT_RFE))) {
  141. length--;
  142. /* read byte */
  143. *(data++) = readl(&base->rx);
  144. }
  145. }
  146. /* wait for end of transation */
  147. while (!((stat = readl(&base->stat)) & LPC32XX_I2C_STAT_TDI))
  148. ;
  149. /* clear end-of-transaction flag */
  150. writel(1, &base->stat);
  151. }
  152. /* success */
  153. return 0;
  154. }
  155. /*
  156. * I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c
  157. * Begin write, send address byte(s), send data bytes, end.
  158. */
  159. static int __i2c_write(struct lpc32xx_i2c_base *base, u8 dev, uint addr,
  160. int alen, u8 *data, int length)
  161. {
  162. int stat;
  163. /* Soft-reset the controller */
  164. writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl);
  165. while (readl(&base->ctrl) & LPC32XX_I2C_SOFT_RESET)
  166. ;
  167. /* do we need to write anything at all? */
  168. if (alen | length)
  169. /* Address slave in write mode */
  170. writel((dev<<1) | LPC32XX_I2C_TX_START, &base->tx);
  171. else
  172. return 0;
  173. /* write address bytes */
  174. while (alen) {
  175. /* wait for transmit fifo not full */
  176. stat = readl(&base->stat);
  177. if (!(stat & LPC32XX_I2C_STAT_TFF)) {
  178. alen--;
  179. int a = (addr >> (8 * alen)) & 0xff;
  180. if (!(alen | length))
  181. a |= LPC32XX_I2C_TX_STOP;
  182. /* Send address byte */
  183. writel(a, &base->tx);
  184. }
  185. }
  186. while (length) {
  187. /* wait for transmit fifo not full */
  188. stat = readl(&base->stat);
  189. if (!(stat & LPC32XX_I2C_STAT_TFF)) {
  190. /* compute data byte, add stop if length==0 */
  191. length--;
  192. int d = *(data++);
  193. if (!length)
  194. d |= LPC32XX_I2C_TX_STOP;
  195. /* Send data byte */
  196. writel(d, &base->tx);
  197. }
  198. }
  199. /* wait for end of transation */
  200. while (!((stat = readl(&base->stat)) & LPC32XX_I2C_STAT_TDI))
  201. ;
  202. /* clear end-of-transaction flag */
  203. writel(1, &base->stat);
  204. return 0;
  205. }
  206. #if !CONFIG_IS_ENABLED(DM_I2C)
  207. static void lpc32xx_i2c_init(struct i2c_adapter *adap,
  208. int requested_speed, int slaveadd)
  209. {
  210. __i2c_init(lpc32xx_i2c[adap->hwadapnr], requested_speed, slaveadd,
  211. adap->hwadapnr);
  212. }
  213. static int lpc32xx_i2c_probe_chip(struct i2c_adapter *adap, u8 dev)
  214. {
  215. return __i2c_probe_chip(lpc32xx_i2c[adap->hwadapnr], dev);
  216. }
  217. static int lpc32xx_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
  218. int alen, u8 *data, int length)
  219. {
  220. return __i2c_read(lpc32xx_i2c[adap->hwadapnr], dev, addr,
  221. alen, data, length);
  222. }
  223. static int lpc32xx_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
  224. int alen, u8 *data, int length)
  225. {
  226. return __i2c_write(lpc32xx_i2c[adap->hwadapnr], dev, addr,
  227. alen, data, length);
  228. }
  229. static unsigned int lpc32xx_i2c_set_bus_speed(struct i2c_adapter *adap,
  230. unsigned int speed)
  231. {
  232. return __i2c_set_bus_speed(lpc32xx_i2c[adap->hwadapnr], speed,
  233. adap->hwadapnr);
  234. }
  235. U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_0, lpc32xx_i2c_init, lpc32xx_i2c_probe_chip,
  236. lpc32xx_i2c_read, lpc32xx_i2c_write,
  237. lpc32xx_i2c_set_bus_speed,
  238. CONFIG_SYS_I2C_LPC32XX_SPEED,
  239. CONFIG_SYS_I2C_LPC32XX_SLAVE,
  240. 0)
  241. U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_1, lpc32xx_i2c_init, lpc32xx_i2c_probe_chip,
  242. lpc32xx_i2c_read, lpc32xx_i2c_write,
  243. lpc32xx_i2c_set_bus_speed,
  244. CONFIG_SYS_I2C_LPC32XX_SPEED,
  245. CONFIG_SYS_I2C_LPC32XX_SLAVE,
  246. 1)
  247. U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_2, lpc32xx_i2c_init, NULL,
  248. lpc32xx_i2c_read, lpc32xx_i2c_write,
  249. lpc32xx_i2c_set_bus_speed,
  250. 100000,
  251. 0,
  252. 2)
  253. #else /* CONFIG_DM_I2C */
  254. static int lpc32xx_i2c_probe(struct udevice *bus)
  255. {
  256. struct lpc32xx_i2c_dev *dev = dev_get_plat(bus);
  257. dev->base = dev_read_addr_ptr(bus);
  258. __i2c_init(dev->base, dev->speed, 0, dev->index);
  259. return 0;
  260. }
  261. static int lpc32xx_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
  262. u32 chip_flags)
  263. {
  264. struct lpc32xx_i2c_dev *dev = dev_get_plat(bus);
  265. return __i2c_probe_chip(dev->base, chip_addr);
  266. }
  267. static int lpc32xx_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
  268. int nmsgs)
  269. {
  270. struct lpc32xx_i2c_dev *dev = dev_get_plat(bus);
  271. struct i2c_msg *dmsg, *omsg, dummy;
  272. uint i = 0, address = 0;
  273. memset(&dummy, 0, sizeof(struct i2c_msg));
  274. /* We expect either two messages (one with an offset and one with the
  275. * actual data) or one message (just data)
  276. */
  277. if (nmsgs > 2 || nmsgs == 0) {
  278. debug("%s: Only one or two messages are supported.", __func__);
  279. return -1;
  280. }
  281. omsg = nmsgs == 1 ? &dummy : msg;
  282. dmsg = nmsgs == 1 ? msg : msg + 1;
  283. /* the address is expected to be a uint, not a array. */
  284. address = omsg->buf[0];
  285. for (i = 1; i < omsg->len; i++)
  286. address = (address << 8) + omsg->buf[i];
  287. if (dmsg->flags & I2C_M_RD)
  288. return __i2c_read(dev->base, dmsg->addr, address,
  289. omsg->len, dmsg->buf, dmsg->len);
  290. else
  291. return __i2c_write(dev->base, dmsg->addr, address,
  292. omsg->len, dmsg->buf, dmsg->len);
  293. }
  294. static int lpc32xx_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
  295. {
  296. struct lpc32xx_i2c_dev *dev = dev_get_plat(bus);
  297. return __i2c_set_bus_speed(dev->base, speed, dev->index);
  298. }
  299. static int lpc32xx_i2c_reset(struct udevice *bus)
  300. {
  301. struct lpc32xx_i2c_dev *dev = dev_get_plat(bus);
  302. __i2c_init(dev->base, dev->speed, 0, dev->index);
  303. return 0;
  304. }
  305. static const struct dm_i2c_ops lpc32xx_i2c_ops = {
  306. .xfer = lpc32xx_i2c_xfer,
  307. .probe_chip = lpc32xx_i2c_probe_chip,
  308. .deblock = lpc32xx_i2c_reset,
  309. .set_bus_speed = lpc32xx_i2c_set_bus_speed,
  310. };
  311. static const struct udevice_id lpc32xx_i2c_ids[] = {
  312. { .compatible = "nxp,pnx-i2c" },
  313. { }
  314. };
  315. U_BOOT_DRIVER(i2c_lpc32xx) = {
  316. .name = "i2c_lpc32xx",
  317. .id = UCLASS_I2C,
  318. .of_match = lpc32xx_i2c_ids,
  319. .probe = lpc32xx_i2c_probe,
  320. .ops = &lpc32xx_i2c_ops,
  321. };
  322. #endif /* CONFIG_DM_I2C */