kona_i2c.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2013 Broadcom Corporation.
  4. *
  5. * NOTE: This driver should be converted to driver model before June 2017.
  6. * Please see doc/driver-model/i2c-howto.rst for instructions.
  7. */
  8. #include <common.h>
  9. #include <log.h>
  10. #include <asm/io.h>
  11. #include <linux/delay.h>
  12. #include <linux/errno.h>
  13. #include <asm/arch/sysmap.h>
  14. #include <asm/kona-common/clk.h>
  15. #include <i2c.h>
  16. /* Hardware register offsets and field defintions */
  17. #define CS_OFFSET 0x00000020
  18. #define CS_ACK_SHIFT 3
  19. #define CS_ACK_MASK 0x00000008
  20. #define CS_ACK_CMD_GEN_START 0x00000000
  21. #define CS_ACK_CMD_GEN_RESTART 0x00000001
  22. #define CS_CMD_SHIFT 1
  23. #define CS_CMD_CMD_NO_ACTION 0x00000000
  24. #define CS_CMD_CMD_START_RESTART 0x00000001
  25. #define CS_CMD_CMD_STOP 0x00000002
  26. #define CS_EN_SHIFT 0
  27. #define CS_EN_CMD_ENABLE_BSC 0x00000001
  28. #define TIM_OFFSET 0x00000024
  29. #define TIM_PRESCALE_SHIFT 6
  30. #define TIM_P_SHIFT 3
  31. #define TIM_NO_DIV_SHIFT 2
  32. #define TIM_DIV_SHIFT 0
  33. #define DAT_OFFSET 0x00000028
  34. #define TOUT_OFFSET 0x0000002c
  35. #define TXFCR_OFFSET 0x0000003c
  36. #define TXFCR_FIFO_FLUSH_MASK 0x00000080
  37. #define TXFCR_FIFO_EN_MASK 0x00000040
  38. #define IER_OFFSET 0x00000044
  39. #define IER_READ_COMPLETE_INT_MASK 0x00000010
  40. #define IER_I2C_INT_EN_MASK 0x00000008
  41. #define IER_FIFO_INT_EN_MASK 0x00000002
  42. #define IER_NOACK_EN_MASK 0x00000001
  43. #define ISR_OFFSET 0x00000048
  44. #define ISR_RESERVED_MASK 0xffffff60
  45. #define ISR_CMDBUSY_MASK 0x00000080
  46. #define ISR_READ_COMPLETE_MASK 0x00000010
  47. #define ISR_SES_DONE_MASK 0x00000008
  48. #define ISR_ERR_MASK 0x00000004
  49. #define ISR_TXFIFOEMPTY_MASK 0x00000002
  50. #define ISR_NOACK_MASK 0x00000001
  51. #define CLKEN_OFFSET 0x0000004c
  52. #define CLKEN_AUTOSENSE_OFF_MASK 0x00000080
  53. #define CLKEN_M_SHIFT 4
  54. #define CLKEN_N_SHIFT 1
  55. #define CLKEN_CLKEN_MASK 0x00000001
  56. #define FIFO_STATUS_OFFSET 0x00000054
  57. #define FIFO_STATUS_RXFIFO_EMPTY_MASK 0x00000004
  58. #define FIFO_STATUS_TXFIFO_EMPTY_MASK 0x00000010
  59. #define HSTIM_OFFSET 0x00000058
  60. #define HSTIM_HS_MODE_MASK 0x00008000
  61. #define HSTIM_HS_HOLD_SHIFT 10
  62. #define HSTIM_HS_HIGH_PHASE_SHIFT 5
  63. #define HSTIM_HS_SETUP_SHIFT 0
  64. #define PADCTL_OFFSET 0x0000005c
  65. #define PADCTL_PAD_OUT_EN_MASK 0x00000004
  66. #define RXFCR_OFFSET 0x00000068
  67. #define RXFCR_NACK_EN_SHIFT 7
  68. #define RXFCR_READ_COUNT_SHIFT 0
  69. #define RXFIFORDOUT_OFFSET 0x0000006c
  70. /* Locally used constants */
  71. #define MAX_RX_FIFO_SIZE 64U /* bytes */
  72. #define MAX_TX_FIFO_SIZE 64U /* bytes */
  73. #define I2C_TIMEOUT 100000 /* usecs */
  74. #define WAIT_INT_CHK 100 /* usecs */
  75. #if I2C_TIMEOUT % WAIT_INT_CHK
  76. #error I2C_TIMEOUT must be a multiple of WAIT_INT_CHK
  77. #endif
  78. /* Operations that can be commanded to the controller */
  79. enum bcm_kona_cmd_t {
  80. BCM_CMD_NOACTION = 0,
  81. BCM_CMD_START,
  82. BCM_CMD_RESTART,
  83. BCM_CMD_STOP,
  84. };
  85. /* Internal divider settings for standard mode, fast mode and fast mode plus */
  86. struct bus_speed_cfg {
  87. uint8_t time_m; /* Number of cycles for setup time */
  88. uint8_t time_n; /* Number of cycles for hold time */
  89. uint8_t prescale; /* Prescale divider */
  90. uint8_t time_p; /* Timing coefficient */
  91. uint8_t no_div; /* Disable clock divider */
  92. uint8_t time_div; /* Post-prescale divider */
  93. };
  94. static const struct bus_speed_cfg std_cfg_table[] = {
  95. [IC_SPEED_MODE_STANDARD] = {0x01, 0x01, 0x03, 0x06, 0x00, 0x02},
  96. [IC_SPEED_MODE_FAST] = {0x05, 0x01, 0x03, 0x05, 0x01, 0x02},
  97. [IC_SPEED_MODE_FAST_PLUS] = {0x01, 0x01, 0x03, 0x01, 0x01, 0x03},
  98. };
  99. struct bcm_kona_i2c_dev {
  100. void *base;
  101. uint speed;
  102. const struct bus_speed_cfg *std_cfg;
  103. };
  104. /* Keep these two defines in sync */
  105. #define DEF_SPD I2C_SPEED_STANDARD_RATE
  106. #define DEF_SPD_ENUM IC_SPEED_MODE_STANDARD
  107. #define DEF_DEVICE(num) \
  108. {(void *)CONFIG_SYS_I2C_BASE##num, DEF_SPD, &std_cfg_table[DEF_SPD_ENUM]}
  109. static struct bcm_kona_i2c_dev g_i2c_devs[CONFIG_SYS_MAX_I2C_BUS] = {
  110. #ifdef CONFIG_SYS_I2C_BASE0
  111. DEF_DEVICE(0),
  112. #endif
  113. #ifdef CONFIG_SYS_I2C_BASE1
  114. DEF_DEVICE(1),
  115. #endif
  116. #ifdef CONFIG_SYS_I2C_BASE2
  117. DEF_DEVICE(2),
  118. #endif
  119. #ifdef CONFIG_SYS_I2C_BASE3
  120. DEF_DEVICE(3),
  121. #endif
  122. #ifdef CONFIG_SYS_I2C_BASE4
  123. DEF_DEVICE(4),
  124. #endif
  125. #ifdef CONFIG_SYS_I2C_BASE5
  126. DEF_DEVICE(5),
  127. #endif
  128. };
  129. #define I2C_M_TEN 0x0010 /* ten bit address */
  130. #define I2C_M_RD 0x0001 /* read data */
  131. #define I2C_M_NOSTART 0x4000 /* no restart between msgs */
  132. struct kona_i2c_msg {
  133. uint16_t addr;
  134. uint16_t flags;
  135. uint16_t len;
  136. uint8_t *buf;
  137. };
  138. static void bcm_kona_i2c_send_cmd_to_ctrl(struct bcm_kona_i2c_dev *dev,
  139. enum bcm_kona_cmd_t cmd)
  140. {
  141. debug("%s, %d\n", __func__, cmd);
  142. switch (cmd) {
  143. case BCM_CMD_NOACTION:
  144. writel((CS_CMD_CMD_NO_ACTION << CS_CMD_SHIFT) |
  145. (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
  146. dev->base + CS_OFFSET);
  147. break;
  148. case BCM_CMD_START:
  149. writel((CS_ACK_CMD_GEN_START << CS_ACK_SHIFT) |
  150. (CS_CMD_CMD_START_RESTART << CS_CMD_SHIFT) |
  151. (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
  152. dev->base + CS_OFFSET);
  153. break;
  154. case BCM_CMD_RESTART:
  155. writel((CS_ACK_CMD_GEN_RESTART << CS_ACK_SHIFT) |
  156. (CS_CMD_CMD_START_RESTART << CS_CMD_SHIFT) |
  157. (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
  158. dev->base + CS_OFFSET);
  159. break;
  160. case BCM_CMD_STOP:
  161. writel((CS_CMD_CMD_STOP << CS_CMD_SHIFT) |
  162. (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
  163. dev->base + CS_OFFSET);
  164. break;
  165. default:
  166. printf("Unknown command %d\n", cmd);
  167. }
  168. }
  169. static void bcm_kona_i2c_enable_clock(struct bcm_kona_i2c_dev *dev)
  170. {
  171. writel(readl(dev->base + CLKEN_OFFSET) | CLKEN_CLKEN_MASK,
  172. dev->base + CLKEN_OFFSET);
  173. }
  174. static void bcm_kona_i2c_disable_clock(struct bcm_kona_i2c_dev *dev)
  175. {
  176. writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_CLKEN_MASK,
  177. dev->base + CLKEN_OFFSET);
  178. }
  179. /* Wait until at least one of the mask bit(s) are set */
  180. static unsigned long wait_for_int_timeout(struct bcm_kona_i2c_dev *dev,
  181. unsigned long time_left,
  182. uint32_t mask)
  183. {
  184. uint32_t status;
  185. while (time_left) {
  186. status = readl(dev->base + ISR_OFFSET);
  187. if ((status & ~ISR_RESERVED_MASK) == 0) {
  188. debug("Bogus I2C interrupt 0x%x\n", status);
  189. continue;
  190. }
  191. /* Must flush the TX FIFO when NAK detected */
  192. if (status & ISR_NOACK_MASK)
  193. writel(TXFCR_FIFO_FLUSH_MASK | TXFCR_FIFO_EN_MASK,
  194. dev->base + TXFCR_OFFSET);
  195. writel(status & ~ISR_RESERVED_MASK, dev->base + ISR_OFFSET);
  196. if (status & mask) {
  197. /* We are done since one of the mask bits are set */
  198. return time_left;
  199. }
  200. udelay(WAIT_INT_CHK);
  201. time_left -= WAIT_INT_CHK;
  202. }
  203. return 0;
  204. }
  205. /* Send command to I2C bus */
  206. static int bcm_kona_send_i2c_cmd(struct bcm_kona_i2c_dev *dev,
  207. enum bcm_kona_cmd_t cmd)
  208. {
  209. int rc = 0;
  210. unsigned long time_left = I2C_TIMEOUT;
  211. /* Send the command */
  212. bcm_kona_i2c_send_cmd_to_ctrl(dev, cmd);
  213. /* Wait for transaction to finish or timeout */
  214. time_left = wait_for_int_timeout(dev, time_left, IER_I2C_INT_EN_MASK);
  215. if (!time_left) {
  216. printf("controller timed out\n");
  217. rc = -ETIMEDOUT;
  218. }
  219. /* Clear command */
  220. bcm_kona_i2c_send_cmd_to_ctrl(dev, BCM_CMD_NOACTION);
  221. return rc;
  222. }
  223. /* Read a single RX FIFO worth of data from the i2c bus */
  224. static int bcm_kona_i2c_read_fifo_single(struct bcm_kona_i2c_dev *dev,
  225. uint8_t *buf, unsigned int len,
  226. unsigned int last_byte_nak)
  227. {
  228. unsigned long time_left = I2C_TIMEOUT;
  229. /* Start the RX FIFO */
  230. writel((last_byte_nak << RXFCR_NACK_EN_SHIFT) |
  231. (len << RXFCR_READ_COUNT_SHIFT), dev->base + RXFCR_OFFSET);
  232. /* Wait for FIFO read to complete */
  233. time_left =
  234. wait_for_int_timeout(dev, time_left, IER_READ_COMPLETE_INT_MASK);
  235. if (!time_left) {
  236. printf("RX FIFO time out\n");
  237. return -EREMOTEIO;
  238. }
  239. /* Read data from FIFO */
  240. for (; len > 0; len--, buf++)
  241. *buf = readl(dev->base + RXFIFORDOUT_OFFSET);
  242. return 0;
  243. }
  244. /* Read any amount of data using the RX FIFO from the i2c bus */
  245. static int bcm_kona_i2c_read_fifo(struct bcm_kona_i2c_dev *dev,
  246. struct kona_i2c_msg *msg)
  247. {
  248. unsigned int bytes_to_read = MAX_RX_FIFO_SIZE;
  249. unsigned int last_byte_nak = 0;
  250. unsigned int bytes_read = 0;
  251. int rc;
  252. uint8_t *tmp_buf = msg->buf;
  253. while (bytes_read < msg->len) {
  254. if (msg->len - bytes_read <= MAX_RX_FIFO_SIZE) {
  255. last_byte_nak = 1; /* NAK last byte of transfer */
  256. bytes_to_read = msg->len - bytes_read;
  257. }
  258. rc = bcm_kona_i2c_read_fifo_single(dev, tmp_buf, bytes_to_read,
  259. last_byte_nak);
  260. if (rc < 0)
  261. return -EREMOTEIO;
  262. bytes_read += bytes_to_read;
  263. tmp_buf += bytes_to_read;
  264. }
  265. return 0;
  266. }
  267. /* Write a single byte of data to the i2c bus */
  268. static int bcm_kona_i2c_write_byte(struct bcm_kona_i2c_dev *dev, uint8_t data,
  269. unsigned int nak_expected)
  270. {
  271. unsigned long time_left = I2C_TIMEOUT;
  272. unsigned int nak_received;
  273. /* Clear pending session done interrupt */
  274. writel(ISR_SES_DONE_MASK, dev->base + ISR_OFFSET);
  275. /* Send one byte of data */
  276. writel(data, dev->base + DAT_OFFSET);
  277. time_left = wait_for_int_timeout(dev, time_left, IER_I2C_INT_EN_MASK);
  278. if (!time_left) {
  279. debug("controller timed out\n");
  280. return -ETIMEDOUT;
  281. }
  282. nak_received = readl(dev->base + CS_OFFSET) & CS_ACK_MASK ? 1 : 0;
  283. if (nak_received ^ nak_expected) {
  284. debug("unexpected NAK/ACK\n");
  285. return -EREMOTEIO;
  286. }
  287. return 0;
  288. }
  289. /* Write a single TX FIFO worth of data to the i2c bus */
  290. static int bcm_kona_i2c_write_fifo_single(struct bcm_kona_i2c_dev *dev,
  291. uint8_t *buf, unsigned int len)
  292. {
  293. int k;
  294. unsigned long time_left = I2C_TIMEOUT;
  295. unsigned int fifo_status;
  296. /* Write data into FIFO */
  297. for (k = 0; k < len; k++)
  298. writel(buf[k], (dev->base + DAT_OFFSET));
  299. /* Wait for FIFO to empty */
  300. do {
  301. time_left =
  302. wait_for_int_timeout(dev, time_left,
  303. (IER_FIFO_INT_EN_MASK |
  304. IER_NOACK_EN_MASK));
  305. fifo_status = readl(dev->base + FIFO_STATUS_OFFSET);
  306. } while (time_left && !(fifo_status & FIFO_STATUS_TXFIFO_EMPTY_MASK));
  307. /* Check if there was a NAK */
  308. if (readl(dev->base + CS_OFFSET) & CS_ACK_MASK) {
  309. printf("unexpected NAK\n");
  310. return -EREMOTEIO;
  311. }
  312. /* Check if a timeout occurred */
  313. if (!time_left) {
  314. printf("completion timed out\n");
  315. return -EREMOTEIO;
  316. }
  317. return 0;
  318. }
  319. /* Write any amount of data using TX FIFO to the i2c bus */
  320. static int bcm_kona_i2c_write_fifo(struct bcm_kona_i2c_dev *dev,
  321. struct kona_i2c_msg *msg)
  322. {
  323. unsigned int bytes_to_write = MAX_TX_FIFO_SIZE;
  324. unsigned int bytes_written = 0;
  325. int rc;
  326. uint8_t *tmp_buf = msg->buf;
  327. while (bytes_written < msg->len) {
  328. if (msg->len - bytes_written <= MAX_TX_FIFO_SIZE)
  329. bytes_to_write = msg->len - bytes_written;
  330. rc = bcm_kona_i2c_write_fifo_single(dev, tmp_buf,
  331. bytes_to_write);
  332. if (rc < 0)
  333. return -EREMOTEIO;
  334. bytes_written += bytes_to_write;
  335. tmp_buf += bytes_to_write;
  336. }
  337. return 0;
  338. }
  339. /* Send i2c address */
  340. static int bcm_kona_i2c_do_addr(struct bcm_kona_i2c_dev *dev,
  341. struct kona_i2c_msg *msg)
  342. {
  343. unsigned char addr;
  344. if (msg->flags & I2C_M_TEN) {
  345. /* First byte is 11110XX0 where XX is upper 2 bits */
  346. addr = 0xf0 | ((msg->addr & 0x300) >> 7);
  347. if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
  348. return -EREMOTEIO;
  349. /* Second byte is the remaining 8 bits */
  350. addr = msg->addr & 0xff;
  351. if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
  352. return -EREMOTEIO;
  353. if (msg->flags & I2C_M_RD) {
  354. /* For read, send restart command */
  355. if (bcm_kona_send_i2c_cmd(dev, BCM_CMD_RESTART) < 0)
  356. return -EREMOTEIO;
  357. /* Then re-send the first byte with the read bit set */
  358. addr = 0xf0 | ((msg->addr & 0x300) >> 7) | 0x01;
  359. if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
  360. return -EREMOTEIO;
  361. }
  362. } else {
  363. addr = msg->addr << 1;
  364. if (msg->flags & I2C_M_RD)
  365. addr |= 1;
  366. if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
  367. return -EREMOTEIO;
  368. }
  369. return 0;
  370. }
  371. static void bcm_kona_i2c_enable_autosense(struct bcm_kona_i2c_dev *dev)
  372. {
  373. writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_AUTOSENSE_OFF_MASK,
  374. dev->base + CLKEN_OFFSET);
  375. }
  376. static void bcm_kona_i2c_config_timing(struct bcm_kona_i2c_dev *dev)
  377. {
  378. writel(readl(dev->base + HSTIM_OFFSET) & ~HSTIM_HS_MODE_MASK,
  379. dev->base + HSTIM_OFFSET);
  380. writel((dev->std_cfg->prescale << TIM_PRESCALE_SHIFT) |
  381. (dev->std_cfg->time_p << TIM_P_SHIFT) |
  382. (dev->std_cfg->no_div << TIM_NO_DIV_SHIFT) |
  383. (dev->std_cfg->time_div << TIM_DIV_SHIFT),
  384. dev->base + TIM_OFFSET);
  385. writel((dev->std_cfg->time_m << CLKEN_M_SHIFT) |
  386. (dev->std_cfg->time_n << CLKEN_N_SHIFT) |
  387. CLKEN_CLKEN_MASK, dev->base + CLKEN_OFFSET);
  388. }
  389. /* Master transfer function */
  390. static int bcm_kona_i2c_xfer(struct bcm_kona_i2c_dev *dev,
  391. struct kona_i2c_msg msgs[], int num)
  392. {
  393. struct kona_i2c_msg *pmsg;
  394. int rc = 0;
  395. int i;
  396. /* Enable pad output */
  397. writel(0, dev->base + PADCTL_OFFSET);
  398. /* Enable internal clocks */
  399. bcm_kona_i2c_enable_clock(dev);
  400. /* Send start command */
  401. rc = bcm_kona_send_i2c_cmd(dev, BCM_CMD_START);
  402. if (rc < 0) {
  403. printf("Start command failed rc = %d\n", rc);
  404. goto xfer_disable_pad;
  405. }
  406. /* Loop through all messages */
  407. for (i = 0; i < num; i++) {
  408. pmsg = &msgs[i];
  409. /* Send restart for subsequent messages */
  410. if ((i != 0) && ((pmsg->flags & I2C_M_NOSTART) == 0)) {
  411. rc = bcm_kona_send_i2c_cmd(dev, BCM_CMD_RESTART);
  412. if (rc < 0) {
  413. printf("restart cmd failed rc = %d\n", rc);
  414. goto xfer_send_stop;
  415. }
  416. }
  417. /* Send slave address */
  418. if (!(pmsg->flags & I2C_M_NOSTART)) {
  419. rc = bcm_kona_i2c_do_addr(dev, pmsg);
  420. if (rc < 0) {
  421. debug("NAK from addr %2.2x msg#%d rc = %d\n",
  422. pmsg->addr, i, rc);
  423. goto xfer_send_stop;
  424. }
  425. }
  426. /* Perform data transfer */
  427. if (pmsg->flags & I2C_M_RD) {
  428. rc = bcm_kona_i2c_read_fifo(dev, pmsg);
  429. if (rc < 0) {
  430. printf("read failure\n");
  431. goto xfer_send_stop;
  432. }
  433. } else {
  434. rc = bcm_kona_i2c_write_fifo(dev, pmsg);
  435. if (rc < 0) {
  436. printf("write failure");
  437. goto xfer_send_stop;
  438. }
  439. }
  440. }
  441. rc = num;
  442. xfer_send_stop:
  443. /* Send a STOP command */
  444. bcm_kona_send_i2c_cmd(dev, BCM_CMD_STOP);
  445. xfer_disable_pad:
  446. /* Disable pad output */
  447. writel(PADCTL_PAD_OUT_EN_MASK, dev->base + PADCTL_OFFSET);
  448. /* Stop internal clock */
  449. bcm_kona_i2c_disable_clock(dev);
  450. return rc;
  451. }
  452. static uint bcm_kona_i2c_assign_bus_speed(struct bcm_kona_i2c_dev *dev,
  453. uint speed)
  454. {
  455. switch (speed) {
  456. case I2C_SPEED_STANDARD_RATE:
  457. dev->std_cfg = &std_cfg_table[IC_SPEED_MODE_STANDARD];
  458. break;
  459. case I2C_SPEED_FAST_RATE:
  460. dev->std_cfg = &std_cfg_table[IC_SPEED_MODE_FAST];
  461. break;
  462. case I2C_SPEED_FAST_PLUS_RATE:
  463. dev->std_cfg = &std_cfg_table[IC_SPEED_MODE_FAST_PLUS];
  464. break;
  465. default:
  466. printf("%d hz bus speed not supported\n", speed);
  467. return -EINVAL;
  468. }
  469. dev->speed = speed;
  470. return 0;
  471. }
  472. static void bcm_kona_i2c_init(struct bcm_kona_i2c_dev *dev)
  473. {
  474. /* Parse bus speed */
  475. bcm_kona_i2c_assign_bus_speed(dev, dev->speed);
  476. /* Enable internal clocks */
  477. bcm_kona_i2c_enable_clock(dev);
  478. /* Configure internal dividers */
  479. bcm_kona_i2c_config_timing(dev);
  480. /* Disable timeout */
  481. writel(0, dev->base + TOUT_OFFSET);
  482. /* Enable autosense */
  483. bcm_kona_i2c_enable_autosense(dev);
  484. /* Enable TX FIFO */
  485. writel(TXFCR_FIFO_FLUSH_MASK | TXFCR_FIFO_EN_MASK,
  486. dev->base + TXFCR_OFFSET);
  487. /* Mask all interrupts */
  488. writel(0, dev->base + IER_OFFSET);
  489. /* Clear all pending interrupts */
  490. writel(ISR_CMDBUSY_MASK |
  491. ISR_READ_COMPLETE_MASK |
  492. ISR_SES_DONE_MASK |
  493. ISR_ERR_MASK |
  494. ISR_TXFIFOEMPTY_MASK | ISR_NOACK_MASK, dev->base + ISR_OFFSET);
  495. /* Enable the controller but leave it idle */
  496. bcm_kona_i2c_send_cmd_to_ctrl(dev, BCM_CMD_NOACTION);
  497. /* Disable pad output */
  498. writel(PADCTL_PAD_OUT_EN_MASK, dev->base + PADCTL_OFFSET);
  499. }
  500. /*
  501. * uboot layer
  502. */
  503. struct bcm_kona_i2c_dev *kona_get_dev(struct i2c_adapter *adap)
  504. {
  505. return &g_i2c_devs[adap->hwadapnr];
  506. }
  507. static void kona_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
  508. {
  509. struct bcm_kona_i2c_dev *dev = kona_get_dev(adap);
  510. if (clk_bsc_enable(dev->base))
  511. return;
  512. bcm_kona_i2c_init(dev);
  513. }
  514. static int kona_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
  515. int alen, uchar *buffer, int len)
  516. {
  517. /* msg[0] writes the addr, msg[1] reads the data */
  518. struct kona_i2c_msg msg[2];
  519. unsigned char msgbuf0[64];
  520. struct bcm_kona_i2c_dev *dev = kona_get_dev(adap);
  521. msg[0].addr = chip;
  522. msg[0].flags = 0;
  523. msg[0].len = 1;
  524. msg[0].buf = msgbuf0; /* msgbuf0 contains incrementing reg addr */
  525. msg[1].addr = chip;
  526. msg[1].flags = I2C_M_RD;
  527. /* msg[1].buf dest ptr increments each read */
  528. msgbuf0[0] = (unsigned char)addr;
  529. msg[1].buf = buffer;
  530. msg[1].len = len;
  531. if (bcm_kona_i2c_xfer(dev, msg, 2) < 0) {
  532. /* Sending 2 i2c messages */
  533. kona_i2c_init(adap, adap->speed, adap->slaveaddr);
  534. debug("I2C read: I/O error\n");
  535. return -EIO;
  536. }
  537. return 0;
  538. }
  539. static int kona_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
  540. int alen, uchar *buffer, int len)
  541. {
  542. struct kona_i2c_msg msg[1];
  543. unsigned char msgbuf0[64];
  544. unsigned int i;
  545. struct bcm_kona_i2c_dev *dev = kona_get_dev(adap);
  546. msg[0].addr = chip;
  547. msg[0].flags = 0;
  548. msg[0].len = 2; /* addr byte plus data */
  549. msg[0].buf = msgbuf0;
  550. for (i = 0; i < len; i++) {
  551. msgbuf0[0] = addr++;
  552. msgbuf0[1] = buffer[i];
  553. if (bcm_kona_i2c_xfer(dev, msg, 1) < 0) {
  554. kona_i2c_init(adap, adap->speed, adap->slaveaddr);
  555. debug("I2C write: I/O error\n");
  556. return -EIO;
  557. }
  558. }
  559. return 0;
  560. }
  561. static int kona_i2c_probe(struct i2c_adapter *adap, uchar chip)
  562. {
  563. uchar tmp;
  564. /*
  565. * read addr 0x0 of the given chip.
  566. */
  567. return kona_i2c_read(adap, chip, 0x0, 1, &tmp, 1);
  568. }
  569. static uint kona_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
  570. {
  571. struct bcm_kona_i2c_dev *dev = kona_get_dev(adap);
  572. return bcm_kona_i2c_assign_bus_speed(dev, speed);
  573. }
  574. /*
  575. * Register kona i2c adapters. Keep the order below so
  576. * that the bus number matches the adapter number.
  577. */
  578. #define DEF_ADAPTER(num) \
  579. U_BOOT_I2C_ADAP_COMPLETE(kona##num, kona_i2c_init, kona_i2c_probe, \
  580. kona_i2c_read, kona_i2c_write, \
  581. kona_i2c_set_bus_speed, DEF_SPD, 0x00, num)
  582. #ifdef CONFIG_SYS_I2C_BASE0
  583. DEF_ADAPTER(0)
  584. #endif
  585. #ifdef CONFIG_SYS_I2C_BASE1
  586. DEF_ADAPTER(1)
  587. #endif
  588. #ifdef CONFIG_SYS_I2C_BASE2
  589. DEF_ADAPTER(2)
  590. #endif
  591. #ifdef CONFIG_SYS_I2C_BASE3
  592. DEF_ADAPTER(3)
  593. #endif
  594. #ifdef CONFIG_SYS_I2C_BASE4
  595. DEF_ADAPTER(4)
  596. #endif
  597. #ifdef CONFIG_SYS_I2C_BASE5
  598. DEF_ADAPTER(5)
  599. #endif