iproc_i2c.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2018 Broadcom
  4. *
  5. */
  6. #include <asm/global_data.h>
  7. #include <asm/io.h>
  8. #include <common.h>
  9. #include <config.h>
  10. #include <dm.h>
  11. #include "errno.h"
  12. #include <i2c.h>
  13. #include "iproc_i2c.h"
  14. DECLARE_GLOBAL_DATA_PTR;
  15. struct iproc_i2c_regs {
  16. u32 cfg_reg;
  17. u32 timg_cfg;
  18. u32 addr_reg;
  19. u32 mstr_fifo_ctrl;
  20. u32 slv_fifo_ctrl;
  21. u32 bitbng_ctrl;
  22. u32 blnks[6]; /* Not to be used */
  23. u32 mstr_cmd;
  24. u32 slv_cmd;
  25. u32 evt_en;
  26. u32 evt_sts;
  27. u32 mstr_datawr;
  28. u32 mstr_datard;
  29. u32 slv_datawr;
  30. u32 slv_datard;
  31. };
  32. struct iproc_i2c {
  33. struct iproc_i2c_regs __iomem *base; /* register base */
  34. int bus_speed;
  35. int i2c_init_done;
  36. };
  37. /* Function to read a value from specified register. */
  38. static unsigned int iproc_i2c_reg_read(u32 *reg_addr)
  39. {
  40. unsigned int val;
  41. val = readl((void *)(reg_addr));
  42. return cpu_to_le32(val);
  43. }
  44. /* Function to write a value ('val') in to a specified register. */
  45. static int iproc_i2c_reg_write(u32 *reg_addr, unsigned int val)
  46. {
  47. val = cpu_to_le32(val);
  48. writel(val, (void *)(reg_addr));
  49. return 0;
  50. }
  51. #if defined(DEBUG)
  52. static int iproc_dump_i2c_regs(struct iproc_i2c *bus_prvdata)
  53. {
  54. struct iproc_i2c_regs *base = bus_prvdata->base;
  55. unsigned int regval;
  56. debug("\n----------------------------------------------\n");
  57. debug("%s: Dumping SMBus registers...\n", __func__);
  58. regval = iproc_i2c_reg_read(&base->cfg_reg);
  59. debug("CCB_SMB_CFG_REG=0x%08X\n", regval);
  60. regval = iproc_i2c_reg_read(&base->timg_cfg);
  61. debug("CCB_SMB_TIMGCFG_REG=0x%08X\n", regval);
  62. regval = iproc_i2c_reg_read(&base->addr_reg);
  63. debug("CCB_SMB_ADDR_REG=0x%08X\n", regval);
  64. regval = iproc_i2c_reg_read(&base->mstr_fifo_ctrl);
  65. debug("CCB_SMB_MSTRFIFOCTL_REG=0x%08X\n", regval);
  66. regval = iproc_i2c_reg_read(&base->slv_fifo_ctrl);
  67. debug("CCB_SMB_SLVFIFOCTL_REG=0x%08X\n", regval);
  68. regval = iproc_i2c_reg_read(&base->bitbng_ctrl);
  69. debug("CCB_SMB_BITBANGCTL_REG=0x%08X\n", regval);
  70. regval = iproc_i2c_reg_read(&base->mstr_cmd);
  71. debug("CCB_SMB_MSTRCMD_REG=0x%08X\n", regval);
  72. regval = iproc_i2c_reg_read(&base->slv_cmd);
  73. debug("CCB_SMB_SLVCMD_REG=0x%08X\n", regval);
  74. regval = iproc_i2c_reg_read(&base->evt_en);
  75. debug("CCB_SMB_EVTEN_REG=0x%08X\n", regval);
  76. regval = iproc_i2c_reg_read(&base->evt_sts);
  77. debug("CCB_SMB_EVTSTS_REG=0x%08X\n", regval);
  78. regval = iproc_i2c_reg_read(&base->mstr_datawr);
  79. debug("CCB_SMB_MSTRDATAWR_REG=0x%08X\n", regval);
  80. regval = iproc_i2c_reg_read(&base->mstr_datard);
  81. debug("CCB_SMB_MSTRDATARD_REG=0x%08X\n", regval);
  82. regval = iproc_i2c_reg_read(&base->slv_datawr);
  83. debug("CCB_SMB_SLVDATAWR_REG=0x%08X\n", regval);
  84. regval = iproc_i2c_reg_read(&base->slv_datard);
  85. debug("CCB_SMB_SLVDATARD_REG=0x%08X\n", regval);
  86. debug("----------------------------------------------\n\n");
  87. return 0;
  88. }
  89. #else
  90. static int iproc_dump_i2c_regs(struct iproc_i2c *bus_prvdata)
  91. {
  92. return 0;
  93. }
  94. #endif
  95. /*
  96. * Function to ensure that the previous transaction was completed before
  97. * initiating a new transaction. It can also be used in polling mode to
  98. * check status of completion of a command
  99. */
  100. static int iproc_i2c_startbusy_wait(struct iproc_i2c *bus_prvdata)
  101. {
  102. struct iproc_i2c_regs *base = bus_prvdata->base;
  103. unsigned int regval;
  104. regval = iproc_i2c_reg_read(&base->mstr_cmd);
  105. /* Check if an operation is in progress. During probe it won't be.
  106. * But when shutdown/remove was called we want to make sure that
  107. * the transaction in progress completed
  108. */
  109. if (regval & CCB_SMB_MSTRSTARTBUSYCMD_MASK) {
  110. unsigned int i = 0;
  111. do {
  112. mdelay(10);
  113. i++;
  114. regval = iproc_i2c_reg_read(&base->mstr_cmd);
  115. /* If start-busy bit cleared, exit the loop */
  116. } while ((regval & CCB_SMB_MSTRSTARTBUSYCMD_MASK) &&
  117. (i < IPROC_SMB_MAX_RETRIES));
  118. if (i >= IPROC_SMB_MAX_RETRIES) {
  119. pr_err("%s: START_BUSY bit didn't clear, exiting\n",
  120. __func__);
  121. return -ETIMEDOUT;
  122. }
  123. }
  124. return 0;
  125. }
  126. /*
  127. * This function set clock frequency for SMBus block. As per hardware
  128. * engineering, the clock frequency can be changed dynamically.
  129. */
  130. static int iproc_i2c_set_clk_freq(struct iproc_i2c *bus_prvdata)
  131. {
  132. struct iproc_i2c_regs *base = bus_prvdata->base;
  133. unsigned int regval;
  134. regval = iproc_i2c_reg_read(&base->timg_cfg);
  135. switch (bus_prvdata->bus_speed) {
  136. case I2C_SPEED_STANDARD_RATE:
  137. regval &= ~CCB_SMB_TIMGCFG_MODE400_MASK;
  138. break;
  139. case I2C_SPEED_FAST_RATE:
  140. regval |= CCB_SMB_TIMGCFG_MODE400_MASK;
  141. break;
  142. default:
  143. return -EINVAL;
  144. }
  145. iproc_i2c_reg_write(&base->timg_cfg, regval);
  146. return 0;
  147. }
  148. static int iproc_i2c_init(struct udevice *bus)
  149. {
  150. struct iproc_i2c *bus_prvdata = dev_get_priv(bus);
  151. struct iproc_i2c_regs *base = bus_prvdata->base;
  152. unsigned int regval;
  153. debug("\nEntering %s\n", __func__);
  154. /* Put controller in reset */
  155. regval = iproc_i2c_reg_read(&base->cfg_reg);
  156. regval |= CCB_SMB_CFG_RST_MASK;
  157. regval &= ~CCB_SMB_CFG_SMBEN_MASK;
  158. iproc_i2c_reg_write(&base->cfg_reg, regval);
  159. /* Wait 100 usec as per spec */
  160. udelay(100);
  161. /* bring controller out of reset */
  162. regval &= ~CCB_SMB_CFG_RST_MASK;
  163. iproc_i2c_reg_write(&base->cfg_reg, regval);
  164. /* Flush Tx, Rx FIFOs. Note we are setting the Rx FIFO threshold to 0.
  165. * May be OK since we are setting RX_EVENT and RX_FIFO_FULL interrupts
  166. */
  167. regval = CCB_SMB_MSTRRXFIFOFLSH_MASK | CCB_SMB_MSTRTXFIFOFLSH_MASK;
  168. iproc_i2c_reg_write(&base->mstr_fifo_ctrl, regval);
  169. /* Enable SMbus block. Note, we are setting MASTER_RETRY_COUNT to zero
  170. * since there will be only one master
  171. */
  172. regval = iproc_i2c_reg_read(&base->cfg_reg);
  173. regval |= CCB_SMB_CFG_SMBEN_MASK;
  174. iproc_i2c_reg_write(&base->cfg_reg, regval);
  175. /* Set default clock frequency */
  176. iproc_i2c_set_clk_freq(bus_prvdata);
  177. /* Disable intrs */
  178. iproc_i2c_reg_write(&base->evt_en, 0);
  179. /* Clear intrs (W1TC) */
  180. regval = iproc_i2c_reg_read(&base->evt_sts);
  181. iproc_i2c_reg_write(&base->evt_sts, regval);
  182. bus_prvdata->i2c_init_done = 1;
  183. iproc_dump_i2c_regs(bus_prvdata);
  184. debug("%s: Init successful\n", __func__);
  185. return 0;
  186. }
  187. /*
  188. * This function copies data to SMBus's Tx FIFO. Valid for write transactions
  189. * only
  190. *
  191. * base_addr: Mapped address of this SMBus instance
  192. * dev_addr: SMBus (I2C) device address. We are assuming 7-bit addresses
  193. * initially
  194. * info: Data to copy in to Tx FIFO. For read commands, the size should be
  195. * set to zero by the caller
  196. *
  197. */
  198. static void iproc_i2c_write_trans_data(struct iproc_i2c *bus_prvdata,
  199. unsigned short dev_addr,
  200. struct iproc_xact_info *info)
  201. {
  202. struct iproc_i2c_regs *base = bus_prvdata->base;
  203. unsigned int regval;
  204. unsigned int i;
  205. unsigned int num_data_bytes = 0;
  206. debug("%s: dev_addr=0x%X cmd_valid=%d cmd=0x%02x size=%u proto=%d buf[] %x\n",
  207. __func__, dev_addr, info->cmd_valid,
  208. info->command, info->size, info->smb_proto, info->data[0]);
  209. /* Write SMBus device address first */
  210. /* Note, we are assuming 7-bit addresses for now. For 10-bit addresses,
  211. * we may have one more write to send the upper 3 bits of 10-bit addr
  212. */
  213. iproc_i2c_reg_write(&base->mstr_datawr, dev_addr);
  214. /* If the protocol needs command code, copy it */
  215. if (info->cmd_valid)
  216. iproc_i2c_reg_write(&base->mstr_datawr, info->command);
  217. /* Depending on the SMBus protocol, we need to write additional
  218. * transaction data in to Tx FIFO. Refer to section 5.5 of SMBus
  219. * spec for sequence for a transaction
  220. */
  221. switch (info->smb_proto) {
  222. case SMBUS_PROT_RECV_BYTE:
  223. /* No additional data to be written */
  224. num_data_bytes = 0;
  225. break;
  226. case SMBUS_PROT_SEND_BYTE:
  227. num_data_bytes = info->size;
  228. break;
  229. case SMBUS_PROT_RD_BYTE:
  230. case SMBUS_PROT_RD_WORD:
  231. case SMBUS_PROT_BLK_RD:
  232. /* Write slave address with R/W~ set (bit #0) */
  233. iproc_i2c_reg_write(&base->mstr_datawr,
  234. dev_addr | 0x1);
  235. num_data_bytes = 0;
  236. break;
  237. case SMBUS_PROT_BLK_WR_BLK_RD_PROC_CALL:
  238. iproc_i2c_reg_write(&base->mstr_datawr,
  239. dev_addr | 0x1 |
  240. CCB_SMB_MSTRWRSTS_MASK);
  241. num_data_bytes = 0;
  242. break;
  243. case SMBUS_PROT_WR_BYTE:
  244. case SMBUS_PROT_WR_WORD:
  245. /* No additional bytes to be written.
  246. * Data portion is written in the
  247. * 'for' loop below
  248. */
  249. num_data_bytes = info->size;
  250. break;
  251. case SMBUS_PROT_BLK_WR:
  252. /* 3rd byte is byte count */
  253. iproc_i2c_reg_write(&base->mstr_datawr, info->size);
  254. num_data_bytes = info->size;
  255. break;
  256. default:
  257. return;
  258. }
  259. /* Copy actual data from caller, next. In general, for reads,
  260. * no data is copied
  261. */
  262. for (i = 0; num_data_bytes; --num_data_bytes, i++) {
  263. /* For the last byte, set MASTER_WR_STATUS bit */
  264. regval = (num_data_bytes == 1) ?
  265. info->data[i] | CCB_SMB_MSTRWRSTS_MASK :
  266. info->data[i];
  267. iproc_i2c_reg_write(&base->mstr_datawr, regval);
  268. }
  269. }
  270. static int iproc_i2c_data_send(struct iproc_i2c *bus_prvdata,
  271. unsigned short addr,
  272. struct iproc_xact_info *info)
  273. {
  274. struct iproc_i2c_regs *base = bus_prvdata->base;
  275. int rc, retry = 3;
  276. unsigned int regval;
  277. /* Make sure the previous transaction completed */
  278. rc = iproc_i2c_startbusy_wait(bus_prvdata);
  279. if (rc < 0) {
  280. pr_err("%s: Send: bus is busy, exiting\n", __func__);
  281. return rc;
  282. }
  283. /* Write transaction bytes to Tx FIFO */
  284. iproc_i2c_write_trans_data(bus_prvdata, addr, info);
  285. /* Program master command register (0x30) with protocol type and set
  286. * start_busy_command bit to initiate the write transaction
  287. */
  288. regval = (info->smb_proto << CCB_SMB_MSTRSMBUSPROTO_SHIFT) |
  289. CCB_SMB_MSTRSTARTBUSYCMD_MASK;
  290. iproc_i2c_reg_write(&base->mstr_cmd, regval);
  291. /* Check for Master status */
  292. regval = iproc_i2c_reg_read(&base->mstr_cmd);
  293. while (regval & CCB_SMB_MSTRSTARTBUSYCMD_MASK) {
  294. mdelay(10);
  295. if (retry-- <= 0)
  296. break;
  297. regval = iproc_i2c_reg_read(&base->mstr_cmd);
  298. }
  299. /* If start_busy bit cleared, check if there are any errors */
  300. if (!(regval & CCB_SMB_MSTRSTARTBUSYCMD_MASK)) {
  301. /* start_busy bit cleared, check master_status field now */
  302. regval &= CCB_SMB_MSTRSTS_MASK;
  303. regval >>= CCB_SMB_MSTRSTS_SHIFT;
  304. if (regval != MSTR_STS_XACT_SUCCESS) {
  305. /* Error We can flush Tx FIFO here */
  306. pr_err("%s: ERROR: Error in transaction %u, exiting\n",
  307. __func__, regval);
  308. return -EREMOTEIO;
  309. }
  310. }
  311. return 0;
  312. }
  313. static int iproc_i2c_data_recv(struct iproc_i2c *bus_prvdata,
  314. unsigned short addr,
  315. struct iproc_xact_info *info,
  316. unsigned int *num_bytes_read)
  317. {
  318. struct iproc_i2c_regs *base = bus_prvdata->base;
  319. int rc, retry = 3;
  320. unsigned int regval;
  321. /* Make sure the previous transaction completed */
  322. rc = iproc_i2c_startbusy_wait(bus_prvdata);
  323. if (rc < 0) {
  324. pr_err("%s: Receive: Bus is busy, exiting\n", __func__);
  325. return rc;
  326. }
  327. /* Program all transaction bytes into master Tx FIFO */
  328. iproc_i2c_write_trans_data(bus_prvdata, addr, info);
  329. /* Program master command register (0x30) with protocol type and set
  330. * start_busy_command bit to initiate the write transaction
  331. */
  332. regval = (info->smb_proto << CCB_SMB_MSTRSMBUSPROTO_SHIFT) |
  333. CCB_SMB_MSTRSTARTBUSYCMD_MASK | info->size;
  334. iproc_i2c_reg_write(&base->mstr_cmd, regval);
  335. /* Check for Master status */
  336. regval = iproc_i2c_reg_read(&base->mstr_cmd);
  337. while (regval & CCB_SMB_MSTRSTARTBUSYCMD_MASK) {
  338. udelay(1000);
  339. if (retry-- <= 0)
  340. break;
  341. regval = iproc_i2c_reg_read(&base->mstr_cmd);
  342. }
  343. /* If start_busy bit cleared, check if there are any errors */
  344. if (!(regval & CCB_SMB_MSTRSTARTBUSYCMD_MASK)) {
  345. /* start_busy bit cleared, check master_status field now */
  346. regval &= CCB_SMB_MSTRSTS_MASK;
  347. regval >>= CCB_SMB_MSTRSTS_SHIFT;
  348. if (regval != MSTR_STS_XACT_SUCCESS) {
  349. /* We can flush Tx FIFO here */
  350. pr_err("%s: Error in transaction %d, exiting\n",
  351. __func__, regval);
  352. return -EREMOTEIO;
  353. }
  354. }
  355. /* Read received byte(s), after TX out address etc */
  356. regval = iproc_i2c_reg_read(&base->mstr_datard);
  357. /* For block read, protocol (hw) returns byte count,
  358. * as the first byte
  359. */
  360. if (info->smb_proto == SMBUS_PROT_BLK_RD) {
  361. int i;
  362. *num_bytes_read = regval & CCB_SMB_MSTRRDDATA_MASK;
  363. /* Limit to reading a max of 32 bytes only; just a safeguard.
  364. * If # bytes read is a number > 32, check transaction set up,
  365. * and contact hw engg. Assumption: PEC is disabled
  366. */
  367. for (i = 0;
  368. (i < *num_bytes_read) && (i < I2C_SMBUS_BLOCK_MAX);
  369. i++) {
  370. /* Read Rx FIFO for data bytes */
  371. regval = iproc_i2c_reg_read(&base->mstr_datard);
  372. info->data[i] = regval & CCB_SMB_MSTRRDDATA_MASK;
  373. }
  374. } else {
  375. /* 1 Byte data */
  376. *info->data = regval & CCB_SMB_MSTRRDDATA_MASK;
  377. *num_bytes_read = 1;
  378. }
  379. return 0;
  380. }
  381. static int i2c_write_byte(struct iproc_i2c *bus_prvdata,
  382. u8 devaddr, u8 regoffset, u8 value)
  383. {
  384. int rc;
  385. struct iproc_xact_info info;
  386. devaddr <<= 1;
  387. info.cmd_valid = 1;
  388. info.command = (unsigned char)regoffset;
  389. info.data = &value;
  390. info.size = 1;
  391. info.flags = 0;
  392. info.smb_proto = SMBUS_PROT_WR_BYTE;
  393. /* Refer to i2c_smbus_write_byte params passed. */
  394. rc = iproc_i2c_data_send(bus_prvdata, devaddr, &info);
  395. if (rc < 0) {
  396. pr_err("%s: %s error accessing device 0x%X\n",
  397. __func__, "Write", devaddr);
  398. return -EREMOTEIO;
  399. }
  400. return 0;
  401. }
  402. int i2c_write(struct udevice *bus,
  403. uchar chip, uint regaddr, int alen, uchar *buffer, int len)
  404. {
  405. struct iproc_i2c *bus_prvdata = dev_get_priv(bus);
  406. int i, data_len;
  407. u8 *data;
  408. if (len > 256) {
  409. pr_err("I2C write: address out of range\n");
  410. return 1;
  411. }
  412. if (len < 1) {
  413. pr_err("I2C write: Need offset addr and value\n");
  414. return 1;
  415. }
  416. /* buffer contains offset addr followed by value to be written */
  417. regaddr = buffer[0];
  418. data = &buffer[1];
  419. data_len = len - 1;
  420. for (i = 0; i < data_len; i++) {
  421. if (i2c_write_byte(bus_prvdata, chip, regaddr + i, data[i])) {
  422. pr_err("I2C write (%d): I/O error\n", i);
  423. iproc_i2c_init(bus);
  424. return 1;
  425. }
  426. }
  427. return 0;
  428. }
  429. static int i2c_read_byte(struct iproc_i2c *bus_prvdata,
  430. u8 devaddr, u8 regoffset, u8 *value)
  431. {
  432. int rc;
  433. struct iproc_xact_info info;
  434. unsigned int num_bytes_read = 0;
  435. devaddr <<= 1;
  436. info.cmd_valid = 1;
  437. info.command = (unsigned char)regoffset;
  438. info.data = value;
  439. info.size = 1;
  440. info.flags = 0;
  441. info.smb_proto = SMBUS_PROT_RD_BYTE;
  442. /* Refer to i2c_smbus_read_byte for params passed. */
  443. rc = iproc_i2c_data_recv(bus_prvdata, devaddr, &info, &num_bytes_read);
  444. if (rc < 0) {
  445. pr_err("%s: %s error accessing device 0x%X\n",
  446. __func__, "Read", devaddr);
  447. return -EREMOTEIO;
  448. }
  449. return 0;
  450. }
  451. int i2c_read(struct udevice *bus,
  452. uchar chip, uint addr, int alen, uchar *buffer, int len)
  453. {
  454. struct iproc_i2c *bus_prvdata = dev_get_priv(bus);
  455. int i;
  456. if (len > 256) {
  457. pr_err("I2C read: address out of range\n");
  458. return 1;
  459. }
  460. for (i = 0; i < len; i++) {
  461. if (i2c_read_byte(bus_prvdata, chip, addr + i, &buffer[i])) {
  462. pr_err("I2C read: I/O error\n");
  463. iproc_i2c_init(bus);
  464. return 1;
  465. }
  466. }
  467. return 0;
  468. }
  469. static int iproc_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
  470. {
  471. int ret = 0;
  472. debug("%s: %d messages\n", __func__, nmsgs);
  473. for (; nmsgs > 0; nmsgs--, msg++) {
  474. if (msg->flags & I2C_M_RD)
  475. ret = i2c_read(bus, msg->addr, 0, 0,
  476. msg->buf, msg->len);
  477. else
  478. ret = i2c_write(bus, msg->addr, 0, 0,
  479. msg->buf, msg->len);
  480. }
  481. return ret;
  482. }
  483. static int iproc_i2c_probe_chip(struct udevice *bus, uint chip_addr,
  484. uint chip_flags)
  485. {
  486. struct iproc_i2c *bus_prvdata = dev_get_priv(bus);
  487. struct iproc_i2c_regs *base = bus_prvdata->base;
  488. u32 regval;
  489. debug("\n%s: Entering chip probe\n", __func__);
  490. /* Init internal regs, disable intrs (and then clear intrs), set fifo
  491. * thresholds, etc.
  492. */
  493. if (!bus_prvdata->i2c_init_done)
  494. iproc_i2c_init(bus);
  495. regval = (chip_addr << 1);
  496. iproc_i2c_reg_write(&base->mstr_datawr, regval);
  497. regval = ((SMBUS_PROT_QUICK_CMD << CCB_SMB_MSTRSMBUSPROTO_SHIFT) |
  498. (1 << CCB_SMB_MSTRSTARTBUSYCMD_SHIFT));
  499. iproc_i2c_reg_write(&base->mstr_cmd, regval);
  500. do {
  501. udelay(100);
  502. regval = iproc_i2c_reg_read(&base->mstr_cmd);
  503. regval &= CCB_SMB_MSTRSTARTBUSYCMD_MASK;
  504. } while (regval);
  505. regval = iproc_i2c_reg_read(&base->mstr_cmd);
  506. if ((regval & CCB_SMB_MSTRSTS_MASK) != 0)
  507. return -1;
  508. iproc_dump_i2c_regs(bus_prvdata);
  509. debug("%s: chip probe successful\n", __func__);
  510. return 0;
  511. }
  512. static int iproc_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
  513. {
  514. struct iproc_i2c *bus_prvdata = dev_get_priv(bus);
  515. bus_prvdata->bus_speed = speed;
  516. return iproc_i2c_set_clk_freq(bus_prvdata);
  517. }
  518. /**
  519. * i2c_get_bus_speed - get i2c bus speed
  520. *
  521. * This function returns the speed of operation in Hz
  522. */
  523. int iproc_i2c_get_bus_speed(struct udevice *bus)
  524. {
  525. struct iproc_i2c *bus_prvdata = dev_get_priv(bus);
  526. struct iproc_i2c_regs *base = bus_prvdata->base;
  527. unsigned int regval;
  528. int ret = 0;
  529. regval = iproc_i2c_reg_read(&base->timg_cfg);
  530. regval = (regval & CCB_SMB_TIMGCFG_MODE400_MASK) >>
  531. CCB_SMB_TIMGCFG_MODE400_SHIFT;
  532. switch (regval) {
  533. case 0:
  534. ret = I2C_SPEED_STANDARD_RATE;
  535. break;
  536. case 1:
  537. ret = I2C_SPEED_FAST_RATE;
  538. break;
  539. default:
  540. ret = -EINVAL;
  541. break;
  542. }
  543. return ret;
  544. }
  545. static int iproc_i2c_probe(struct udevice *bus)
  546. {
  547. return iproc_i2c_init(bus);
  548. }
  549. static int iproc_i2c_of_to_plat(struct udevice *bus)
  550. {
  551. struct iproc_i2c *bus_prvdata = dev_get_priv(bus);
  552. int node = dev_of_offset(bus);
  553. const void *blob = gd->fdt_blob;
  554. bus_prvdata->base = map_physmem(dev_read_addr(bus),
  555. sizeof(void *),
  556. MAP_NOCACHE);
  557. bus_prvdata->bus_speed =
  558. fdtdec_get_int(blob, node, "bus-frequency",
  559. I2C_SPEED_STANDARD_RATE);
  560. return 0;
  561. }
  562. static const struct dm_i2c_ops iproc_i2c_ops = {
  563. .xfer = iproc_i2c_xfer,
  564. .probe_chip = iproc_i2c_probe_chip,
  565. .set_bus_speed = iproc_i2c_set_bus_speed,
  566. .get_bus_speed = iproc_i2c_get_bus_speed,
  567. };
  568. static const struct udevice_id iproc_i2c_ids[] = {
  569. { .compatible = "brcm,iproc-i2c" },
  570. { }
  571. };
  572. U_BOOT_DRIVER(iproc_i2c) = {
  573. .name = "iproc_i2c",
  574. .id = UCLASS_I2C,
  575. .of_match = iproc_i2c_ids,
  576. .of_to_plat = iproc_i2c_of_to_plat,
  577. .probe = iproc_i2c_probe,
  578. .priv_auto = sizeof(struct iproc_i2c),
  579. .ops = &iproc_i2c_ops,
  580. .flags = DM_FLAG_PRE_RELOC,
  581. };