imx_lpi2c.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2016 Freescale Semiconductors, Inc.
  4. */
  5. #include <common.h>
  6. #include <errno.h>
  7. #include <log.h>
  8. #include <asm/io.h>
  9. #include <asm/arch/clock.h>
  10. #include <asm/arch/imx-regs.h>
  11. #include <imx_lpi2c.h>
  12. #include <asm/arch/sys_proto.h>
  13. #include <dm.h>
  14. #include <fdtdec.h>
  15. #include <i2c.h>
  16. #include <dm/device_compat.h>
  17. #define LPI2C_FIFO_SIZE 4
  18. #define LPI2C_NACK_TOUT_MS 1
  19. #define LPI2C_TIMEOUT_MS 100
  20. static int bus_i2c_init(struct udevice *bus, int speed);
  21. /* Weak linked function for overridden by some SoC power function */
  22. int __weak init_i2c_power(unsigned i2c_num)
  23. {
  24. return 0;
  25. }
  26. static int imx_lpci2c_check_busy_bus(const struct imx_lpi2c_reg *regs)
  27. {
  28. lpi2c_status_t result = LPI2C_SUCESS;
  29. u32 status;
  30. status = readl(&regs->msr);
  31. if ((status & LPI2C_MSR_BBF_MASK) && !(status & LPI2C_MSR_MBF_MASK))
  32. result = LPI2C_BUSY;
  33. return result;
  34. }
  35. static int imx_lpci2c_check_clear_error(struct imx_lpi2c_reg *regs)
  36. {
  37. lpi2c_status_t result = LPI2C_SUCESS;
  38. u32 val, status;
  39. status = readl(&regs->msr);
  40. /* errors to check for */
  41. status &= LPI2C_MSR_NDF_MASK | LPI2C_MSR_ALF_MASK |
  42. LPI2C_MSR_FEF_MASK | LPI2C_MSR_PLTF_MASK;
  43. if (status) {
  44. if (status & LPI2C_MSR_PLTF_MASK)
  45. result = LPI2C_PIN_LOW_TIMEOUT_ERR;
  46. else if (status & LPI2C_MSR_ALF_MASK)
  47. result = LPI2C_ARB_LOST_ERR;
  48. else if (status & LPI2C_MSR_NDF_MASK)
  49. result = LPI2C_NAK_ERR;
  50. else if (status & LPI2C_MSR_FEF_MASK)
  51. result = LPI2C_FIFO_ERR;
  52. /* clear status flags */
  53. writel(0x7f00, &regs->msr);
  54. /* reset fifos */
  55. val = readl(&regs->mcr);
  56. val |= LPI2C_MCR_RRF_MASK | LPI2C_MCR_RTF_MASK;
  57. writel(val, &regs->mcr);
  58. }
  59. return result;
  60. }
  61. static int bus_i2c_wait_for_tx_ready(struct imx_lpi2c_reg *regs)
  62. {
  63. lpi2c_status_t result = LPI2C_SUCESS;
  64. u32 txcount = 0;
  65. ulong start_time = get_timer(0);
  66. do {
  67. txcount = LPI2C_MFSR_TXCOUNT(readl(&regs->mfsr));
  68. txcount = LPI2C_FIFO_SIZE - txcount;
  69. result = imx_lpci2c_check_clear_error(regs);
  70. if (result) {
  71. debug("i2c: wait for tx ready: result 0x%x\n", result);
  72. return result;
  73. }
  74. if (get_timer(start_time) > LPI2C_TIMEOUT_MS) {
  75. debug("i2c: wait for tx ready: timeout\n");
  76. return -1;
  77. }
  78. } while (!txcount);
  79. return result;
  80. }
  81. static int bus_i2c_send(struct udevice *bus, u8 *txbuf, int len)
  82. {
  83. struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus);
  84. struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)(i2c_bus->base);
  85. lpi2c_status_t result = LPI2C_SUCESS;
  86. /* empty tx */
  87. if (!len)
  88. return result;
  89. while (len--) {
  90. result = bus_i2c_wait_for_tx_ready(regs);
  91. if (result) {
  92. debug("i2c: send wait for tx ready: %d\n", result);
  93. return result;
  94. }
  95. writel(*txbuf++, &regs->mtdr);
  96. }
  97. return result;
  98. }
  99. static int bus_i2c_receive(struct udevice *bus, u8 *rxbuf, int len)
  100. {
  101. struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus);
  102. struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)(i2c_bus->base);
  103. lpi2c_status_t result = LPI2C_SUCESS;
  104. u32 val;
  105. ulong start_time = get_timer(0);
  106. /* empty read */
  107. if (!len)
  108. return result;
  109. result = bus_i2c_wait_for_tx_ready(regs);
  110. if (result) {
  111. debug("i2c: receive wait fot tx ready: %d\n", result);
  112. return result;
  113. }
  114. /* clear all status flags */
  115. writel(0x7f00, &regs->msr);
  116. /* send receive command */
  117. val = LPI2C_MTDR_CMD(0x1) | LPI2C_MTDR_DATA(len - 1);
  118. writel(val, &regs->mtdr);
  119. while (len--) {
  120. do {
  121. result = imx_lpci2c_check_clear_error(regs);
  122. if (result) {
  123. debug("i2c: receive check clear error: %d\n",
  124. result);
  125. return result;
  126. }
  127. if (get_timer(start_time) > LPI2C_TIMEOUT_MS) {
  128. debug("i2c: receive mrdr: timeout\n");
  129. return -1;
  130. }
  131. val = readl(&regs->mrdr);
  132. } while (val & LPI2C_MRDR_RXEMPTY_MASK);
  133. *rxbuf++ = LPI2C_MRDR_DATA(val);
  134. }
  135. return result;
  136. }
  137. static int bus_i2c_start(struct udevice *bus, u8 addr, u8 dir)
  138. {
  139. lpi2c_status_t result;
  140. struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus);
  141. struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)(i2c_bus->base);
  142. u32 val;
  143. result = imx_lpci2c_check_busy_bus(regs);
  144. if (result) {
  145. debug("i2c: start check busy bus: 0x%x\n", result);
  146. /* Try to init the lpi2c then check the bus busy again */
  147. bus_i2c_init(bus, I2C_SPEED_STANDARD_RATE);
  148. result = imx_lpci2c_check_busy_bus(regs);
  149. if (result) {
  150. printf("i2c: Error check busy bus: 0x%x\n", result);
  151. return result;
  152. }
  153. }
  154. /* clear all status flags */
  155. writel(0x7f00, &regs->msr);
  156. /* turn off auto-stop condition */
  157. val = readl(&regs->mcfgr1) & ~LPI2C_MCFGR1_AUTOSTOP_MASK;
  158. writel(val, &regs->mcfgr1);
  159. /* wait tx fifo ready */
  160. result = bus_i2c_wait_for_tx_ready(regs);
  161. if (result) {
  162. debug("i2c: start wait for tx ready: 0x%x\n", result);
  163. return result;
  164. }
  165. /* issue start command */
  166. val = LPI2C_MTDR_CMD(0x4) | (addr << 0x1) | dir;
  167. writel(val, &regs->mtdr);
  168. return result;
  169. }
  170. static int bus_i2c_stop(struct udevice *bus)
  171. {
  172. lpi2c_status_t result;
  173. struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus);
  174. struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)(i2c_bus->base);
  175. u32 status;
  176. ulong start_time;
  177. result = bus_i2c_wait_for_tx_ready(regs);
  178. if (result) {
  179. debug("i2c: stop wait for tx ready: 0x%x\n", result);
  180. return result;
  181. }
  182. /* send stop command */
  183. writel(LPI2C_MTDR_CMD(0x2), &regs->mtdr);
  184. start_time = get_timer(0);
  185. while (1) {
  186. status = readl(&regs->msr);
  187. result = imx_lpci2c_check_clear_error(regs);
  188. /* stop detect flag */
  189. if (status & LPI2C_MSR_SDF_MASK) {
  190. /* clear stop flag */
  191. status &= LPI2C_MSR_SDF_MASK;
  192. writel(status, &regs->msr);
  193. break;
  194. }
  195. if (get_timer(start_time) > LPI2C_NACK_TOUT_MS) {
  196. debug("stop timeout\n");
  197. return -ETIMEDOUT;
  198. }
  199. }
  200. return result;
  201. }
  202. static int bus_i2c_read(struct udevice *bus, u32 chip, u8 *buf, int len)
  203. {
  204. lpi2c_status_t result;
  205. result = bus_i2c_start(bus, chip, 1);
  206. if (result)
  207. return result;
  208. result = bus_i2c_receive(bus, buf, len);
  209. if (result)
  210. return result;
  211. return result;
  212. }
  213. static int bus_i2c_write(struct udevice *bus, u32 chip, u8 *buf, int len)
  214. {
  215. lpi2c_status_t result;
  216. result = bus_i2c_start(bus, chip, 0);
  217. if (result)
  218. return result;
  219. result = bus_i2c_send(bus, buf, len);
  220. if (result)
  221. return result;
  222. return result;
  223. }
  224. u32 __weak imx_get_i2cclk(u32 i2c_num)
  225. {
  226. return 0;
  227. }
  228. static int bus_i2c_set_bus_speed(struct udevice *bus, int speed)
  229. {
  230. struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus);
  231. struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)(i2c_bus->base);
  232. u32 val;
  233. u32 preescale = 0, best_pre = 0, clkhi = 0;
  234. u32 best_clkhi = 0, abs_error = 0, rate;
  235. u32 error = 0xffffffff;
  236. u32 clock_rate;
  237. bool mode;
  238. int i;
  239. if (IS_ENABLED(CONFIG_CLK)) {
  240. clock_rate = clk_get_rate(&i2c_bus->per_clk);
  241. if (clock_rate <= 0) {
  242. dev_err(bus, "Failed to get i2c clk: %d\n", clock_rate);
  243. return clock_rate;
  244. }
  245. } else {
  246. clock_rate = imx_get_i2cclk(dev_seq(bus));
  247. if (!clock_rate)
  248. return -EPERM;
  249. }
  250. mode = (readl(&regs->mcr) & LPI2C_MCR_MEN_MASK) >> LPI2C_MCR_MEN_SHIFT;
  251. /* disable master mode */
  252. val = readl(&regs->mcr) & ~LPI2C_MCR_MEN_MASK;
  253. writel(val | LPI2C_MCR_MEN(0), &regs->mcr);
  254. for (preescale = 1; (preescale <= 128) &&
  255. (error != 0); preescale = 2 * preescale) {
  256. for (clkhi = 1; clkhi < 32; clkhi++) {
  257. if (clkhi == 1)
  258. rate = (clock_rate / preescale) / (1 + 3 + 2 + 2 / preescale);
  259. else
  260. rate = (clock_rate / preescale / (3 * clkhi + 2 + 2 / preescale));
  261. abs_error = speed > rate ? speed - rate : rate - speed;
  262. if (abs_error < error) {
  263. best_pre = preescale;
  264. best_clkhi = clkhi;
  265. error = abs_error;
  266. if (abs_error == 0)
  267. break;
  268. }
  269. }
  270. }
  271. /* Standard, fast, fast mode plus and ultra-fast transfers. */
  272. val = LPI2C_MCCR0_CLKHI(best_clkhi);
  273. if (best_clkhi < 2)
  274. val |= LPI2C_MCCR0_CLKLO(3) | LPI2C_MCCR0_SETHOLD(2) | LPI2C_MCCR0_DATAVD(1);
  275. else
  276. val |= LPI2C_MCCR0_CLKLO(2 * best_clkhi) | LPI2C_MCCR0_SETHOLD(best_clkhi) |
  277. LPI2C_MCCR0_DATAVD(best_clkhi / 2);
  278. writel(val, &regs->mccr0);
  279. for (i = 0; i < 8; i++) {
  280. if (best_pre == (1 << i)) {
  281. best_pre = i;
  282. break;
  283. }
  284. }
  285. val = readl(&regs->mcfgr1) & ~LPI2C_MCFGR1_PRESCALE_MASK;
  286. writel(val | LPI2C_MCFGR1_PRESCALE(best_pre), &regs->mcfgr1);
  287. if (mode) {
  288. val = readl(&regs->mcr) & ~LPI2C_MCR_MEN_MASK;
  289. writel(val | LPI2C_MCR_MEN(1), &regs->mcr);
  290. }
  291. return 0;
  292. }
  293. static int bus_i2c_init(struct udevice *bus, int speed)
  294. {
  295. u32 val;
  296. int ret;
  297. struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus);
  298. struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)(i2c_bus->base);
  299. /* reset peripheral */
  300. writel(LPI2C_MCR_RST_MASK, &regs->mcr);
  301. writel(0x0, &regs->mcr);
  302. /* Disable Dozen mode */
  303. writel(LPI2C_MCR_DBGEN(0) | LPI2C_MCR_DOZEN(1), &regs->mcr);
  304. /* host request disable, active high, external pin */
  305. val = readl(&regs->mcfgr0);
  306. val &= (~(LPI2C_MCFGR0_HREN_MASK | LPI2C_MCFGR0_HRPOL_MASK |
  307. LPI2C_MCFGR0_HRSEL_MASK));
  308. val |= LPI2C_MCFGR0_HRPOL(0x1);
  309. writel(val, &regs->mcfgr0);
  310. /* pincfg and ignore ack */
  311. val = readl(&regs->mcfgr1);
  312. val &= ~(LPI2C_MCFGR1_PINCFG_MASK | LPI2C_MCFGR1_IGNACK_MASK);
  313. val |= LPI2C_MCFGR1_PINCFG(0x0); /* 2 pin open drain */
  314. val |= LPI2C_MCFGR1_IGNACK(0x0); /* ignore nack */
  315. writel(val, &regs->mcfgr1);
  316. ret = bus_i2c_set_bus_speed(bus, speed);
  317. /* enable lpi2c in master mode */
  318. val = readl(&regs->mcr) & ~LPI2C_MCR_MEN_MASK;
  319. writel(val | LPI2C_MCR_MEN(1), &regs->mcr);
  320. debug("i2c : controller bus %d, speed %d:\n", dev_seq(bus), speed);
  321. return ret;
  322. }
  323. static int imx_lpi2c_probe_chip(struct udevice *bus, u32 chip,
  324. u32 chip_flags)
  325. {
  326. lpi2c_status_t result;
  327. result = bus_i2c_start(bus, chip, 0);
  328. if (result) {
  329. bus_i2c_stop(bus);
  330. bus_i2c_init(bus, I2C_SPEED_STANDARD_RATE);
  331. return result;
  332. }
  333. result = bus_i2c_stop(bus);
  334. if (result)
  335. bus_i2c_init(bus, I2C_SPEED_STANDARD_RATE);
  336. return result;
  337. }
  338. static int imx_lpi2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
  339. {
  340. int ret = 0, ret_stop;
  341. for (; nmsgs > 0; nmsgs--, msg++) {
  342. debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
  343. if (msg->flags & I2C_M_RD)
  344. ret = bus_i2c_read(bus, msg->addr, msg->buf, msg->len);
  345. else {
  346. ret = bus_i2c_write(bus, msg->addr, msg->buf,
  347. msg->len);
  348. if (ret)
  349. break;
  350. }
  351. }
  352. if (ret)
  353. debug("i2c_write: error sending\n");
  354. ret_stop = bus_i2c_stop(bus);
  355. if (ret_stop)
  356. debug("i2c_xfer: stop bus error\n");
  357. ret |= ret_stop;
  358. return ret;
  359. }
  360. static int imx_lpi2c_set_bus_speed(struct udevice *bus, unsigned int speed)
  361. {
  362. return bus_i2c_set_bus_speed(bus, speed);
  363. }
  364. __weak int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
  365. {
  366. return 0;
  367. }
  368. static int imx_lpi2c_probe(struct udevice *bus)
  369. {
  370. struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus);
  371. fdt_addr_t addr;
  372. int ret;
  373. i2c_bus->driver_data = dev_get_driver_data(bus);
  374. addr = dev_read_addr(bus);
  375. if (addr == FDT_ADDR_T_NONE)
  376. return -EINVAL;
  377. i2c_bus->base = addr;
  378. i2c_bus->index = dev_seq(bus);
  379. i2c_bus->bus = bus;
  380. /* power up i2c resource */
  381. ret = init_i2c_power(dev_seq(bus));
  382. if (ret) {
  383. debug("init_i2c_power err = %d\n", ret);
  384. return ret;
  385. }
  386. if (IS_ENABLED(CONFIG_CLK)) {
  387. ret = clk_get_by_name(bus, "per", &i2c_bus->per_clk);
  388. if (ret) {
  389. dev_err(bus, "Failed to get per clk\n");
  390. return ret;
  391. }
  392. ret = clk_enable(&i2c_bus->per_clk);
  393. if (ret) {
  394. dev_err(bus, "Failed to enable per clk\n");
  395. return ret;
  396. }
  397. ret = clk_get_by_name(bus, "ipg", &i2c_bus->ipg_clk);
  398. if (ret) {
  399. dev_err(bus, "Failed to get ipg clk\n");
  400. return ret;
  401. }
  402. ret = clk_enable(&i2c_bus->ipg_clk);
  403. if (ret) {
  404. dev_err(bus, "Failed to enable ipg clk\n");
  405. return ret;
  406. }
  407. } else {
  408. /* To i.MX7ULP, only i2c4-7 can be handled by A7 core */
  409. ret = enable_i2c_clk(1, dev_seq(bus));
  410. if (ret < 0)
  411. return ret;
  412. }
  413. ret = bus_i2c_init(bus, I2C_SPEED_STANDARD_RATE);
  414. if (ret < 0)
  415. return ret;
  416. debug("i2c : controller bus %d at 0x%lx , speed %d: ",
  417. dev_seq(bus), i2c_bus->base,
  418. i2c_bus->speed);
  419. return 0;
  420. }
  421. static const struct dm_i2c_ops imx_lpi2c_ops = {
  422. .xfer = imx_lpi2c_xfer,
  423. .probe_chip = imx_lpi2c_probe_chip,
  424. .set_bus_speed = imx_lpi2c_set_bus_speed,
  425. };
  426. static const struct udevice_id imx_lpi2c_ids[] = {
  427. { .compatible = "fsl,imx7ulp-lpi2c", },
  428. { .compatible = "fsl,imx8qm-lpi2c", },
  429. {}
  430. };
  431. U_BOOT_DRIVER(imx_lpi2c) = {
  432. .name = "imx_lpi2c",
  433. .id = UCLASS_I2C,
  434. .of_match = imx_lpi2c_ids,
  435. .probe = imx_lpi2c_probe,
  436. .priv_auto = sizeof(struct imx_lpi2c_bus),
  437. .ops = &imx_lpi2c_ops,
  438. };