i2c-uniphier.c 5.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014 Panasonic Corporation
  4. * Copyright (C) 2015-2016 Socionext Inc.
  5. * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  6. */
  7. #include <dm/device_compat.h>
  8. #include <linux/delay.h>
  9. #include <linux/errno.h>
  10. #include <linux/io.h>
  11. #include <linux/sizes.h>
  12. #include <linux/types.h>
  13. #include <dm.h>
  14. #include <fdtdec.h>
  15. #include <i2c.h>
  16. struct uniphier_i2c_regs {
  17. u32 dtrm; /* data transmission */
  18. #define I2C_DTRM_STA (1 << 10)
  19. #define I2C_DTRM_STO (1 << 9)
  20. #define I2C_DTRM_NACK (1 << 8)
  21. #define I2C_DTRM_RD (1 << 0)
  22. u32 drec; /* data reception */
  23. #define I2C_DREC_STS (1 << 12)
  24. #define I2C_DREC_LRB (1 << 11)
  25. #define I2C_DREC_LAB (1 << 9)
  26. u32 myad; /* slave address */
  27. u32 clk; /* clock frequency control */
  28. u32 brst; /* bus reset */
  29. #define I2C_BRST_FOEN (1 << 1)
  30. #define I2C_BRST_BRST (1 << 0)
  31. u32 hold; /* hold time control */
  32. u32 bsts; /* bus status monitor */
  33. u32 noise; /* noise filter control */
  34. u32 setup; /* setup time control */
  35. };
  36. #define IOBUS_FREQ 100000000
  37. struct uniphier_i2c_priv {
  38. struct udevice *dev;
  39. struct uniphier_i2c_regs __iomem *regs; /* register base */
  40. unsigned long input_clk; /* master clock (Hz) */
  41. unsigned long wait_us; /* wait for every byte transfer (us) */
  42. };
  43. static int uniphier_i2c_probe(struct udevice *dev)
  44. {
  45. fdt_addr_t addr;
  46. struct uniphier_i2c_priv *priv = dev_get_priv(dev);
  47. addr = dev_read_addr(dev);
  48. if (addr == FDT_ADDR_T_NONE)
  49. return -EINVAL;
  50. priv->regs = devm_ioremap(dev, addr, SZ_64);
  51. if (!priv->regs)
  52. return -ENOMEM;
  53. priv->input_clk = IOBUS_FREQ;
  54. priv->dev = dev;
  55. /* deassert reset */
  56. writel(0x3, &priv->regs->brst);
  57. return 0;
  58. }
  59. static int send_and_recv_byte(struct uniphier_i2c_priv *priv, u32 dtrm)
  60. {
  61. writel(dtrm, &priv->regs->dtrm);
  62. /*
  63. * This controller only provides interruption to inform the completion
  64. * of each byte transfer. (No status register to poll it.)
  65. * Unfortunately, U-Boot does not have a good support of interrupt.
  66. * Wait for a while.
  67. */
  68. udelay(priv->wait_us);
  69. return readl(&priv->regs->drec);
  70. }
  71. static int send_byte(struct uniphier_i2c_priv *priv, u32 dtrm, bool *stop)
  72. {
  73. int ret = 0;
  74. u32 drec;
  75. drec = send_and_recv_byte(priv, dtrm);
  76. if (drec & I2C_DREC_LAB) {
  77. dev_dbg(priv->dev, "uniphier_i2c: bus arbitration failed\n");
  78. *stop = false;
  79. ret = -EREMOTEIO;
  80. }
  81. if (drec & I2C_DREC_LRB) {
  82. dev_dbg(priv->dev, "uniphier_i2c: slave did not return ACK\n");
  83. ret = -EREMOTEIO;
  84. }
  85. return ret;
  86. }
  87. static int uniphier_i2c_transmit(struct uniphier_i2c_priv *priv, uint addr,
  88. uint len, const u8 *buf, bool *stop)
  89. {
  90. int ret;
  91. dev_dbg(priv->dev, "%s: addr = %x, len = %d\n", __func__, addr, len);
  92. ret = send_byte(priv, I2C_DTRM_STA | I2C_DTRM_NACK | addr << 1, stop);
  93. if (ret < 0)
  94. goto fail;
  95. while (len--) {
  96. ret = send_byte(priv, I2C_DTRM_NACK | *buf++, stop);
  97. if (ret < 0)
  98. goto fail;
  99. }
  100. fail:
  101. if (*stop)
  102. writel(I2C_DTRM_STO | I2C_DTRM_NACK, &priv->regs->dtrm);
  103. return ret;
  104. }
  105. static int uniphier_i2c_receive(struct uniphier_i2c_priv *priv, uint addr,
  106. uint len, u8 *buf, bool *stop)
  107. {
  108. int ret;
  109. dev_dbg(priv->dev, "%s: addr = %x, len = %d\n", __func__, addr, len);
  110. ret = send_byte(priv, I2C_DTRM_STA | I2C_DTRM_NACK |
  111. I2C_DTRM_RD | addr << 1, stop);
  112. if (ret < 0)
  113. goto fail;
  114. while (len--)
  115. *buf++ = send_and_recv_byte(priv, len ? 0 : I2C_DTRM_NACK);
  116. fail:
  117. if (*stop)
  118. writel(I2C_DTRM_STO | I2C_DTRM_NACK, &priv->regs->dtrm);
  119. return ret;
  120. }
  121. static int uniphier_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
  122. int nmsgs)
  123. {
  124. int ret = 0;
  125. struct uniphier_i2c_priv *priv = dev_get_priv(bus);
  126. bool stop;
  127. for (; nmsgs > 0; nmsgs--, msg++) {
  128. /* If next message is read, skip the stop condition */
  129. stop = nmsgs > 1 && msg[1].flags & I2C_M_RD ? false : true;
  130. if (msg->flags & I2C_M_RD)
  131. ret = uniphier_i2c_receive(priv, msg->addr, msg->len,
  132. msg->buf, &stop);
  133. else
  134. ret = uniphier_i2c_transmit(priv, msg->addr, msg->len,
  135. msg->buf, &stop);
  136. if (ret < 0)
  137. break;
  138. }
  139. return ret;
  140. }
  141. static int uniphier_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
  142. {
  143. struct uniphier_i2c_priv *priv = dev_get_priv(bus);
  144. /* max supported frequency is 400 kHz */
  145. if (speed > I2C_SPEED_FAST_RATE)
  146. return -EINVAL;
  147. /* bus reset: make sure the bus is idle when change the frequency */
  148. writel(0x1, &priv->regs->brst);
  149. writel((priv->input_clk / speed / 2 << 16) | (priv->input_clk / speed),
  150. &priv->regs->clk);
  151. writel(0x3, &priv->regs->brst);
  152. /*
  153. * Theoretically, each byte can be transferred in
  154. * 1000000 * 9 / speed usec. For safety, wait more than double.
  155. */
  156. priv->wait_us = 20000000 / speed;
  157. return 0;
  158. }
  159. static const struct dm_i2c_ops uniphier_i2c_ops = {
  160. .xfer = uniphier_i2c_xfer,
  161. .set_bus_speed = uniphier_i2c_set_bus_speed,
  162. };
  163. static const struct udevice_id uniphier_i2c_of_match[] = {
  164. { .compatible = "socionext,uniphier-i2c" },
  165. { /* sentinel */ }
  166. };
  167. U_BOOT_DRIVER(uniphier_i2c) = {
  168. .name = "uniphier-i2c",
  169. .id = UCLASS_I2C,
  170. .of_match = uniphier_i2c_of_match,
  171. .probe = uniphier_i2c_probe,
  172. .priv_auto = sizeof(struct uniphier_i2c_priv),
  173. .ops = &uniphier_i2c_ops,
  174. };