i2c-uniphier-f.c 8.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014 Panasonic Corporation
  4. * Copyright (C) 2015-2016 Socionext Inc.
  5. * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  6. */
  7. #include <dm/device_compat.h>
  8. #include <linux/errno.h>
  9. #include <linux/io.h>
  10. #include <linux/iopoll.h>
  11. #include <linux/sizes.h>
  12. #include <linux/types.h>
  13. #include <dm.h>
  14. #include <i2c.h>
  15. #include <fdtdec.h>
  16. struct uniphier_fi2c_regs {
  17. u32 cr; /* control register */
  18. #define I2C_CR_MST (1 << 3) /* master mode */
  19. #define I2C_CR_STA (1 << 2) /* start condition */
  20. #define I2C_CR_STO (1 << 1) /* stop condition */
  21. #define I2C_CR_NACK (1 << 0) /* not ACK */
  22. u32 dttx; /* send FIFO (write-only) */
  23. #define dtrx dttx /* receive FIFO (read-only) */
  24. #define I2C_DTTX_CMD (1 << 8) /* send command (slave addr) */
  25. #define I2C_DTTX_RD (1 << 0) /* read */
  26. u32 __reserved; /* no register at offset 0x08 */
  27. u32 slad; /* slave address */
  28. u32 cyc; /* clock cycle control */
  29. u32 lctl; /* clock low period control */
  30. u32 ssut; /* restart/stop setup time control */
  31. u32 dsut; /* data setup time control */
  32. u32 intr; /* interrupt status */
  33. u32 ie; /* interrupt enable */
  34. u32 ic; /* interrupt clear */
  35. #define I2C_INT_TE (1 << 9) /* TX FIFO empty */
  36. #define I2C_INT_RB (1 << 4) /* received specified bytes */
  37. #define I2C_INT_NA (1 << 2) /* no answer */
  38. #define I2C_INT_AL (1 << 1) /* arbitration lost */
  39. u32 sr; /* status register */
  40. #define I2C_SR_DB (1 << 12) /* device busy */
  41. #define I2C_SR_BB (1 << 8) /* bus busy */
  42. #define I2C_SR_RFF (1 << 3) /* Rx FIFO full */
  43. #define I2C_SR_RNE (1 << 2) /* Rx FIFO not empty */
  44. #define I2C_SR_TNF (1 << 1) /* Tx FIFO not full */
  45. #define I2C_SR_TFE (1 << 0) /* Tx FIFO empty */
  46. u32 __reserved2; /* no register at offset 0x30 */
  47. u32 rst; /* reset control */
  48. #define I2C_RST_TBRST (1 << 2) /* clear Tx FIFO */
  49. #define I2C_RST_RBRST (1 << 1) /* clear Rx FIFO */
  50. #define I2C_RST_RST (1 << 0) /* forcible bus reset */
  51. u32 bm; /* bus monitor */
  52. u32 noise; /* noise filter control */
  53. u32 tbc; /* Tx byte count setting */
  54. u32 rbc; /* Rx byte count setting */
  55. u32 tbcm; /* Tx byte count monitor */
  56. u32 rbcm; /* Rx byte count monitor */
  57. u32 brst; /* bus reset */
  58. #define I2C_BRST_FOEN (1 << 1) /* normal operation */
  59. #define I2C_BRST_RSCLO (1 << 0) /* release SCL low fixing */
  60. };
  61. #define FIOCLK 50000000
  62. struct uniphier_fi2c_priv {
  63. struct udevice *dev;
  64. struct uniphier_fi2c_regs __iomem *regs; /* register base */
  65. unsigned long fioclk; /* internal operation clock */
  66. unsigned long timeout; /* time out (us) */
  67. };
  68. static void uniphier_fi2c_reset(struct uniphier_fi2c_priv *priv)
  69. {
  70. writel(I2C_RST_RST, &priv->regs->rst);
  71. }
  72. static int uniphier_fi2c_check_bus_busy(struct uniphier_fi2c_priv *priv)
  73. {
  74. u32 val;
  75. int ret;
  76. ret = readl_poll_timeout(&priv->regs->sr, val, !(val & I2C_SR_DB), 100);
  77. if (ret < 0) {
  78. dev_dbg(priv->dev, "error: device busy too long. reset...\n");
  79. uniphier_fi2c_reset(priv);
  80. }
  81. return ret;
  82. }
  83. static int uniphier_fi2c_probe(struct udevice *dev)
  84. {
  85. fdt_addr_t addr;
  86. struct uniphier_fi2c_priv *priv = dev_get_priv(dev);
  87. addr = dev_read_addr(dev);
  88. if (addr == FDT_ADDR_T_NONE)
  89. return -EINVAL;
  90. priv->regs = devm_ioremap(dev, addr, SZ_128);
  91. if (!priv->regs)
  92. return -ENOMEM;
  93. priv->fioclk = FIOCLK;
  94. priv->dev = dev;
  95. /* bus forcible reset */
  96. uniphier_fi2c_reset(priv);
  97. writel(I2C_BRST_FOEN | I2C_BRST_RSCLO, &priv->regs->brst);
  98. return 0;
  99. }
  100. static int wait_for_irq(struct uniphier_fi2c_priv *priv, u32 flags,
  101. bool *stop)
  102. {
  103. u32 irq;
  104. int ret;
  105. ret = readl_poll_timeout(&priv->regs->intr, irq, irq & flags,
  106. priv->timeout);
  107. if (ret < 0) {
  108. dev_dbg(priv->dev, "error: time out\n");
  109. return ret;
  110. }
  111. if (irq & I2C_INT_AL) {
  112. dev_dbg(priv->dev, "error: arbitration lost\n");
  113. *stop = false;
  114. return ret;
  115. }
  116. if (irq & I2C_INT_NA) {
  117. dev_dbg(priv->dev, "error: no answer\n");
  118. return ret;
  119. }
  120. return 0;
  121. }
  122. static int issue_stop(struct uniphier_fi2c_priv *priv, int old_ret)
  123. {
  124. int ret;
  125. dev_dbg(priv->dev, "stop condition\n");
  126. writel(I2C_CR_MST | I2C_CR_STO, &priv->regs->cr);
  127. ret = uniphier_fi2c_check_bus_busy(priv);
  128. if (ret < 0)
  129. dev_dbg(priv->dev, "error: device busy after operation\n");
  130. return old_ret ? old_ret : ret;
  131. }
  132. static int uniphier_fi2c_transmit(struct uniphier_fi2c_priv *priv, uint addr,
  133. uint len, const u8 *buf, bool *stop)
  134. {
  135. int ret;
  136. const u32 irq_flags = I2C_INT_TE | I2C_INT_NA | I2C_INT_AL;
  137. struct uniphier_fi2c_regs __iomem *regs = priv->regs;
  138. dev_dbg(priv->dev, "%s: addr = %x, len = %d\n", __func__, addr, len);
  139. writel(I2C_DTTX_CMD | addr << 1, &regs->dttx);
  140. writel(irq_flags, &regs->ie);
  141. writel(irq_flags, &regs->ic);
  142. dev_dbg(priv->dev, "start condition\n");
  143. writel(I2C_CR_MST | I2C_CR_STA, &regs->cr);
  144. ret = wait_for_irq(priv, irq_flags, stop);
  145. if (ret < 0)
  146. goto error;
  147. while (len--) {
  148. dev_dbg(priv->dev, "sending %x\n", *buf);
  149. writel(*buf++, &regs->dttx);
  150. writel(irq_flags, &regs->ic);
  151. ret = wait_for_irq(priv, irq_flags, stop);
  152. if (ret < 0)
  153. goto error;
  154. }
  155. error:
  156. writel(irq_flags, &regs->ic);
  157. if (*stop)
  158. ret = issue_stop(priv, ret);
  159. return ret;
  160. }
  161. static int uniphier_fi2c_receive(struct uniphier_fi2c_priv *priv, uint addr,
  162. uint len, u8 *buf, bool *stop)
  163. {
  164. int ret = 0;
  165. const u32 irq_flags = I2C_INT_RB | I2C_INT_NA | I2C_INT_AL;
  166. struct uniphier_fi2c_regs __iomem *regs = priv->regs;
  167. dev_dbg(priv->dev, "%s: addr = %x, len = %d\n", __func__, addr, len);
  168. /*
  169. * In case 'len == 0', only the slave address should be sent
  170. * for probing, which is covered by the transmit function.
  171. */
  172. if (len == 0)
  173. return uniphier_fi2c_transmit(priv, addr, len, buf, stop);
  174. writel(I2C_DTTX_CMD | I2C_DTTX_RD | addr << 1, &regs->dttx);
  175. writel(0, &regs->rbc);
  176. writel(irq_flags, &regs->ie);
  177. writel(irq_flags, &regs->ic);
  178. dev_dbg(priv->dev, "start condition\n");
  179. writel(I2C_CR_MST | I2C_CR_STA | (len == 1 ? I2C_CR_NACK : 0),
  180. &regs->cr);
  181. while (len--) {
  182. ret = wait_for_irq(priv, irq_flags, stop);
  183. if (ret < 0)
  184. goto error;
  185. *buf++ = readl(&regs->dtrx);
  186. dev_dbg(priv->dev, "received %x\n", *(buf - 1));
  187. if (len == 1)
  188. writel(I2C_CR_MST | I2C_CR_NACK, &regs->cr);
  189. writel(irq_flags, &regs->ic);
  190. }
  191. error:
  192. writel(irq_flags, &regs->ic);
  193. if (*stop)
  194. ret = issue_stop(priv, ret);
  195. return ret;
  196. }
  197. static int uniphier_fi2c_xfer(struct udevice *bus, struct i2c_msg *msg,
  198. int nmsgs)
  199. {
  200. int ret;
  201. struct uniphier_fi2c_priv *priv = dev_get_priv(bus);
  202. bool stop;
  203. ret = uniphier_fi2c_check_bus_busy(priv);
  204. if (ret < 0)
  205. return ret;
  206. for (; nmsgs > 0; nmsgs--, msg++) {
  207. /* If next message is read, skip the stop condition */
  208. stop = nmsgs > 1 && msg[1].flags & I2C_M_RD ? false : true;
  209. if (msg->flags & I2C_M_RD)
  210. ret = uniphier_fi2c_receive(priv, msg->addr, msg->len,
  211. msg->buf, &stop);
  212. else
  213. ret = uniphier_fi2c_transmit(priv, msg->addr, msg->len,
  214. msg->buf, &stop);
  215. if (ret < 0)
  216. break;
  217. }
  218. return ret;
  219. }
  220. static int uniphier_fi2c_set_bus_speed(struct udevice *bus, unsigned int speed)
  221. {
  222. int ret;
  223. unsigned int clk_count;
  224. struct uniphier_fi2c_priv *priv = dev_get_priv(bus);
  225. struct uniphier_fi2c_regs __iomem *regs = priv->regs;
  226. /* max supported frequency is 400 kHz */
  227. if (speed > I2C_SPEED_FAST_RATE)
  228. return -EINVAL;
  229. ret = uniphier_fi2c_check_bus_busy(priv);
  230. if (ret < 0)
  231. return ret;
  232. /* make sure the bus is idle when changing the frequency */
  233. writel(I2C_BRST_RSCLO, &regs->brst);
  234. clk_count = priv->fioclk / speed;
  235. writel(clk_count, &regs->cyc);
  236. writel(clk_count / 2, &regs->lctl);
  237. writel(clk_count / 2, &regs->ssut);
  238. writel(clk_count / 16, &regs->dsut);
  239. writel(I2C_BRST_FOEN | I2C_BRST_RSCLO, &regs->brst);
  240. /*
  241. * Theoretically, each byte can be transferred in
  242. * 1000000 * 9 / speed usec.
  243. * This time out value is long enough.
  244. */
  245. priv->timeout = 100000000L / speed;
  246. return 0;
  247. }
  248. static const struct dm_i2c_ops uniphier_fi2c_ops = {
  249. .xfer = uniphier_fi2c_xfer,
  250. .set_bus_speed = uniphier_fi2c_set_bus_speed,
  251. };
  252. static const struct udevice_id uniphier_fi2c_of_match[] = {
  253. { .compatible = "socionext,uniphier-fi2c" },
  254. { /* sentinel */ }
  255. };
  256. U_BOOT_DRIVER(uniphier_fi2c) = {
  257. .name = "uniphier-fi2c",
  258. .id = UCLASS_I2C,
  259. .of_match = uniphier_fi2c_of_match,
  260. .probe = uniphier_fi2c_probe,
  261. .priv_auto = sizeof(struct uniphier_fi2c_priv),
  262. .ops = &uniphier_fi2c_ops,
  263. };