i2c-cdns.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015 Moritz Fischer <moritz.fischer@ettus.com>
  4. * IP from Cadence (ID T-CS-PE-0007-100, Version R1p10f2)
  5. *
  6. * This file is based on: drivers/i2c/zynq_i2c.c,
  7. * with added driver-model support and code cleanup.
  8. */
  9. #include <common.h>
  10. #include <dm.h>
  11. #include <log.h>
  12. #include <linux/bitops.h>
  13. #include <linux/delay.h>
  14. #include <linux/types.h>
  15. #include <linux/io.h>
  16. #include <linux/errno.h>
  17. #include <dm/device_compat.h>
  18. #include <dm/root.h>
  19. #include <i2c.h>
  20. #include <fdtdec.h>
  21. #include <mapmem.h>
  22. #include <wait_bit.h>
  23. #include <clk.h>
  24. /* i2c register set */
  25. struct cdns_i2c_regs {
  26. u32 control;
  27. u32 status;
  28. u32 address;
  29. u32 data;
  30. u32 interrupt_status;
  31. u32 transfer_size;
  32. u32 slave_mon_pause;
  33. u32 time_out;
  34. u32 interrupt_mask;
  35. u32 interrupt_enable;
  36. u32 interrupt_disable;
  37. };
  38. /* Control register fields */
  39. #define CDNS_I2C_CONTROL_RW 0x00000001
  40. #define CDNS_I2C_CONTROL_MS 0x00000002
  41. #define CDNS_I2C_CONTROL_NEA 0x00000004
  42. #define CDNS_I2C_CONTROL_ACKEN 0x00000008
  43. #define CDNS_I2C_CONTROL_HOLD 0x00000010
  44. #define CDNS_I2C_CONTROL_SLVMON 0x00000020
  45. #define CDNS_I2C_CONTROL_CLR_FIFO 0x00000040
  46. #define CDNS_I2C_CONTROL_DIV_B_SHIFT 8
  47. #define CDNS_I2C_CONTROL_DIV_B_MASK 0x00003F00
  48. #define CDNS_I2C_CONTROL_DIV_A_SHIFT 14
  49. #define CDNS_I2C_CONTROL_DIV_A_MASK 0x0000C000
  50. /* Status register values */
  51. #define CDNS_I2C_STATUS_RXDV 0x00000020
  52. #define CDNS_I2C_STATUS_TXDV 0x00000040
  53. #define CDNS_I2C_STATUS_RXOVF 0x00000080
  54. #define CDNS_I2C_STATUS_BA 0x00000100
  55. /* Interrupt register fields */
  56. #define CDNS_I2C_INTERRUPT_COMP 0x00000001
  57. #define CDNS_I2C_INTERRUPT_DATA 0x00000002
  58. #define CDNS_I2C_INTERRUPT_NACK 0x00000004
  59. #define CDNS_I2C_INTERRUPT_TO 0x00000008
  60. #define CDNS_I2C_INTERRUPT_SLVRDY 0x00000010
  61. #define CDNS_I2C_INTERRUPT_RXOVF 0x00000020
  62. #define CDNS_I2C_INTERRUPT_TXOVF 0x00000040
  63. #define CDNS_I2C_INTERRUPT_RXUNF 0x00000080
  64. #define CDNS_I2C_INTERRUPT_ARBLOST 0x00000200
  65. #define CDNS_I2C_INTERRUPTS_MASK (CDNS_I2C_INTERRUPT_COMP | \
  66. CDNS_I2C_INTERRUPT_DATA | \
  67. CDNS_I2C_INTERRUPT_NACK | \
  68. CDNS_I2C_INTERRUPT_TO | \
  69. CDNS_I2C_INTERRUPT_SLVRDY | \
  70. CDNS_I2C_INTERRUPT_RXOVF | \
  71. CDNS_I2C_INTERRUPT_TXOVF | \
  72. CDNS_I2C_INTERRUPT_RXUNF | \
  73. CDNS_I2C_INTERRUPT_ARBLOST)
  74. #define CDNS_I2C_FIFO_DEPTH 16
  75. #define CDNS_I2C_TRANSFER_SIZE_MAX 255 /* Controller transfer limit */
  76. #define CDNS_I2C_TRANSFER_SIZE (CDNS_I2C_TRANSFER_SIZE_MAX - 3)
  77. #define CDNS_I2C_BROKEN_HOLD_BIT BIT(0)
  78. #define CDNS_I2C_ARB_LOST_MAX_RETRIES 10
  79. #ifdef DEBUG
  80. static void cdns_i2c_debug_status(struct cdns_i2c_regs *cdns_i2c)
  81. {
  82. int int_status;
  83. int status;
  84. int_status = readl(&cdns_i2c->interrupt_status);
  85. status = readl(&cdns_i2c->status);
  86. if (int_status || status) {
  87. debug("Status: ");
  88. if (int_status & CDNS_I2C_INTERRUPT_COMP)
  89. debug("COMP ");
  90. if (int_status & CDNS_I2C_INTERRUPT_DATA)
  91. debug("DATA ");
  92. if (int_status & CDNS_I2C_INTERRUPT_NACK)
  93. debug("NACK ");
  94. if (int_status & CDNS_I2C_INTERRUPT_TO)
  95. debug("TO ");
  96. if (int_status & CDNS_I2C_INTERRUPT_SLVRDY)
  97. debug("SLVRDY ");
  98. if (int_status & CDNS_I2C_INTERRUPT_RXOVF)
  99. debug("RXOVF ");
  100. if (int_status & CDNS_I2C_INTERRUPT_TXOVF)
  101. debug("TXOVF ");
  102. if (int_status & CDNS_I2C_INTERRUPT_RXUNF)
  103. debug("RXUNF ");
  104. if (int_status & CDNS_I2C_INTERRUPT_ARBLOST)
  105. debug("ARBLOST ");
  106. if (status & CDNS_I2C_STATUS_RXDV)
  107. debug("RXDV ");
  108. if (status & CDNS_I2C_STATUS_TXDV)
  109. debug("TXDV ");
  110. if (status & CDNS_I2C_STATUS_RXOVF)
  111. debug("RXOVF ");
  112. if (status & CDNS_I2C_STATUS_BA)
  113. debug("BA ");
  114. debug("TS%d ", readl(&cdns_i2c->transfer_size));
  115. debug("\n");
  116. }
  117. }
  118. #endif
  119. struct i2c_cdns_bus {
  120. int id;
  121. unsigned int input_freq;
  122. struct cdns_i2c_regs __iomem *regs; /* register base */
  123. int hold_flag;
  124. u32 quirks;
  125. };
  126. struct cdns_i2c_platform_data {
  127. u32 quirks;
  128. };
  129. /* Wait for an interrupt */
  130. static u32 cdns_i2c_wait(struct cdns_i2c_regs *cdns_i2c, u32 mask)
  131. {
  132. int timeout, int_status;
  133. for (timeout = 0; timeout < 100; timeout++) {
  134. int_status = readl(&cdns_i2c->interrupt_status);
  135. if (int_status & mask)
  136. break;
  137. udelay(100);
  138. }
  139. /* Clear interrupt status flags */
  140. writel(int_status & mask, &cdns_i2c->interrupt_status);
  141. return int_status & mask;
  142. }
  143. #define CDNS_I2C_DIVA_MAX 4
  144. #define CDNS_I2C_DIVB_MAX 64
  145. static int cdns_i2c_calc_divs(unsigned long *f, unsigned long input_clk,
  146. unsigned int *a, unsigned int *b)
  147. {
  148. unsigned long fscl = *f, best_fscl = *f, actual_fscl, temp;
  149. unsigned int div_a, div_b, calc_div_a = 0, calc_div_b = 0;
  150. unsigned int last_error, current_error;
  151. /* calculate (divisor_a+1) x (divisor_b+1) */
  152. temp = input_clk / (22 * fscl);
  153. /*
  154. * If the calculated value is negative or 0CDNS_I2C_DIVA_MAX,
  155. * the fscl input is out of range. Return error.
  156. */
  157. if (!temp || (temp > (CDNS_I2C_DIVA_MAX * CDNS_I2C_DIVB_MAX)))
  158. return -EINVAL;
  159. last_error = -1;
  160. for (div_a = 0; div_a < CDNS_I2C_DIVA_MAX; div_a++) {
  161. div_b = DIV_ROUND_UP(input_clk, 22 * fscl * (div_a + 1));
  162. if ((div_b < 1) || (div_b > CDNS_I2C_DIVB_MAX))
  163. continue;
  164. div_b--;
  165. actual_fscl = input_clk / (22 * (div_a + 1) * (div_b + 1));
  166. if (actual_fscl > fscl)
  167. continue;
  168. current_error = ((actual_fscl > fscl) ? (actual_fscl - fscl) :
  169. (fscl - actual_fscl));
  170. if (last_error > current_error) {
  171. calc_div_a = div_a;
  172. calc_div_b = div_b;
  173. best_fscl = actual_fscl;
  174. last_error = current_error;
  175. }
  176. }
  177. *a = calc_div_a;
  178. *b = calc_div_b;
  179. *f = best_fscl;
  180. return 0;
  181. }
  182. static int cdns_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
  183. {
  184. struct i2c_cdns_bus *bus = dev_get_priv(dev);
  185. u32 div_a = 0, div_b = 0;
  186. unsigned long speed_p = speed;
  187. int ret = 0;
  188. if (speed > I2C_SPEED_FAST_RATE) {
  189. debug("%s, failed to set clock speed to %u\n", __func__,
  190. speed);
  191. return -EINVAL;
  192. }
  193. ret = cdns_i2c_calc_divs(&speed_p, bus->input_freq, &div_a, &div_b);
  194. if (ret)
  195. return ret;
  196. debug("%s: div_a: %d, div_b: %d, input freq: %d, speed: %d/%ld\n",
  197. __func__, div_a, div_b, bus->input_freq, speed, speed_p);
  198. writel((div_b << CDNS_I2C_CONTROL_DIV_B_SHIFT) |
  199. (div_a << CDNS_I2C_CONTROL_DIV_A_SHIFT), &bus->regs->control);
  200. /* Enable master mode, ack, and 7-bit addressing */
  201. setbits_le32(&bus->regs->control, CDNS_I2C_CONTROL_MS |
  202. CDNS_I2C_CONTROL_ACKEN | CDNS_I2C_CONTROL_NEA);
  203. return 0;
  204. }
  205. static inline u32 is_arbitration_lost(struct cdns_i2c_regs *regs)
  206. {
  207. return (readl(&regs->interrupt_status) & CDNS_I2C_INTERRUPT_ARBLOST);
  208. }
  209. static int cdns_i2c_write_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
  210. u32 len)
  211. {
  212. u8 *cur_data = data;
  213. struct cdns_i2c_regs *regs = i2c_bus->regs;
  214. u32 ret;
  215. /* Set the controller in Master transmit mode and clear FIFO */
  216. setbits_le32(&regs->control, CDNS_I2C_CONTROL_CLR_FIFO);
  217. clrbits_le32(&regs->control, CDNS_I2C_CONTROL_RW);
  218. /* Check message size against FIFO depth, and set hold bus bit
  219. * if it is greater than FIFO depth
  220. */
  221. if (len > CDNS_I2C_FIFO_DEPTH)
  222. setbits_le32(&regs->control, CDNS_I2C_CONTROL_HOLD);
  223. /* Clear the interrupts in status register */
  224. writel(CDNS_I2C_INTERRUPTS_MASK, &regs->interrupt_status);
  225. writel(addr, &regs->address);
  226. while (len-- && !is_arbitration_lost(regs)) {
  227. writel(*(cur_data++), &regs->data);
  228. if (len && readl(&regs->transfer_size) == CDNS_I2C_FIFO_DEPTH) {
  229. ret = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
  230. CDNS_I2C_INTERRUPT_ARBLOST);
  231. if (ret & CDNS_I2C_INTERRUPT_ARBLOST)
  232. return -EAGAIN;
  233. if (ret & CDNS_I2C_INTERRUPT_COMP)
  234. continue;
  235. /* Release the bus */
  236. clrbits_le32(&regs->control,
  237. CDNS_I2C_CONTROL_HOLD);
  238. return -ETIMEDOUT;
  239. }
  240. }
  241. if (len && is_arbitration_lost(regs))
  242. return -EAGAIN;
  243. /* All done... release the bus */
  244. if (!i2c_bus->hold_flag)
  245. clrbits_le32(&regs->control, CDNS_I2C_CONTROL_HOLD);
  246. /* Wait for the address and data to be sent */
  247. ret = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
  248. CDNS_I2C_INTERRUPT_ARBLOST);
  249. if (!(ret & (CDNS_I2C_INTERRUPT_ARBLOST |
  250. CDNS_I2C_INTERRUPT_COMP)))
  251. return -ETIMEDOUT;
  252. if (ret & CDNS_I2C_INTERRUPT_ARBLOST)
  253. return -EAGAIN;
  254. return 0;
  255. }
  256. static inline bool cdns_is_hold_quirk(int hold_quirk, int curr_recv_count)
  257. {
  258. return hold_quirk && (curr_recv_count == CDNS_I2C_FIFO_DEPTH + 1);
  259. }
  260. static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
  261. u32 recv_count)
  262. {
  263. u8 *cur_data = data;
  264. struct cdns_i2c_regs *regs = i2c_bus->regs;
  265. u32 curr_recv_count;
  266. int updatetx, hold_quirk;
  267. u32 ret;
  268. curr_recv_count = recv_count;
  269. /* Check for the message size against the FIFO depth */
  270. if (recv_count > CDNS_I2C_FIFO_DEPTH)
  271. setbits_le32(&regs->control, CDNS_I2C_CONTROL_HOLD);
  272. setbits_le32(&regs->control, CDNS_I2C_CONTROL_CLR_FIFO |
  273. CDNS_I2C_CONTROL_RW);
  274. if (recv_count > CDNS_I2C_TRANSFER_SIZE) {
  275. curr_recv_count = CDNS_I2C_TRANSFER_SIZE;
  276. writel(curr_recv_count, &regs->transfer_size);
  277. } else {
  278. writel(recv_count, &regs->transfer_size);
  279. }
  280. /* Start reading data */
  281. writel(addr, &regs->address);
  282. updatetx = recv_count > curr_recv_count;
  283. hold_quirk = (i2c_bus->quirks & CDNS_I2C_BROKEN_HOLD_BIT) && updatetx;
  284. while (recv_count && !is_arbitration_lost(regs)) {
  285. while (readl(&regs->status) & CDNS_I2C_STATUS_RXDV) {
  286. if (recv_count < CDNS_I2C_FIFO_DEPTH &&
  287. !i2c_bus->hold_flag) {
  288. clrbits_le32(&regs->control,
  289. CDNS_I2C_CONTROL_HOLD);
  290. }
  291. *(cur_data)++ = readl(&regs->data);
  292. recv_count--;
  293. curr_recv_count--;
  294. if (cdns_is_hold_quirk(hold_quirk, curr_recv_count))
  295. break;
  296. }
  297. if (cdns_is_hold_quirk(hold_quirk, curr_recv_count)) {
  298. /* wait while fifo is full */
  299. while (readl(&regs->transfer_size) !=
  300. (curr_recv_count - CDNS_I2C_FIFO_DEPTH))
  301. ;
  302. /*
  303. * Check number of bytes to be received against maximum
  304. * transfer size and update register accordingly.
  305. */
  306. if ((recv_count - CDNS_I2C_FIFO_DEPTH) >
  307. CDNS_I2C_TRANSFER_SIZE) {
  308. writel(CDNS_I2C_TRANSFER_SIZE,
  309. &regs->transfer_size);
  310. curr_recv_count = CDNS_I2C_TRANSFER_SIZE +
  311. CDNS_I2C_FIFO_DEPTH;
  312. } else {
  313. writel(recv_count - CDNS_I2C_FIFO_DEPTH,
  314. &regs->transfer_size);
  315. curr_recv_count = recv_count;
  316. }
  317. } else if (recv_count && !hold_quirk && !curr_recv_count) {
  318. writel(addr, &regs->address);
  319. if (recv_count > CDNS_I2C_TRANSFER_SIZE) {
  320. writel(CDNS_I2C_TRANSFER_SIZE,
  321. &regs->transfer_size);
  322. curr_recv_count = CDNS_I2C_TRANSFER_SIZE;
  323. } else {
  324. writel(recv_count, &regs->transfer_size);
  325. curr_recv_count = recv_count;
  326. }
  327. }
  328. }
  329. /* Wait for the address and data to be sent */
  330. ret = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
  331. CDNS_I2C_INTERRUPT_ARBLOST);
  332. if (!(ret & (CDNS_I2C_INTERRUPT_ARBLOST |
  333. CDNS_I2C_INTERRUPT_COMP)))
  334. return -ETIMEDOUT;
  335. if (ret & CDNS_I2C_INTERRUPT_ARBLOST)
  336. return -EAGAIN;
  337. return 0;
  338. }
  339. static int cdns_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
  340. int nmsgs)
  341. {
  342. struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev);
  343. int ret = 0;
  344. int count;
  345. bool hold_quirk;
  346. struct i2c_msg *message = msg;
  347. int num_msgs = nmsgs;
  348. hold_quirk = !!(i2c_bus->quirks & CDNS_I2C_BROKEN_HOLD_BIT);
  349. if (nmsgs > 1) {
  350. /*
  351. * This controller does not give completion interrupt after a
  352. * master receive message if HOLD bit is set (repeated start),
  353. * resulting in SW timeout. Hence, if a receive message is
  354. * followed by any other message, an error is returned
  355. * indicating that this sequence is not supported.
  356. */
  357. for (count = 0; (count < nmsgs - 1) && hold_quirk; count++) {
  358. if (msg[count].flags & I2C_M_RD) {
  359. printf("Can't do repeated start after a receive message\n");
  360. return -EOPNOTSUPP;
  361. }
  362. }
  363. i2c_bus->hold_flag = 1;
  364. setbits_le32(&i2c_bus->regs->control, CDNS_I2C_CONTROL_HOLD);
  365. } else {
  366. i2c_bus->hold_flag = 0;
  367. }
  368. debug("i2c_xfer: %d messages\n", nmsgs);
  369. for (u8 retry = 0; retry < CDNS_I2C_ARB_LOST_MAX_RETRIES &&
  370. nmsgs > 0; nmsgs--, msg++) {
  371. debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
  372. if (msg->flags & I2C_M_RD) {
  373. ret = cdns_i2c_read_data(i2c_bus, msg->addr, msg->buf,
  374. msg->len);
  375. } else {
  376. ret = cdns_i2c_write_data(i2c_bus, msg->addr, msg->buf,
  377. msg->len);
  378. }
  379. if (ret == -EAGAIN) {
  380. msg = message;
  381. nmsgs = num_msgs;
  382. retry++;
  383. printf("%s,arbitration lost, retrying:%d\n", __func__,
  384. retry);
  385. continue;
  386. }
  387. if (ret) {
  388. debug("i2c_write: error sending\n");
  389. return -EREMOTEIO;
  390. }
  391. }
  392. return ret;
  393. }
  394. static int cdns_i2c_of_to_plat(struct udevice *dev)
  395. {
  396. struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev);
  397. struct cdns_i2c_platform_data *pdata =
  398. (struct cdns_i2c_platform_data *)dev_get_driver_data(dev);
  399. struct clk clk;
  400. int ret;
  401. i2c_bus->regs = (struct cdns_i2c_regs *)dev_read_addr(dev);
  402. if (!i2c_bus->regs)
  403. return -ENOMEM;
  404. if (pdata)
  405. i2c_bus->quirks = pdata->quirks;
  406. ret = clk_get_by_index(dev, 0, &clk);
  407. if (ret)
  408. return ret;
  409. i2c_bus->input_freq = clk_get_rate(&clk);
  410. ret = clk_enable(&clk);
  411. if (ret) {
  412. dev_err(dev, "failed to enable clock\n");
  413. return ret;
  414. }
  415. return 0;
  416. }
  417. static const struct dm_i2c_ops cdns_i2c_ops = {
  418. .xfer = cdns_i2c_xfer,
  419. .set_bus_speed = cdns_i2c_set_bus_speed,
  420. };
  421. static const struct cdns_i2c_platform_data r1p10_i2c_def = {
  422. .quirks = CDNS_I2C_BROKEN_HOLD_BIT,
  423. };
  424. static const struct udevice_id cdns_i2c_of_match[] = {
  425. { .compatible = "cdns,i2c-r1p10", .data = (ulong)&r1p10_i2c_def },
  426. { .compatible = "cdns,i2c-r1p14" },
  427. { /* end of table */ }
  428. };
  429. U_BOOT_DRIVER(cdns_i2c) = {
  430. .name = "i2c_cdns",
  431. .id = UCLASS_I2C,
  432. .of_match = cdns_i2c_of_match,
  433. .of_to_plat = cdns_i2c_of_to_plat,
  434. .priv_auto = sizeof(struct i2c_cdns_bus),
  435. .ops = &cdns_i2c_ops,
  436. };