exynos_hs_i2c.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2016, Google Inc
  4. *
  5. * (C) Copyright 2002
  6. * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
  7. */
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <i2c.h>
  11. #include <log.h>
  12. #include <asm/arch/clk.h>
  13. #include <asm/arch/cpu.h>
  14. #include <asm/arch/pinmux.h>
  15. #include <asm/global_data.h>
  16. #include <linux/delay.h>
  17. #include "s3c24x0_i2c.h"
  18. DECLARE_GLOBAL_DATA_PTR;
  19. /* HSI2C-specific register description */
  20. /* I2C_CTL Register bits */
  21. #define HSI2C_FUNC_MODE_I2C (1u << 0)
  22. #define HSI2C_MASTER (1u << 3)
  23. #define HSI2C_RXCHON (1u << 6) /* Write/Send */
  24. #define HSI2C_TXCHON (1u << 7) /* Read/Receive */
  25. #define HSI2C_SW_RST (1u << 31)
  26. /* I2C_FIFO_CTL Register bits */
  27. #define HSI2C_RXFIFO_EN (1u << 0)
  28. #define HSI2C_TXFIFO_EN (1u << 1)
  29. #define HSI2C_TXFIFO_TRIGGER_LEVEL (0x20 << 16)
  30. #define HSI2C_RXFIFO_TRIGGER_LEVEL (0x20 << 4)
  31. /* I2C_TRAILING_CTL Register bits */
  32. #define HSI2C_TRAILING_COUNT (0xff)
  33. /* I2C_INT_EN Register bits */
  34. #define HSI2C_TX_UNDERRUN_EN (1u << 2)
  35. #define HSI2C_TX_OVERRUN_EN (1u << 3)
  36. #define HSI2C_RX_UNDERRUN_EN (1u << 4)
  37. #define HSI2C_RX_OVERRUN_EN (1u << 5)
  38. #define HSI2C_INT_TRAILING_EN (1u << 6)
  39. #define HSI2C_INT_I2C_EN (1u << 9)
  40. #define HSI2C_INT_ERROR_MASK (HSI2C_TX_UNDERRUN_EN |\
  41. HSI2C_TX_OVERRUN_EN |\
  42. HSI2C_RX_UNDERRUN_EN |\
  43. HSI2C_RX_OVERRUN_EN |\
  44. HSI2C_INT_TRAILING_EN)
  45. /* I2C_CONF Register bits */
  46. #define HSI2C_AUTO_MODE (1u << 31)
  47. #define HSI2C_10BIT_ADDR_MODE (1u << 30)
  48. #define HSI2C_HS_MODE (1u << 29)
  49. /* I2C_AUTO_CONF Register bits */
  50. #define HSI2C_READ_WRITE (1u << 16)
  51. #define HSI2C_STOP_AFTER_TRANS (1u << 17)
  52. #define HSI2C_MASTER_RUN (1u << 31)
  53. /* I2C_TIMEOUT Register bits */
  54. #define HSI2C_TIMEOUT_EN (1u << 31)
  55. /* I2C_TRANS_STATUS register bits */
  56. #define HSI2C_MASTER_BUSY (1u << 17)
  57. #define HSI2C_SLAVE_BUSY (1u << 16)
  58. #define HSI2C_TIMEOUT_AUTO (1u << 4)
  59. #define HSI2C_NO_DEV (1u << 3)
  60. #define HSI2C_NO_DEV_ACK (1u << 2)
  61. #define HSI2C_TRANS_ABORT (1u << 1)
  62. #define HSI2C_TRANS_SUCCESS (1u << 0)
  63. #define HSI2C_TRANS_ERROR_MASK (HSI2C_TIMEOUT_AUTO |\
  64. HSI2C_NO_DEV | HSI2C_NO_DEV_ACK |\
  65. HSI2C_TRANS_ABORT)
  66. #define HSI2C_TRANS_FINISHED_MASK (HSI2C_TRANS_ERROR_MASK | HSI2C_TRANS_SUCCESS)
  67. /* I2C_FIFO_STAT Register bits */
  68. #define HSI2C_RX_FIFO_EMPTY (1u << 24)
  69. #define HSI2C_RX_FIFO_FULL (1u << 23)
  70. #define HSI2C_TX_FIFO_EMPTY (1u << 8)
  71. #define HSI2C_TX_FIFO_FULL (1u << 7)
  72. #define HSI2C_RX_FIFO_LEVEL(x) (((x) >> 16) & 0x7f)
  73. #define HSI2C_TX_FIFO_LEVEL(x) ((x) & 0x7f)
  74. #define HSI2C_SLV_ADDR_MAS(x) ((x & 0x3ff) << 10)
  75. #define HSI2C_TIMEOUT_US 10000 /* 10 ms, finer granularity */
  76. /*
  77. * Wait for transfer completion.
  78. *
  79. * This function reads the interrupt status register waiting for the INT_I2C
  80. * bit to be set, which indicates copletion of a transaction.
  81. *
  82. * @param i2c: pointer to the appropriate register bank
  83. *
  84. * @return: I2C_OK in case of successful completion, I2C_NOK_TIMEOUT in case
  85. * the status bits do not get set in time, or an approrpiate error
  86. * value in case of transfer errors.
  87. */
  88. static int hsi2c_wait_for_trx(struct exynos5_hsi2c *i2c)
  89. {
  90. int i = HSI2C_TIMEOUT_US;
  91. while (i-- > 0) {
  92. u32 int_status = readl(&i2c->usi_int_stat);
  93. if (int_status & HSI2C_INT_I2C_EN) {
  94. u32 trans_status = readl(&i2c->usi_trans_status);
  95. /* Deassert pending interrupt. */
  96. writel(int_status, &i2c->usi_int_stat);
  97. if (trans_status & HSI2C_NO_DEV_ACK) {
  98. debug("%s: no ACK from device\n", __func__);
  99. return I2C_NACK;
  100. }
  101. if (trans_status & HSI2C_NO_DEV) {
  102. debug("%s: no device\n", __func__);
  103. return I2C_NOK;
  104. }
  105. if (trans_status & HSI2C_TRANS_ABORT) {
  106. debug("%s: arbitration lost\n", __func__);
  107. return I2C_NOK_LA;
  108. }
  109. if (trans_status & HSI2C_TIMEOUT_AUTO) {
  110. debug("%s: device timed out\n", __func__);
  111. return I2C_NOK_TOUT;
  112. }
  113. return I2C_OK;
  114. }
  115. udelay(1);
  116. }
  117. debug("%s: transaction timeout!\n", __func__);
  118. return I2C_NOK_TOUT;
  119. }
  120. static int hsi2c_get_clk_details(struct s3c24x0_i2c_bus *i2c_bus)
  121. {
  122. struct exynos5_hsi2c *hsregs = i2c_bus->hsregs;
  123. ulong clkin;
  124. unsigned int op_clk = i2c_bus->clock_frequency;
  125. unsigned int i = 0, utemp0 = 0, utemp1 = 0;
  126. unsigned int t_ftl_cycle;
  127. #if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
  128. clkin = get_i2c_clk();
  129. #else
  130. clkin = get_PCLK();
  131. #endif
  132. /* FPCLK / FI2C =
  133. * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE
  134. * uTemp0 = (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2)
  135. * uTemp1 = (TSCLK_L + TSCLK_H + 2)
  136. * uTemp2 = TSCLK_L + TSCLK_H
  137. */
  138. t_ftl_cycle = (readl(&hsregs->usi_conf) >> 16) & 0x7;
  139. utemp0 = (clkin / op_clk) - 8 - 2 * t_ftl_cycle;
  140. /* CLK_DIV max is 256 */
  141. for (i = 0; i < 256; i++) {
  142. utemp1 = utemp0 / (i + 1);
  143. if ((utemp1 < 512) && (utemp1 > 4)) {
  144. i2c_bus->clk_cycle = utemp1 - 2;
  145. i2c_bus->clk_div = i;
  146. return 0;
  147. }
  148. }
  149. return -EINVAL;
  150. }
  151. static void hsi2c_ch_init(struct s3c24x0_i2c_bus *i2c_bus)
  152. {
  153. struct exynos5_hsi2c *hsregs = i2c_bus->hsregs;
  154. unsigned int t_sr_release;
  155. unsigned int n_clkdiv;
  156. unsigned int t_start_su, t_start_hd;
  157. unsigned int t_stop_su;
  158. unsigned int t_data_su, t_data_hd;
  159. unsigned int t_scl_l, t_scl_h;
  160. u32 i2c_timing_s1;
  161. u32 i2c_timing_s2;
  162. u32 i2c_timing_s3;
  163. u32 i2c_timing_sla;
  164. n_clkdiv = i2c_bus->clk_div;
  165. t_scl_l = i2c_bus->clk_cycle / 2;
  166. t_scl_h = i2c_bus->clk_cycle / 2;
  167. t_start_su = t_scl_l;
  168. t_start_hd = t_scl_l;
  169. t_stop_su = t_scl_l;
  170. t_data_su = t_scl_l / 2;
  171. t_data_hd = t_scl_l / 2;
  172. t_sr_release = i2c_bus->clk_cycle;
  173. i2c_timing_s1 = t_start_su << 24 | t_start_hd << 16 | t_stop_su << 8;
  174. i2c_timing_s2 = t_data_su << 24 | t_scl_l << 8 | t_scl_h << 0;
  175. i2c_timing_s3 = n_clkdiv << 16 | t_sr_release << 0;
  176. i2c_timing_sla = t_data_hd << 0;
  177. writel(HSI2C_TRAILING_COUNT, &hsregs->usi_trailing_ctl);
  178. /* Clear to enable Timeout */
  179. clrsetbits_le32(&hsregs->usi_timeout, HSI2C_TIMEOUT_EN, 0);
  180. /* set AUTO mode */
  181. writel(readl(&hsregs->usi_conf) | HSI2C_AUTO_MODE, &hsregs->usi_conf);
  182. /* Enable completion conditions' reporting. */
  183. writel(HSI2C_INT_I2C_EN, &hsregs->usi_int_en);
  184. /* Enable FIFOs */
  185. writel(HSI2C_RXFIFO_EN | HSI2C_TXFIFO_EN, &hsregs->usi_fifo_ctl);
  186. /* Currently operating in Fast speed mode. */
  187. writel(i2c_timing_s1, &hsregs->usi_timing_fs1);
  188. writel(i2c_timing_s2, &hsregs->usi_timing_fs2);
  189. writel(i2c_timing_s3, &hsregs->usi_timing_fs3);
  190. writel(i2c_timing_sla, &hsregs->usi_timing_sla);
  191. }
  192. /* SW reset for the high speed bus */
  193. static void exynos5_i2c_reset(struct s3c24x0_i2c_bus *i2c_bus)
  194. {
  195. struct exynos5_hsi2c *i2c = i2c_bus->hsregs;
  196. u32 i2c_ctl;
  197. /* Set and clear the bit for reset */
  198. i2c_ctl = readl(&i2c->usi_ctl);
  199. i2c_ctl |= HSI2C_SW_RST;
  200. writel(i2c_ctl, &i2c->usi_ctl);
  201. i2c_ctl = readl(&i2c->usi_ctl);
  202. i2c_ctl &= ~HSI2C_SW_RST;
  203. writel(i2c_ctl, &i2c->usi_ctl);
  204. /* Initialize the configure registers */
  205. hsi2c_ch_init(i2c_bus);
  206. }
  207. /*
  208. * Poll the appropriate bit of the fifo status register until the interface is
  209. * ready to process the next byte or timeout expires.
  210. *
  211. * In addition to the FIFO status register this function also polls the
  212. * interrupt status register to be able to detect unexpected transaction
  213. * completion.
  214. *
  215. * When FIFO is ready to process the next byte, this function returns I2C_OK.
  216. * If in course of polling the INT_I2C assertion is detected, the function
  217. * returns I2C_NOK. If timeout happens before any of the above conditions is
  218. * met - the function returns I2C_NOK_TOUT;
  219. * @param i2c: pointer to the appropriate i2c register bank.
  220. * @param rx_transfer: set to True if the receive transaction is in progress.
  221. * @return: as described above.
  222. */
  223. static unsigned hsi2c_poll_fifo(struct exynos5_hsi2c *i2c, bool rx_transfer)
  224. {
  225. u32 fifo_bit = rx_transfer ? HSI2C_RX_FIFO_EMPTY : HSI2C_TX_FIFO_FULL;
  226. int i = HSI2C_TIMEOUT_US;
  227. while (readl(&i2c->usi_fifo_stat) & fifo_bit) {
  228. if (readl(&i2c->usi_int_stat) & HSI2C_INT_I2C_EN) {
  229. /*
  230. * There is a chance that assertion of
  231. * HSI2C_INT_I2C_EN and deassertion of
  232. * HSI2C_RX_FIFO_EMPTY happen simultaneously. Let's
  233. * give FIFO status priority and check it one more
  234. * time before reporting interrupt. The interrupt will
  235. * be reported next time this function is called.
  236. */
  237. if (rx_transfer &&
  238. !(readl(&i2c->usi_fifo_stat) & fifo_bit))
  239. break;
  240. return I2C_NOK;
  241. }
  242. if (!i--) {
  243. debug("%s: FIFO polling timeout!\n", __func__);
  244. return I2C_NOK_TOUT;
  245. }
  246. udelay(1);
  247. }
  248. return I2C_OK;
  249. }
  250. /*
  251. * Preapre hsi2c transaction, either read or write.
  252. *
  253. * Set up transfer as described in section 27.5.1.2 'I2C Channel Auto Mode' of
  254. * the 5420 UM.
  255. *
  256. * @param i2c: pointer to the appropriate i2c register bank.
  257. * @param chip: slave address on the i2c bus (with read/write bit exlcuded)
  258. * @param len: number of bytes expected to be sent or received
  259. * @param rx_transfer: set to true for receive transactions
  260. * @param: issue_stop: set to true if i2c stop condition should be generated
  261. * after this transaction.
  262. * @return: I2C_NOK_TOUT in case the bus remained busy for HSI2C_TIMEOUT_US,
  263. * I2C_OK otherwise.
  264. */
  265. static int hsi2c_prepare_transaction(struct exynos5_hsi2c *i2c,
  266. u8 chip,
  267. u16 len,
  268. bool rx_transfer,
  269. bool issue_stop)
  270. {
  271. u32 conf;
  272. conf = len | HSI2C_MASTER_RUN;
  273. if (issue_stop)
  274. conf |= HSI2C_STOP_AFTER_TRANS;
  275. /* Clear to enable Timeout */
  276. writel(readl(&i2c->usi_timeout) & ~HSI2C_TIMEOUT_EN, &i2c->usi_timeout);
  277. /* Set slave address */
  278. writel(HSI2C_SLV_ADDR_MAS(chip), &i2c->i2c_addr);
  279. if (rx_transfer) {
  280. /* i2c master, read transaction */
  281. writel((HSI2C_RXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER),
  282. &i2c->usi_ctl);
  283. /* read up to len bytes, stop after transaction is finished */
  284. writel(conf | HSI2C_READ_WRITE, &i2c->usi_auto_conf);
  285. } else {
  286. /* i2c master, write transaction */
  287. writel((HSI2C_TXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER),
  288. &i2c->usi_ctl);
  289. /* write up to len bytes, stop after transaction is finished */
  290. writel(conf, &i2c->usi_auto_conf);
  291. }
  292. /* Reset all pending interrupt status bits we care about, if any */
  293. writel(HSI2C_INT_I2C_EN, &i2c->usi_int_stat);
  294. return I2C_OK;
  295. }
  296. /*
  297. * Wait while i2c bus is settling down (mostly stop gets completed).
  298. */
  299. static int hsi2c_wait_while_busy(struct exynos5_hsi2c *i2c)
  300. {
  301. int i = HSI2C_TIMEOUT_US;
  302. while (readl(&i2c->usi_trans_status) & HSI2C_MASTER_BUSY) {
  303. if (!i--) {
  304. debug("%s: bus busy\n", __func__);
  305. return I2C_NOK_TOUT;
  306. }
  307. udelay(1);
  308. }
  309. return I2C_OK;
  310. }
  311. static int hsi2c_write(struct exynos5_hsi2c *i2c,
  312. unsigned char chip,
  313. unsigned char addr[],
  314. unsigned char alen,
  315. unsigned char data[],
  316. unsigned short len,
  317. bool issue_stop)
  318. {
  319. int i, rv = 0;
  320. if (!(len + alen)) {
  321. /* Writes of zero length not supported in auto mode. */
  322. debug("%s: zero length writes not supported\n", __func__);
  323. return I2C_NOK;
  324. }
  325. rv = hsi2c_prepare_transaction
  326. (i2c, chip, len + alen, false, issue_stop);
  327. if (rv != I2C_OK)
  328. return rv;
  329. /* Move address, if any, and the data, if any, into the FIFO. */
  330. for (i = 0; i < alen; i++) {
  331. rv = hsi2c_poll_fifo(i2c, false);
  332. if (rv != I2C_OK) {
  333. debug("%s: address write failed\n", __func__);
  334. goto write_error;
  335. }
  336. writel(addr[i], &i2c->usi_txdata);
  337. }
  338. for (i = 0; i < len; i++) {
  339. rv = hsi2c_poll_fifo(i2c, false);
  340. if (rv != I2C_OK) {
  341. debug("%s: data write failed\n", __func__);
  342. goto write_error;
  343. }
  344. writel(data[i], &i2c->usi_txdata);
  345. }
  346. rv = hsi2c_wait_for_trx(i2c);
  347. write_error:
  348. if (issue_stop) {
  349. int tmp_ret = hsi2c_wait_while_busy(i2c);
  350. if (rv == I2C_OK)
  351. rv = tmp_ret;
  352. }
  353. writel(HSI2C_FUNC_MODE_I2C, &i2c->usi_ctl); /* done */
  354. return rv;
  355. }
  356. static int hsi2c_read(struct exynos5_hsi2c *i2c,
  357. unsigned char chip,
  358. unsigned char addr[],
  359. unsigned char alen,
  360. unsigned char data[],
  361. unsigned short len)
  362. {
  363. int i, rv, tmp_ret;
  364. bool drop_data = false;
  365. if (!len) {
  366. /* Reads of zero length not supported in auto mode. */
  367. debug("%s: zero length read adjusted\n", __func__);
  368. drop_data = true;
  369. len = 1;
  370. }
  371. if (alen) {
  372. /* Internal register adress needs to be written first. */
  373. rv = hsi2c_write(i2c, chip, addr, alen, NULL, 0, false);
  374. if (rv != I2C_OK)
  375. return rv;
  376. }
  377. rv = hsi2c_prepare_transaction(i2c, chip, len, true, true);
  378. if (rv != I2C_OK)
  379. return rv;
  380. for (i = 0; i < len; i++) {
  381. rv = hsi2c_poll_fifo(i2c, true);
  382. if (rv != I2C_OK)
  383. goto read_err;
  384. if (drop_data)
  385. continue;
  386. data[i] = readl(&i2c->usi_rxdata);
  387. }
  388. rv = hsi2c_wait_for_trx(i2c);
  389. read_err:
  390. tmp_ret = hsi2c_wait_while_busy(i2c);
  391. if (rv == I2C_OK)
  392. rv = tmp_ret;
  393. writel(HSI2C_FUNC_MODE_I2C, &i2c->usi_ctl); /* done */
  394. return rv;
  395. }
  396. static int exynos_hs_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
  397. int nmsgs)
  398. {
  399. struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
  400. struct exynos5_hsi2c *hsregs = i2c_bus->hsregs;
  401. int ret;
  402. for (; nmsgs > 0; nmsgs--, msg++) {
  403. if (msg->flags & I2C_M_RD) {
  404. ret = hsi2c_read(hsregs, msg->addr, 0, 0, msg->buf,
  405. msg->len);
  406. } else {
  407. ret = hsi2c_write(hsregs, msg->addr, 0, 0, msg->buf,
  408. msg->len, true);
  409. }
  410. if (ret) {
  411. exynos5_i2c_reset(i2c_bus);
  412. return -EREMOTEIO;
  413. }
  414. }
  415. return 0;
  416. }
  417. static int s3c24x0_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
  418. {
  419. struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
  420. i2c_bus->clock_frequency = speed;
  421. if (hsi2c_get_clk_details(i2c_bus))
  422. return -EFAULT;
  423. hsi2c_ch_init(i2c_bus);
  424. return 0;
  425. }
  426. static int s3c24x0_i2c_probe(struct udevice *dev, uint chip, uint chip_flags)
  427. {
  428. struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
  429. uchar buf[1];
  430. int ret;
  431. buf[0] = 0;
  432. /*
  433. * What is needed is to send the chip address and verify that the
  434. * address was <ACK>ed (i.e. there was a chip at that address which
  435. * drove the data line low).
  436. */
  437. ret = hsi2c_read(i2c_bus->hsregs, chip, 0, 0, buf, 1);
  438. return ret != I2C_OK;
  439. }
  440. static int s3c_i2c_of_to_plat(struct udevice *dev)
  441. {
  442. const void *blob = gd->fdt_blob;
  443. struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
  444. int node;
  445. node = dev_of_offset(dev);
  446. i2c_bus->hsregs = dev_read_addr_ptr(dev);
  447. i2c_bus->id = pinmux_decode_periph_id(blob, node);
  448. i2c_bus->clock_frequency =
  449. dev_read_u32_default(dev, "clock-frequency",
  450. I2C_SPEED_STANDARD_RATE);
  451. i2c_bus->node = node;
  452. i2c_bus->bus_num = dev_seq(dev);
  453. exynos_pinmux_config(i2c_bus->id, PINMUX_FLAG_HS_MODE);
  454. i2c_bus->active = true;
  455. return 0;
  456. }
  457. static const struct dm_i2c_ops exynos_hs_i2c_ops = {
  458. .xfer = exynos_hs_i2c_xfer,
  459. .probe_chip = s3c24x0_i2c_probe,
  460. .set_bus_speed = s3c24x0_i2c_set_bus_speed,
  461. };
  462. static const struct udevice_id exynos_hs_i2c_ids[] = {
  463. { .compatible = "samsung,exynos5-hsi2c" },
  464. { }
  465. };
  466. U_BOOT_DRIVER(hs_i2c) = {
  467. .name = "i2c_s3c_hs",
  468. .id = UCLASS_I2C,
  469. .of_match = exynos_hs_i2c_ids,
  470. .of_to_plat = s3c_i2c_of_to_plat,
  471. .priv_auto = sizeof(struct s3c24x0_i2c_bus),
  472. .ops = &exynos_hs_i2c_ops,
  473. };