designware_i2c_pci.c 5.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2009
  4. * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
  5. * Copyright 2019 Google Inc
  6. */
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <log.h>
  10. #include <spl.h>
  11. #include <acpi/acpigen.h>
  12. #include <acpi/acpi_device.h>
  13. #include <asm/lpss.h>
  14. #include <dm/acpi.h>
  15. #include <dm/device-internal.h>
  16. #include <dm/uclass-internal.h>
  17. #include "designware_i2c.h"
  18. enum {
  19. VANILLA = 0, /* standard I2C with no tweaks */
  20. INTEL_APL, /* Apollo Lake I2C */
  21. };
  22. /* BayTrail HCNT/LCNT/SDA hold time */
  23. static struct dw_scl_sda_cfg byt_config = {
  24. .ss_hcnt = 0x200,
  25. .fs_hcnt = 0x55,
  26. .ss_lcnt = 0x200,
  27. .fs_lcnt = 0x99,
  28. .sda_hold = 0x6,
  29. };
  30. /* Have a weak function for now - possibly should be a new uclass */
  31. __weak void lpss_reset_release(void *regs);
  32. static int designware_i2c_pci_of_to_plat(struct udevice *dev)
  33. {
  34. struct dw_i2c *priv = dev_get_priv(dev);
  35. if (spl_phase() < PHASE_SPL) {
  36. u32 base;
  37. int ret;
  38. ret = dev_read_u32(dev, "early-regs", &base);
  39. if (ret)
  40. return log_msg_ret("early-regs", ret);
  41. /* Set i2c base address */
  42. dm_pci_write_config32(dev, PCI_BASE_ADDRESS_0, base);
  43. /* Enable memory access and bus master */
  44. dm_pci_write_config32(dev, PCI_COMMAND, PCI_COMMAND_MEMORY |
  45. PCI_COMMAND_MASTER);
  46. }
  47. if (spl_phase() < PHASE_BOARD_F) {
  48. /* Handle early, fixed mapping into a different address space */
  49. priv->regs = (struct i2c_regs *)dm_pci_read_bar32(dev, 0);
  50. } else {
  51. priv->regs = (struct i2c_regs *)
  52. dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
  53. }
  54. if (!priv->regs)
  55. return -EINVAL;
  56. /* Save base address from PCI BAR */
  57. if (IS_ENABLED(CONFIG_INTEL_BAYTRAIL))
  58. /* Use BayTrail specific timing values */
  59. priv->scl_sda_cfg = &byt_config;
  60. if (dev_get_driver_data(dev) == INTEL_APL)
  61. priv->has_spk_cnt = true;
  62. return designware_i2c_of_to_plat(dev);
  63. }
  64. static int designware_i2c_pci_probe(struct udevice *dev)
  65. {
  66. struct dw_i2c *priv = dev_get_priv(dev);
  67. if (dev_get_driver_data(dev) == INTEL_APL) {
  68. /* Ensure controller is in D0 state */
  69. lpss_set_power_state(dev, STATE_D0);
  70. lpss_reset_release(priv->regs);
  71. }
  72. return designware_i2c_probe(dev);
  73. }
  74. static int designware_i2c_pci_bind(struct udevice *dev)
  75. {
  76. char name[20];
  77. if (dev_has_ofnode(dev))
  78. return 0;
  79. sprintf(name, "i2c_designware#%u", dev_seq(dev));
  80. device_set_name(dev, name);
  81. return 0;
  82. }
  83. /*
  84. * Write ACPI object to describe speed configuration.
  85. *
  86. * ACPI Object: Name ("xxxx", Package () { scl_lcnt, scl_hcnt, sda_hold }
  87. *
  88. * SSCN: I2C_SPEED_STANDARD
  89. * FMCN: I2C_SPEED_FAST
  90. * FPCN: I2C_SPEED_FAST_PLUS
  91. * HSCN: I2C_SPEED_HIGH
  92. */
  93. static void dw_i2c_acpi_write_speed_config(struct acpi_ctx *ctx,
  94. struct dw_i2c_speed_config *config)
  95. {
  96. switch (config->speed_mode) {
  97. case IC_SPEED_MODE_HIGH:
  98. acpigen_write_name(ctx, "HSCN");
  99. break;
  100. case IC_SPEED_MODE_FAST_PLUS:
  101. acpigen_write_name(ctx, "FPCN");
  102. break;
  103. case IC_SPEED_MODE_FAST:
  104. acpigen_write_name(ctx, "FMCN");
  105. break;
  106. case IC_SPEED_MODE_STANDARD:
  107. default:
  108. acpigen_write_name(ctx, "SSCN");
  109. }
  110. /* Package () { scl_lcnt, scl_hcnt, sda_hold } */
  111. acpigen_write_package(ctx, 3);
  112. acpigen_write_word(ctx, config->scl_hcnt);
  113. acpigen_write_word(ctx, config->scl_lcnt);
  114. acpigen_write_dword(ctx, config->sda_hold);
  115. acpigen_pop_len(ctx);
  116. }
  117. /*
  118. * Generate I2C timing information into the SSDT for the OS driver to consume,
  119. * optionally applying override values provided by the caller.
  120. */
  121. static int dw_i2c_acpi_fill_ssdt(const struct udevice *dev,
  122. struct acpi_ctx *ctx)
  123. {
  124. struct dw_i2c_speed_config config;
  125. char path[ACPI_PATH_MAX];
  126. u32 speeds[4];
  127. uint speed;
  128. int size;
  129. int ret;
  130. /* If no device-tree node, ignore this since we assume it isn't used */
  131. if (!dev_has_ofnode(dev))
  132. return 0;
  133. ret = acpi_device_path(dev, path, sizeof(path));
  134. if (ret)
  135. return log_msg_ret("path", ret);
  136. size = dev_read_size(dev, "i2c,speeds");
  137. if (size < 0)
  138. return log_msg_ret("i2c,speeds", -EINVAL);
  139. size /= sizeof(u32);
  140. if (size > ARRAY_SIZE(speeds))
  141. return log_msg_ret("array", -E2BIG);
  142. ret = dev_read_u32_array(dev, "i2c,speeds", speeds, size);
  143. if (ret)
  144. return log_msg_ret("read", -E2BIG);
  145. speed = dev_read_u32_default(dev, "clock-frequency", 100000);
  146. acpigen_write_scope(ctx, path);
  147. ret = dw_i2c_gen_speed_config(dev, speed, &config);
  148. if (ret)
  149. return log_msg_ret("config", ret);
  150. dw_i2c_acpi_write_speed_config(ctx, &config);
  151. acpigen_pop_len(ctx);
  152. return 0;
  153. }
  154. struct acpi_ops dw_i2c_acpi_ops = {
  155. .fill_ssdt = dw_i2c_acpi_fill_ssdt,
  156. };
  157. static const struct udevice_id designware_i2c_pci_ids[] = {
  158. { .compatible = "snps,designware-i2c-pci" },
  159. { .compatible = "intel,apl-i2c", .data = INTEL_APL },
  160. { }
  161. };
  162. DM_DRIVER_ALIAS(i2c_designware_pci, intel_apl_i2c)
  163. U_BOOT_DRIVER(i2c_designware_pci) = {
  164. .name = "i2c_designware_pci",
  165. .id = UCLASS_I2C,
  166. .of_match = designware_i2c_pci_ids,
  167. .bind = designware_i2c_pci_bind,
  168. .of_to_plat = designware_i2c_pci_of_to_plat,
  169. .probe = designware_i2c_pci_probe,
  170. .priv_auto = sizeof(struct dw_i2c),
  171. .remove = designware_i2c_remove,
  172. .flags = DM_FLAG_OS_PREPARE,
  173. .ops = &designware_i2c_ops,
  174. ACPI_OPS_PTR(&dw_i2c_acpi_ops)
  175. };
  176. static struct pci_device_id designware_pci_supported[] = {
  177. /* Intel BayTrail has 7 I2C controller located on the PCI bus */
  178. { PCI_VDEVICE(INTEL, 0x0f41) },
  179. { PCI_VDEVICE(INTEL, 0x0f42) },
  180. { PCI_VDEVICE(INTEL, 0x0f43) },
  181. { PCI_VDEVICE(INTEL, 0x0f44) },
  182. { PCI_VDEVICE(INTEL, 0x0f45) },
  183. { PCI_VDEVICE(INTEL, 0x0f46) },
  184. { PCI_VDEVICE(INTEL, 0x0f47) },
  185. { PCI_VDEVICE(INTEL, 0x5aac), .driver_data = INTEL_APL },
  186. { PCI_VDEVICE(INTEL, 0x5aae), .driver_data = INTEL_APL },
  187. { PCI_VDEVICE(INTEL, 0x5ab0), .driver_data = INTEL_APL },
  188. { PCI_VDEVICE(INTEL, 0x5ab2), .driver_data = INTEL_APL },
  189. { PCI_VDEVICE(INTEL, 0x5ab4), .driver_data = INTEL_APL },
  190. { PCI_VDEVICE(INTEL, 0x5ab6), .driver_data = INTEL_APL },
  191. {},
  192. };
  193. U_BOOT_PCI_DEVICE(i2c_designware_pci, designware_pci_supported);