designware_i2c.h 6.1 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2009
  4. * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
  5. */
  6. #ifndef __DW_I2C_H_
  7. #define __DW_I2C_H_
  8. #include <clk.h>
  9. #include <i2c.h>
  10. #include <reset.h>
  11. #include <linux/bitops.h>
  12. struct i2c_regs {
  13. u32 ic_con; /* 0x00 */
  14. u32 ic_tar; /* 0x04 */
  15. u32 ic_sar; /* 0x08 */
  16. u32 ic_hs_maddr; /* 0x0c */
  17. u32 ic_cmd_data; /* 0x10 */
  18. u32 ic_ss_scl_hcnt; /* 0x14 */
  19. u32 ic_ss_scl_lcnt; /* 0x18 */
  20. u32 ic_fs_scl_hcnt; /* 0x1c */
  21. u32 ic_fs_scl_lcnt; /* 0x20 */
  22. u32 ic_hs_scl_hcnt; /* 0x24 */
  23. u32 ic_hs_scl_lcnt; /* 0x28 */
  24. u32 ic_intr_stat; /* 0x2c */
  25. u32 ic_intr_mask; /* 0x30 */
  26. u32 ic_raw_intr_stat; /* 0x34 */
  27. u32 ic_rx_tl; /* 0x38 */
  28. u32 ic_tx_tl; /* 0x3c */
  29. u32 ic_clr_intr; /* 0x40 */
  30. u32 ic_clr_rx_under; /* 0x44 */
  31. u32 ic_clr_rx_over; /* 0x48 */
  32. u32 ic_clr_tx_over; /* 0x4c */
  33. u32 ic_clr_rd_req; /* 0x50 */
  34. u32 ic_clr_tx_abrt; /* 0x54 */
  35. u32 ic_clr_rx_done; /* 0x58 */
  36. u32 ic_clr_activity; /* 0x5c */
  37. u32 ic_clr_stop_det; /* 0x60 */
  38. u32 ic_clr_start_det; /* 0x64 */
  39. u32 ic_clr_gen_call; /* 0x68 */
  40. u32 ic_enable; /* 0x6c */
  41. u32 ic_status; /* 0x70 */
  42. u32 ic_txflr; /* 0x74 */
  43. u32 ic_rxflr; /* 0x78 */
  44. u32 ic_sda_hold; /* 0x7c */
  45. u32 ic_tx_abrt_source; /* 0x80 */
  46. u32 slv_data_nak_only;
  47. u32 dma_cr;
  48. u32 dma_tdlr;
  49. u32 dma_rdlr;
  50. u32 sda_setup;
  51. u32 ack_general_call;
  52. u32 ic_enable_status; /* 0x9c */
  53. u32 fs_spklen;
  54. u32 hs_spklen;
  55. u32 clr_restart_det;
  56. u8 reserved[0xf4 - 0xac];
  57. u32 comp_param1; /* 0xf4 */
  58. u32 comp_version;
  59. u32 comp_type;
  60. };
  61. #define IC_CLK 166666666
  62. #define NANO_TO_KILO 1000000
  63. /* High and low times in different speed modes (in ns) */
  64. #define MIN_SS_SCL_HIGHTIME 4000
  65. #define MIN_SS_SCL_LOWTIME 4700
  66. #define MIN_FS_SCL_HIGHTIME 600
  67. #define MIN_FS_SCL_LOWTIME 1300
  68. #define MIN_FP_SCL_HIGHTIME 260
  69. #define MIN_FP_SCL_LOWTIME 500
  70. #define MIN_HS_SCL_HIGHTIME 60
  71. #define MIN_HS_SCL_LOWTIME 160
  72. /* Worst case timeout for 1 byte is kept as 2ms */
  73. #define I2C_BYTE_TO (CONFIG_SYS_HZ/500)
  74. #define I2C_STOPDET_TO (CONFIG_SYS_HZ/500)
  75. #define I2C_BYTE_TO_BB (I2C_BYTE_TO * 16)
  76. /* i2c control register definitions */
  77. #define IC_CON_SD 0x0040
  78. #define IC_CON_RE 0x0020
  79. #define IC_CON_10BITADDRMASTER 0x0010
  80. #define IC_CON_10BITADDR_SLAVE 0x0008
  81. #define IC_CON_SPD_MSK 0x0006
  82. #define IC_CON_SPD_SS 0x0002
  83. #define IC_CON_SPD_FS 0x0004
  84. #define IC_CON_SPD_HS 0x0006
  85. #define IC_CON_MM 0x0001
  86. /* i2c target address register definitions */
  87. #define TAR_ADDR 0x0050
  88. /* i2c slave address register definitions */
  89. #define IC_SLAVE_ADDR 0x0002
  90. /* i2c data buffer and command register definitions */
  91. #define IC_CMD 0x0100
  92. #define IC_STOP 0x0200
  93. /* i2c interrupt status register definitions */
  94. #define IC_GEN_CALL 0x0800
  95. #define IC_START_DET 0x0400
  96. #define IC_STOP_DET 0x0200
  97. #define IC_ACTIVITY 0x0100
  98. #define IC_RX_DONE 0x0080
  99. #define IC_TX_ABRT 0x0040
  100. #define IC_RD_REQ 0x0020
  101. #define IC_TX_EMPTY 0x0010
  102. #define IC_TX_OVER 0x0008
  103. #define IC_RX_FULL 0x0004
  104. #define IC_RX_OVER 0x0002
  105. #define IC_RX_UNDER 0x0001
  106. /* fifo threshold register definitions */
  107. #define IC_TL0 0x00
  108. #define IC_TL1 0x01
  109. #define IC_TL2 0x02
  110. #define IC_TL3 0x03
  111. #define IC_TL4 0x04
  112. #define IC_TL5 0x05
  113. #define IC_TL6 0x06
  114. #define IC_TL7 0x07
  115. #define IC_RX_TL IC_TL0
  116. #define IC_TX_TL IC_TL0
  117. /* i2c enable register definitions */
  118. #define IC_ENABLE_0B 0x0001
  119. /* i2c status register definitions */
  120. #define IC_STATUS_SA 0x0040
  121. #define IC_STATUS_MA 0x0020
  122. #define IC_STATUS_RFF 0x0010
  123. #define IC_STATUS_RFNE 0x0008
  124. #define IC_STATUS_TFE 0x0004
  125. #define IC_STATUS_TFNF 0x0002
  126. #define IC_STATUS_ACT 0x0001
  127. #define DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH (BIT(2) | BIT(3))
  128. #define DW_IC_COMP_PARAM_1_SPEED_MODE_MASK (BIT(2) | BIT(3))
  129. /**
  130. * struct dw_scl_sda_cfg - I2C timing configuration
  131. *
  132. * @ss_hcnt: Standard speed high time in ns
  133. * @fs_hcnt: Fast speed high time in ns
  134. * @hs_hcnt: High speed high time in ns
  135. * @ss_lcnt: Standard speed low time in ns
  136. * @fs_lcnt: Fast speed low time in ns
  137. * @hs_lcnt: High speed low time in ns
  138. * @sda_hold: SDA hold time
  139. */
  140. struct dw_scl_sda_cfg {
  141. u32 ss_hcnt;
  142. u32 fs_hcnt;
  143. u32 hs_hcnt;
  144. u32 ss_lcnt;
  145. u32 fs_lcnt;
  146. u32 hs_lcnt;
  147. u32 sda_hold;
  148. };
  149. /**
  150. * struct dw_i2c_speed_config - timings to use for a particular speed
  151. *
  152. * This holds calculated values to be written to the I2C controller. Each value
  153. * is represented as a number of IC clock cycles.
  154. *
  155. * @scl_lcnt: Low count value for SCL
  156. * @scl_hcnt: High count value for SCL
  157. * @sda_hold: Data hold count
  158. * @speed_mode: Speed mode being used
  159. */
  160. struct dw_i2c_speed_config {
  161. /* SCL high and low period count */
  162. u16 scl_lcnt;
  163. u16 scl_hcnt;
  164. u32 sda_hold;
  165. enum i2c_speed_mode speed_mode;
  166. };
  167. /**
  168. * struct dw_i2c - private information for the bus
  169. *
  170. * @regs: Registers pointer
  171. * @scl_sda_cfg: Deprecated information for x86 (should move to device tree)
  172. * @resets: Resets for the I2C controller
  173. * @scl_rise_time_ns: Configured SCL rise time in nanoseconds
  174. * @scl_fall_time_ns: Configured SCL fall time in nanoseconds
  175. * @sda_hold_time_ns: Configured SDA hold time in nanoseconds
  176. * @has_spk_cnt: true if the spike-count register is present
  177. * @clk: Clock input to the I2C controller
  178. */
  179. struct dw_i2c {
  180. struct i2c_regs *regs;
  181. struct dw_scl_sda_cfg *scl_sda_cfg;
  182. struct reset_ctl_bulk resets;
  183. u32 scl_rise_time_ns;
  184. u32 scl_fall_time_ns;
  185. u32 sda_hold_time_ns;
  186. bool has_spk_cnt;
  187. #if CONFIG_IS_ENABLED(CLK)
  188. struct clk clk;
  189. struct clk_bulk clks;
  190. #endif
  191. struct dw_i2c_speed_config config;
  192. };
  193. extern const struct dm_i2c_ops designware_i2c_ops;
  194. int designware_i2c_probe(struct udevice *bus);
  195. int designware_i2c_remove(struct udevice *dev);
  196. int designware_i2c_of_to_plat(struct udevice *bus);
  197. /**
  198. * dw_i2c_gen_speed_config() - Calculate config info from requested speed
  199. *
  200. * Calculate the speed config from the given @speed_hz and return it so that
  201. * it can be incorporated in ACPI tables
  202. *
  203. * @dev: I2C bus to check
  204. * @speed_hz: Requested speed in Hz
  205. * @config: Returns config to use for that speed
  206. * @return 0 if OK, -ve on error
  207. */
  208. int dw_i2c_gen_speed_config(const struct udevice *dev, int speed_hz,
  209. struct dw_i2c_speed_config *config);
  210. #endif /* __DW_I2C_H_ */