designware_i2c.c 21 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2009
  4. * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
  5. */
  6. #include <common.h>
  7. #include <clk.h>
  8. #include <dm.h>
  9. #include <i2c.h>
  10. #include <log.h>
  11. #include <malloc.h>
  12. #include <pci.h>
  13. #include <reset.h>
  14. #include <asm/io.h>
  15. #include <linux/delay.h>
  16. #include "designware_i2c.h"
  17. #include <dm/device_compat.h>
  18. #include <linux/err.h>
  19. /*
  20. * This assigned unique hex value is constant and is derived from the two ASCII
  21. * letters 'DW' followed by a 16-bit unsigned number
  22. */
  23. #define DW_I2C_COMP_TYPE 0x44570140
  24. static int dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
  25. {
  26. u32 ena = enable ? IC_ENABLE_0B : 0;
  27. int timeout = 100;
  28. do {
  29. writel(ena, &i2c_base->ic_enable);
  30. if ((readl(&i2c_base->ic_enable_status) & IC_ENABLE_0B) == ena)
  31. return 0;
  32. /*
  33. * Wait 10 times the signaling period of the highest I2C
  34. * transfer supported by the driver (for 400KHz this is
  35. * 25us) as described in the DesignWare I2C databook.
  36. */
  37. udelay(25);
  38. } while (timeout--);
  39. printf("timeout in %sabling I2C adapter\n", enable ? "en" : "dis");
  40. return -ETIMEDOUT;
  41. }
  42. /* High and low times in different speed modes (in ns) */
  43. enum {
  44. /* SDA Hold Time */
  45. DEFAULT_SDA_HOLD_TIME = 300,
  46. };
  47. /**
  48. * calc_counts() - Convert a period to a number of IC clk cycles
  49. *
  50. * @ic_clk: Input clock in Hz
  51. * @period_ns: Period to represent, in ns
  52. * @return calculated count
  53. */
  54. static uint calc_counts(uint ic_clk, uint period_ns)
  55. {
  56. return DIV_ROUND_UP(ic_clk / 1000 * period_ns, NANO_TO_KILO);
  57. }
  58. /**
  59. * struct i2c_mode_info - Information about an I2C speed mode
  60. *
  61. * Each speed mode has its own characteristics. This struct holds these to aid
  62. * calculations in dw_i2c_calc_timing().
  63. *
  64. * @speed: Speed in Hz
  65. * @min_scl_lowtime_ns: Minimum value for SCL low period in ns
  66. * @min_scl_hightime_ns: Minimum value for SCL high period in ns
  67. * @def_rise_time_ns: Default rise time in ns
  68. * @def_fall_time_ns: Default fall time in ns
  69. */
  70. struct i2c_mode_info {
  71. int speed;
  72. int min_scl_hightime_ns;
  73. int min_scl_lowtime_ns;
  74. int def_rise_time_ns;
  75. int def_fall_time_ns;
  76. };
  77. static const struct i2c_mode_info info_for_mode[] = {
  78. [IC_SPEED_MODE_STANDARD] = {
  79. I2C_SPEED_STANDARD_RATE,
  80. MIN_SS_SCL_HIGHTIME,
  81. MIN_SS_SCL_LOWTIME,
  82. 1000,
  83. 300,
  84. },
  85. [IC_SPEED_MODE_FAST] = {
  86. I2C_SPEED_FAST_RATE,
  87. MIN_FS_SCL_HIGHTIME,
  88. MIN_FS_SCL_LOWTIME,
  89. 300,
  90. 300,
  91. },
  92. [IC_SPEED_MODE_FAST_PLUS] = {
  93. I2C_SPEED_FAST_PLUS_RATE,
  94. MIN_FP_SCL_HIGHTIME,
  95. MIN_FP_SCL_LOWTIME,
  96. 260,
  97. 500,
  98. },
  99. [IC_SPEED_MODE_HIGH] = {
  100. I2C_SPEED_HIGH_RATE,
  101. MIN_HS_SCL_HIGHTIME,
  102. MIN_HS_SCL_LOWTIME,
  103. 120,
  104. 120,
  105. },
  106. };
  107. /**
  108. * dw_i2c_calc_timing() - Calculate the timings to use for a bus
  109. *
  110. * @priv: Bus private information (NULL if not using driver model)
  111. * @mode: Speed mode to use
  112. * @ic_clk: IC clock speed in Hz
  113. * @spk_cnt: Spike-suppression count
  114. * @config: Returns value to use
  115. * @return 0 if OK, -EINVAL if the calculation failed due to invalid data
  116. */
  117. static int dw_i2c_calc_timing(struct dw_i2c *priv, enum i2c_speed_mode mode,
  118. int ic_clk, int spk_cnt,
  119. struct dw_i2c_speed_config *config)
  120. {
  121. int fall_cnt, rise_cnt, min_tlow_cnt, min_thigh_cnt;
  122. int hcnt, lcnt, period_cnt, diff, tot;
  123. int sda_hold_time_ns, scl_rise_time_ns, scl_fall_time_ns;
  124. const struct i2c_mode_info *info;
  125. /*
  126. * Find the period, rise, fall, min tlow, and min thigh in terms of
  127. * counts of the IC clock
  128. */
  129. info = &info_for_mode[mode];
  130. period_cnt = ic_clk / info->speed;
  131. scl_rise_time_ns = priv && priv->scl_rise_time_ns ?
  132. priv->scl_rise_time_ns : info->def_rise_time_ns;
  133. scl_fall_time_ns = priv && priv->scl_fall_time_ns ?
  134. priv->scl_fall_time_ns : info->def_fall_time_ns;
  135. rise_cnt = calc_counts(ic_clk, scl_rise_time_ns);
  136. fall_cnt = calc_counts(ic_clk, scl_fall_time_ns);
  137. min_tlow_cnt = calc_counts(ic_clk, info->min_scl_lowtime_ns);
  138. min_thigh_cnt = calc_counts(ic_clk, info->min_scl_hightime_ns);
  139. debug("dw_i2c: mode %d, ic_clk %d, speed %d, period %d rise %d fall %d tlow %d thigh %d spk %d\n",
  140. mode, ic_clk, info->speed, period_cnt, rise_cnt, fall_cnt,
  141. min_tlow_cnt, min_thigh_cnt, spk_cnt);
  142. /*
  143. * Back-solve for hcnt and lcnt according to the following equations:
  144. * SCL_High_time = [(HCNT + IC_*_SPKLEN + 7) * ic_clk] + SCL_Fall_time
  145. * SCL_Low_time = [(LCNT + 1) * ic_clk] - SCL_Fall_time + SCL_Rise_time
  146. */
  147. hcnt = min_thigh_cnt - fall_cnt - 7 - spk_cnt;
  148. lcnt = min_tlow_cnt - rise_cnt + fall_cnt - 1;
  149. if (hcnt < 0 || lcnt < 0) {
  150. debug("dw_i2c: bad counts. hcnt = %d lcnt = %d\n", hcnt, lcnt);
  151. return log_msg_ret("counts", -EINVAL);
  152. }
  153. /*
  154. * Now add things back up to ensure the period is hit. If it is off,
  155. * split the difference and bias to lcnt for remainder
  156. */
  157. tot = hcnt + lcnt + 7 + spk_cnt + rise_cnt + 1;
  158. if (tot < period_cnt) {
  159. diff = (period_cnt - tot) / 2;
  160. hcnt += diff;
  161. lcnt += diff;
  162. tot = hcnt + lcnt + 7 + spk_cnt + rise_cnt + 1;
  163. lcnt += period_cnt - tot;
  164. }
  165. config->scl_lcnt = lcnt;
  166. config->scl_hcnt = hcnt;
  167. /* Use internal default unless other value is specified */
  168. sda_hold_time_ns = priv && priv->sda_hold_time_ns ?
  169. priv->sda_hold_time_ns : DEFAULT_SDA_HOLD_TIME;
  170. config->sda_hold = calc_counts(ic_clk, sda_hold_time_ns);
  171. debug("dw_i2c: hcnt = %d lcnt = %d sda hold = %d\n", hcnt, lcnt,
  172. config->sda_hold);
  173. return 0;
  174. }
  175. /**
  176. * calc_bus_speed() - Calculate the config to use for a particular i2c speed
  177. *
  178. * @priv: Private information for the driver (NULL if not using driver model)
  179. * @i2c_base: Registers for the I2C controller
  180. * @speed: Required i2c speed in Hz
  181. * @bus_clk: Input clock to the I2C controller in Hz (e.g. IC_CLK)
  182. * @config: Returns the config to use for this speed
  183. * @return 0 if OK, -ve on error
  184. */
  185. static int calc_bus_speed(struct dw_i2c *priv, struct i2c_regs *regs, int speed,
  186. ulong bus_clk, struct dw_i2c_speed_config *config)
  187. {
  188. const struct dw_scl_sda_cfg *scl_sda_cfg = NULL;
  189. enum i2c_speed_mode i2c_spd;
  190. int spk_cnt;
  191. int ret;
  192. if (priv)
  193. scl_sda_cfg = priv->scl_sda_cfg;
  194. /* Allow high speed if there is no config, or the config allows it */
  195. if (speed >= I2C_SPEED_HIGH_RATE)
  196. i2c_spd = IC_SPEED_MODE_HIGH;
  197. else if (speed >= I2C_SPEED_FAST_PLUS_RATE)
  198. i2c_spd = IC_SPEED_MODE_FAST_PLUS;
  199. else if (speed >= I2C_SPEED_FAST_RATE)
  200. i2c_spd = IC_SPEED_MODE_FAST;
  201. else
  202. i2c_spd = IC_SPEED_MODE_STANDARD;
  203. /* Check is high speed possible and fall back to fast mode if not */
  204. if (i2c_spd == IC_SPEED_MODE_HIGH) {
  205. u32 comp_param1;
  206. comp_param1 = readl(&regs->comp_param1);
  207. if ((comp_param1 & DW_IC_COMP_PARAM_1_SPEED_MODE_MASK)
  208. != DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH)
  209. i2c_spd = IC_SPEED_MODE_FAST;
  210. }
  211. /* Get the proper spike-suppression count based on target speed */
  212. if (!priv || !priv->has_spk_cnt)
  213. spk_cnt = 0;
  214. else if (i2c_spd >= IC_SPEED_MODE_HIGH)
  215. spk_cnt = readl(&regs->hs_spklen);
  216. else
  217. spk_cnt = readl(&regs->fs_spklen);
  218. if (scl_sda_cfg) {
  219. config->sda_hold = scl_sda_cfg->sda_hold;
  220. if (i2c_spd == IC_SPEED_MODE_STANDARD) {
  221. config->scl_hcnt = scl_sda_cfg->ss_hcnt;
  222. config->scl_lcnt = scl_sda_cfg->ss_lcnt;
  223. } else if (i2c_spd == IC_SPEED_MODE_HIGH) {
  224. config->scl_hcnt = scl_sda_cfg->hs_hcnt;
  225. config->scl_lcnt = scl_sda_cfg->hs_lcnt;
  226. } else {
  227. config->scl_hcnt = scl_sda_cfg->fs_hcnt;
  228. config->scl_lcnt = scl_sda_cfg->fs_lcnt;
  229. }
  230. } else {
  231. ret = dw_i2c_calc_timing(priv, i2c_spd, bus_clk, spk_cnt,
  232. config);
  233. if (ret)
  234. return log_msg_ret("gen_confg", ret);
  235. }
  236. config->speed_mode = i2c_spd;
  237. return 0;
  238. }
  239. /**
  240. * _dw_i2c_set_bus_speed() - Set the i2c speed
  241. *
  242. * @priv: Private information for the driver (NULL if not using driver model)
  243. * @i2c_base: Registers for the I2C controller
  244. * @speed: Required i2c speed in Hz
  245. * @bus_clk: Input clock to the I2C controller in Hz (e.g. IC_CLK)
  246. * @return 0 if OK, -ve on error
  247. */
  248. static int _dw_i2c_set_bus_speed(struct dw_i2c *priv, struct i2c_regs *i2c_base,
  249. unsigned int speed, unsigned int bus_clk)
  250. {
  251. struct dw_i2c_speed_config config;
  252. unsigned int cntl;
  253. unsigned int ena;
  254. int ret;
  255. ret = calc_bus_speed(priv, i2c_base, speed, bus_clk, &config);
  256. if (ret)
  257. return ret;
  258. /* Get enable setting for restore later */
  259. ena = readl(&i2c_base->ic_enable) & IC_ENABLE_0B;
  260. /* to set speed cltr must be disabled */
  261. dw_i2c_enable(i2c_base, false);
  262. cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK));
  263. switch (config.speed_mode) {
  264. case IC_SPEED_MODE_HIGH:
  265. cntl |= IC_CON_SPD_HS;
  266. writel(config.scl_hcnt, &i2c_base->ic_hs_scl_hcnt);
  267. writel(config.scl_lcnt, &i2c_base->ic_hs_scl_lcnt);
  268. break;
  269. case IC_SPEED_MODE_STANDARD:
  270. cntl |= IC_CON_SPD_SS;
  271. writel(config.scl_hcnt, &i2c_base->ic_ss_scl_hcnt);
  272. writel(config.scl_lcnt, &i2c_base->ic_ss_scl_lcnt);
  273. break;
  274. case IC_SPEED_MODE_FAST_PLUS:
  275. case IC_SPEED_MODE_FAST:
  276. default:
  277. cntl |= IC_CON_SPD_FS;
  278. writel(config.scl_hcnt, &i2c_base->ic_fs_scl_hcnt);
  279. writel(config.scl_lcnt, &i2c_base->ic_fs_scl_lcnt);
  280. break;
  281. }
  282. writel(cntl, &i2c_base->ic_con);
  283. /* Configure SDA Hold Time if required */
  284. if (config.sda_hold)
  285. writel(config.sda_hold, &i2c_base->ic_sda_hold);
  286. /* Restore back i2c now speed set */
  287. if (ena == IC_ENABLE_0B)
  288. dw_i2c_enable(i2c_base, true);
  289. if (priv)
  290. priv->config = config;
  291. return 0;
  292. }
  293. int dw_i2c_gen_speed_config(const struct udevice *dev, int speed_hz,
  294. struct dw_i2c_speed_config *config)
  295. {
  296. struct dw_i2c *priv = dev_get_priv(dev);
  297. ulong rate;
  298. int ret;
  299. #if CONFIG_IS_ENABLED(CLK)
  300. rate = clk_get_rate(&priv->clk);
  301. if (IS_ERR_VALUE(rate))
  302. return log_msg_ret("clk", -EINVAL);
  303. #else
  304. rate = IC_CLK;
  305. #endif
  306. ret = calc_bus_speed(priv, priv->regs, speed_hz, rate, config);
  307. if (ret)
  308. printf("%s: ret=%d\n", __func__, ret);
  309. if (ret)
  310. return log_msg_ret("calc_bus_speed", ret);
  311. return 0;
  312. }
  313. /*
  314. * i2c_setaddress - Sets the target slave address
  315. * @i2c_addr: target i2c address
  316. *
  317. * Sets the target slave address.
  318. */
  319. static void i2c_setaddress(struct i2c_regs *i2c_base, unsigned int i2c_addr)
  320. {
  321. /* Disable i2c */
  322. dw_i2c_enable(i2c_base, false);
  323. writel(i2c_addr, &i2c_base->ic_tar);
  324. /* Enable i2c */
  325. dw_i2c_enable(i2c_base, true);
  326. }
  327. /*
  328. * i2c_flush_rxfifo - Flushes the i2c RX FIFO
  329. *
  330. * Flushes the i2c RX FIFO
  331. */
  332. static void i2c_flush_rxfifo(struct i2c_regs *i2c_base)
  333. {
  334. while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE)
  335. readl(&i2c_base->ic_cmd_data);
  336. }
  337. /*
  338. * i2c_wait_for_bb - Waits for bus busy
  339. *
  340. * Waits for bus busy
  341. */
  342. static int i2c_wait_for_bb(struct i2c_regs *i2c_base)
  343. {
  344. unsigned long start_time_bb = get_timer(0);
  345. while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) ||
  346. !(readl(&i2c_base->ic_status) & IC_STATUS_TFE)) {
  347. /* Evaluate timeout */
  348. if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB))
  349. return 1;
  350. }
  351. return 0;
  352. }
  353. static int i2c_xfer_init(struct i2c_regs *i2c_base, uchar chip, uint addr,
  354. int alen)
  355. {
  356. if (i2c_wait_for_bb(i2c_base))
  357. return 1;
  358. i2c_setaddress(i2c_base, chip);
  359. while (alen) {
  360. alen--;
  361. /* high byte address going out first */
  362. writel((addr >> (alen * 8)) & 0xff,
  363. &i2c_base->ic_cmd_data);
  364. }
  365. return 0;
  366. }
  367. static int i2c_xfer_finish(struct i2c_regs *i2c_base)
  368. {
  369. ulong start_stop_det = get_timer(0);
  370. while (1) {
  371. if ((readl(&i2c_base->ic_raw_intr_stat) & IC_STOP_DET)) {
  372. readl(&i2c_base->ic_clr_stop_det);
  373. break;
  374. } else if (get_timer(start_stop_det) > I2C_STOPDET_TO) {
  375. break;
  376. }
  377. }
  378. if (i2c_wait_for_bb(i2c_base)) {
  379. printf("Timed out waiting for bus\n");
  380. return 1;
  381. }
  382. i2c_flush_rxfifo(i2c_base);
  383. return 0;
  384. }
  385. /*
  386. * i2c_read - Read from i2c memory
  387. * @chip: target i2c address
  388. * @addr: address to read from
  389. * @alen:
  390. * @buffer: buffer for read data
  391. * @len: no of bytes to be read
  392. *
  393. * Read from i2c memory.
  394. */
  395. static int __dw_i2c_read(struct i2c_regs *i2c_base, u8 dev, uint addr,
  396. int alen, u8 *buffer, int len)
  397. {
  398. unsigned long start_time_rx;
  399. unsigned int active = 0;
  400. #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
  401. /*
  402. * EEPROM chips that implement "address overflow" are ones
  403. * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
  404. * address and the extra bits end up in the "chip address"
  405. * bit slots. This makes a 24WC08 (1Kbyte) chip look like
  406. * four 256 byte chips.
  407. *
  408. * Note that we consider the length of the address field to
  409. * still be one byte because the extra address bits are
  410. * hidden in the chip address.
  411. */
  412. dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
  413. addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
  414. debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
  415. addr);
  416. #endif
  417. if (i2c_xfer_init(i2c_base, dev, addr, alen))
  418. return 1;
  419. start_time_rx = get_timer(0);
  420. while (len) {
  421. if (!active) {
  422. /*
  423. * Avoid writing to ic_cmd_data multiple times
  424. * in case this loop spins too quickly and the
  425. * ic_status RFNE bit isn't set after the first
  426. * write. Subsequent writes to ic_cmd_data can
  427. * trigger spurious i2c transfer.
  428. */
  429. if (len == 1)
  430. writel(IC_CMD | IC_STOP, &i2c_base->ic_cmd_data);
  431. else
  432. writel(IC_CMD, &i2c_base->ic_cmd_data);
  433. active = 1;
  434. }
  435. if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) {
  436. *buffer++ = (uchar)readl(&i2c_base->ic_cmd_data);
  437. len--;
  438. start_time_rx = get_timer(0);
  439. active = 0;
  440. } else if (get_timer(start_time_rx) > I2C_BYTE_TO) {
  441. return 1;
  442. }
  443. }
  444. return i2c_xfer_finish(i2c_base);
  445. }
  446. /*
  447. * i2c_write - Write to i2c memory
  448. * @chip: target i2c address
  449. * @addr: address to read from
  450. * @alen:
  451. * @buffer: buffer for read data
  452. * @len: no of bytes to be read
  453. *
  454. * Write to i2c memory.
  455. */
  456. static int __dw_i2c_write(struct i2c_regs *i2c_base, u8 dev, uint addr,
  457. int alen, u8 *buffer, int len)
  458. {
  459. int nb = len;
  460. unsigned long start_time_tx;
  461. #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
  462. /*
  463. * EEPROM chips that implement "address overflow" are ones
  464. * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
  465. * address and the extra bits end up in the "chip address"
  466. * bit slots. This makes a 24WC08 (1Kbyte) chip look like
  467. * four 256 byte chips.
  468. *
  469. * Note that we consider the length of the address field to
  470. * still be one byte because the extra address bits are
  471. * hidden in the chip address.
  472. */
  473. dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
  474. addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
  475. debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
  476. addr);
  477. #endif
  478. if (i2c_xfer_init(i2c_base, dev, addr, alen))
  479. return 1;
  480. start_time_tx = get_timer(0);
  481. while (len) {
  482. if (readl(&i2c_base->ic_status) & IC_STATUS_TFNF) {
  483. if (--len == 0) {
  484. writel(*buffer | IC_STOP,
  485. &i2c_base->ic_cmd_data);
  486. } else {
  487. writel(*buffer, &i2c_base->ic_cmd_data);
  488. }
  489. buffer++;
  490. start_time_tx = get_timer(0);
  491. } else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) {
  492. printf("Timed out. i2c write Failed\n");
  493. return 1;
  494. }
  495. }
  496. return i2c_xfer_finish(i2c_base);
  497. }
  498. /*
  499. * __dw_i2c_init - Init function
  500. * @speed: required i2c speed
  501. * @slaveaddr: slave address for the device
  502. *
  503. * Initialization function.
  504. */
  505. static int __dw_i2c_init(struct i2c_regs *i2c_base, int speed, int slaveaddr)
  506. {
  507. int ret;
  508. /* Disable i2c */
  509. ret = dw_i2c_enable(i2c_base, false);
  510. if (ret)
  511. return ret;
  512. writel(IC_CON_SD | IC_CON_RE | IC_CON_SPD_FS | IC_CON_MM,
  513. &i2c_base->ic_con);
  514. writel(IC_RX_TL, &i2c_base->ic_rx_tl);
  515. writel(IC_TX_TL, &i2c_base->ic_tx_tl);
  516. writel(IC_STOP_DET, &i2c_base->ic_intr_mask);
  517. #if !CONFIG_IS_ENABLED(DM_I2C)
  518. _dw_i2c_set_bus_speed(NULL, i2c_base, speed, IC_CLK);
  519. writel(slaveaddr, &i2c_base->ic_sar);
  520. #endif
  521. /* Enable i2c */
  522. ret = dw_i2c_enable(i2c_base, true);
  523. if (ret)
  524. return ret;
  525. return 0;
  526. }
  527. #if !CONFIG_IS_ENABLED(DM_I2C)
  528. /*
  529. * The legacy I2C functions. These need to get removed once
  530. * all users of this driver are converted to DM.
  531. */
  532. static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap)
  533. {
  534. switch (adap->hwadapnr) {
  535. #if CONFIG_SYS_I2C_BUS_MAX >= 4
  536. case 3:
  537. return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3;
  538. #endif
  539. #if CONFIG_SYS_I2C_BUS_MAX >= 3
  540. case 2:
  541. return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2;
  542. #endif
  543. #if CONFIG_SYS_I2C_BUS_MAX >= 2
  544. case 1:
  545. return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1;
  546. #endif
  547. case 0:
  548. return (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
  549. default:
  550. printf("Wrong I2C-adapter number %d\n", adap->hwadapnr);
  551. }
  552. return NULL;
  553. }
  554. static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
  555. unsigned int speed)
  556. {
  557. adap->speed = speed;
  558. return _dw_i2c_set_bus_speed(NULL, i2c_get_base(adap), speed, IC_CLK);
  559. }
  560. static void dw_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
  561. {
  562. __dw_i2c_init(i2c_get_base(adap), speed, slaveaddr);
  563. }
  564. static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
  565. int alen, u8 *buffer, int len)
  566. {
  567. return __dw_i2c_read(i2c_get_base(adap), dev, addr, alen, buffer, len);
  568. }
  569. static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
  570. int alen, u8 *buffer, int len)
  571. {
  572. return __dw_i2c_write(i2c_get_base(adap), dev, addr, alen, buffer, len);
  573. }
  574. /* dw_i2c_probe - Probe the i2c chip */
  575. static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev)
  576. {
  577. struct i2c_regs *i2c_base = i2c_get_base(adap);
  578. u32 tmp;
  579. int ret;
  580. /*
  581. * Try to read the first location of the chip.
  582. */
  583. ret = __dw_i2c_read(i2c_base, dev, 0, 1, (uchar *)&tmp, 1);
  584. if (ret)
  585. dw_i2c_init(adap, adap->speed, adap->slaveaddr);
  586. return ret;
  587. }
  588. U_BOOT_I2C_ADAP_COMPLETE(dw_0, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
  589. dw_i2c_write, dw_i2c_set_bus_speed,
  590. CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
  591. #if CONFIG_SYS_I2C_BUS_MAX >= 2
  592. U_BOOT_I2C_ADAP_COMPLETE(dw_1, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
  593. dw_i2c_write, dw_i2c_set_bus_speed,
  594. CONFIG_SYS_I2C_SPEED1, CONFIG_SYS_I2C_SLAVE1, 1)
  595. #endif
  596. #if CONFIG_SYS_I2C_BUS_MAX >= 3
  597. U_BOOT_I2C_ADAP_COMPLETE(dw_2, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
  598. dw_i2c_write, dw_i2c_set_bus_speed,
  599. CONFIG_SYS_I2C_SPEED2, CONFIG_SYS_I2C_SLAVE2, 2)
  600. #endif
  601. #if CONFIG_SYS_I2C_BUS_MAX >= 4
  602. U_BOOT_I2C_ADAP_COMPLETE(dw_3, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
  603. dw_i2c_write, dw_i2c_set_bus_speed,
  604. CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3)
  605. #endif
  606. #else /* CONFIG_DM_I2C */
  607. /* The DM I2C functions */
  608. static int designware_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
  609. int nmsgs)
  610. {
  611. struct dw_i2c *i2c = dev_get_priv(bus);
  612. int ret;
  613. debug("i2c_xfer: %d messages\n", nmsgs);
  614. for (; nmsgs > 0; nmsgs--, msg++) {
  615. debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
  616. if (msg->flags & I2C_M_RD) {
  617. ret = __dw_i2c_read(i2c->regs, msg->addr, 0, 0,
  618. msg->buf, msg->len);
  619. } else {
  620. ret = __dw_i2c_write(i2c->regs, msg->addr, 0, 0,
  621. msg->buf, msg->len);
  622. }
  623. if (ret) {
  624. debug("i2c_write: error sending\n");
  625. return -EREMOTEIO;
  626. }
  627. }
  628. return 0;
  629. }
  630. static int designware_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
  631. {
  632. struct dw_i2c *i2c = dev_get_priv(bus);
  633. ulong rate;
  634. #if CONFIG_IS_ENABLED(CLK)
  635. rate = clk_get_rate(&i2c->clk);
  636. if (IS_ERR_VALUE(rate))
  637. return log_ret(-EINVAL);
  638. #else
  639. rate = IC_CLK;
  640. #endif
  641. return _dw_i2c_set_bus_speed(i2c, i2c->regs, speed, rate);
  642. }
  643. static int designware_i2c_probe_chip(struct udevice *bus, uint chip_addr,
  644. uint chip_flags)
  645. {
  646. struct dw_i2c *i2c = dev_get_priv(bus);
  647. struct i2c_regs *i2c_base = i2c->regs;
  648. u32 tmp;
  649. int ret;
  650. /* Try to read the first location of the chip */
  651. ret = __dw_i2c_read(i2c_base, chip_addr, 0, 1, (uchar *)&tmp, 1);
  652. if (ret)
  653. __dw_i2c_init(i2c_base, 0, 0);
  654. return ret;
  655. }
  656. int designware_i2c_of_to_plat(struct udevice *bus)
  657. {
  658. struct dw_i2c *priv = dev_get_priv(bus);
  659. int ret;
  660. if (!priv->regs)
  661. priv->regs = dev_read_addr_ptr(bus);
  662. dev_read_u32(bus, "i2c-scl-rising-time-ns", &priv->scl_rise_time_ns);
  663. dev_read_u32(bus, "i2c-scl-falling-time-ns", &priv->scl_fall_time_ns);
  664. dev_read_u32(bus, "i2c-sda-hold-time-ns", &priv->sda_hold_time_ns);
  665. ret = reset_get_bulk(bus, &priv->resets);
  666. if (ret) {
  667. if (ret != -ENOTSUPP)
  668. dev_warn(bus, "Can't get reset: %d\n", ret);
  669. } else {
  670. reset_deassert_bulk(&priv->resets);
  671. }
  672. #if CONFIG_IS_ENABLED(CLK)
  673. ret = clk_get_by_index(bus, 0, &priv->clk);
  674. if (ret)
  675. return ret;
  676. ret = clk_get_bulk(bus, &priv->clks);
  677. if (ret)
  678. return ret;
  679. ret = clk_enable_bulk(&priv->clks);
  680. if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
  681. clk_release_bulk(&priv->clks);
  682. dev_err(bus, "failed to enable bulk clock\n");
  683. return ret;
  684. }
  685. #endif
  686. return 0;
  687. }
  688. int designware_i2c_probe(struct udevice *bus)
  689. {
  690. struct dw_i2c *priv = dev_get_priv(bus);
  691. uint comp_type;
  692. comp_type = readl(&priv->regs->comp_type);
  693. if (comp_type != DW_I2C_COMP_TYPE) {
  694. log_err("I2C bus %s has unknown type %#x\n", bus->name,
  695. comp_type);
  696. return -ENXIO;
  697. }
  698. log_debug("I2C bus %s version %#x\n", bus->name,
  699. readl(&priv->regs->comp_version));
  700. return __dw_i2c_init(priv->regs, 0, 0);
  701. }
  702. int designware_i2c_remove(struct udevice *dev)
  703. {
  704. struct dw_i2c *priv = dev_get_priv(dev);
  705. #if CONFIG_IS_ENABLED(CLK)
  706. clk_disable_bulk(&priv->clks);
  707. clk_release_bulk(&priv->clks);
  708. #endif
  709. return reset_release_bulk(&priv->resets);
  710. }
  711. const struct dm_i2c_ops designware_i2c_ops = {
  712. .xfer = designware_i2c_xfer,
  713. .probe_chip = designware_i2c_probe_chip,
  714. .set_bus_speed = designware_i2c_set_bus_speed,
  715. };
  716. static const struct udevice_id designware_i2c_ids[] = {
  717. { .compatible = "snps,designware-i2c" },
  718. { }
  719. };
  720. U_BOOT_DRIVER(i2c_designware) = {
  721. .name = "i2c_designware",
  722. .id = UCLASS_I2C,
  723. .of_match = designware_i2c_ids,
  724. .of_to_plat = designware_i2c_of_to_plat,
  725. .probe = designware_i2c_probe,
  726. .priv_auto = sizeof(struct dw_i2c),
  727. .remove = designware_i2c_remove,
  728. .flags = DM_FLAG_OS_PREPARE,
  729. .ops = &designware_i2c_ops,
  730. };
  731. #endif /* CONFIG_DM_I2C */