davinci_i2c.h 2.6 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2004-2014
  4. * Texas Instruments, <www.ti.com>
  5. *
  6. * Some changes copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
  7. */
  8. #ifndef _DAVINCI_I2C_H_
  9. #define _DAVINCI_I2C_H_
  10. #define I2C_WRITE 0
  11. #define I2C_READ 1
  12. struct i2c_regs {
  13. u32 i2c_oa;
  14. u32 i2c_ie;
  15. u32 i2c_stat;
  16. u32 i2c_scll;
  17. u32 i2c_sclh;
  18. u32 i2c_cnt;
  19. u32 i2c_drr;
  20. u32 i2c_sa;
  21. u32 i2c_dxr;
  22. u32 i2c_con;
  23. u32 i2c_iv;
  24. u32 res_2c;
  25. u32 i2c_psc;
  26. };
  27. /* I2C masks */
  28. /* I2C Interrupt Enable Register (I2C_IE): */
  29. #define I2C_IE_SCD_IE (1 << 5) /* Stop condition detect interrupt enable */
  30. #define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */
  31. #define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */
  32. #define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */
  33. #define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */
  34. #define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */
  35. /* I2C Status Register (I2C_STAT): */
  36. #define I2C_STAT_BB (1 << 12) /* Bus busy */
  37. #define I2C_STAT_ROVR (1 << 11) /* Receive overrun */
  38. #define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
  39. #define I2C_STAT_AAS (1 << 9) /* Address as slave */
  40. #define I2C_STAT_SCD (1 << 5) /* Stop condition detect */
  41. #define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
  42. #define I2C_STAT_RRDY (1 << 3) /* Receive data ready */
  43. #define I2C_STAT_ARDY (1 << 2) /* Register access ready */
  44. #define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */
  45. #define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */
  46. /* I2C Interrupt Code Register (I2C_INTCODE): */
  47. #define I2C_INTCODE_MASK 7
  48. #define I2C_INTCODE_NONE 0
  49. #define I2C_INTCODE_AL 1 /* Arbitration lost */
  50. #define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */
  51. #define I2C_INTCODE_ARDY 3 /* Register access ready */
  52. #define I2C_INTCODE_RRDY 4 /* Rcv data ready */
  53. #define I2C_INTCODE_XRDY 5 /* Xmit data ready */
  54. #define I2C_INTCODE_SCD 6 /* Stop condition detect */
  55. /* I2C Configuration Register (I2C_CON): */
  56. #define I2C_CON_EN (1 << 5) /* I2C module enable */
  57. #define I2C_CON_STB (1 << 4) /* Start byte mode (master mode only) */
  58. #define I2C_CON_MST (1 << 10) /* Master/slave mode */
  59. #define I2C_CON_TRX (1 << 9) /* Tx/Rx mode (master mode only) */
  60. #define I2C_CON_XA (1 << 8) /* Expand address */
  61. #define I2C_CON_STP (1 << 11) /* Stop condition (master mode only) */
  62. #define I2C_CON_STT (1 << 13) /* Start condition (master mode only) */
  63. #define I2C_CON_FREE (1 << 14) /* Free run on emulation */
  64. #define I2C_TIMEOUT 0xffff0000 /* Timeout mask for poll_i2c_irq() */
  65. #endif