tegra186_gpio_priv.h 1.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (c) 2016, NVIDIA CORPORATION.
  4. */
  5. #ifndef _TEGRA186_GPIO_PRIV_H_
  6. #define _TEGRA186_GPIO_PRIV_H_
  7. /*
  8. * For each GPIO, there are a set of registers than affect it, all packed
  9. * back-to-back.
  10. */
  11. #include <linux/bitops.h>
  12. #define TEGRA186_GPIO_ENABLE_CONFIG 0x00
  13. #define TEGRA186_GPIO_ENABLE_CONFIG_ENABLE BIT(0)
  14. #define TEGRA186_GPIO_ENABLE_CONFIG_OUT BIT(1)
  15. #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SHIFT 2
  16. #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK 3
  17. #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_NONE 0
  18. #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL 1
  19. #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE 2
  20. #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE 3
  21. #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL_HIGH_RISING BIT(4)
  22. #define TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE_ENABLE BIT(5)
  23. #define TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT_ENABLE BIT(6)
  24. #define TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMPING_ENABLE BIT(7)
  25. #define TEGRA186_GPIO_DEBOUNCE_THRESHOLD 0x04
  26. #define TEGRA186_GPIO_INPUT 0x08
  27. #define TEGRA186_GPIO_OUTPUT_CONTROL 0x0c
  28. #define TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED BIT(0)
  29. #define TEGRA186_GPIO_OUTPUT_VALUE 0x10
  30. #define TEGRA186_GPIO_OUTPUT_VALUE_HIGH 1
  31. #define TEGRA186_GPIO_INTERRUPT_CLEAR 0x14
  32. /*
  33. * 8 GPIOs are packed into a port. Their registers appear back-to-back in the
  34. * port's address space.
  35. */
  36. #define TEGRA186_GPIO_PER_GPIO_STRIDE 0x20
  37. #define TEGRA186_GPIO_PER_GPIO_COUNT 8
  38. /*
  39. * Per-port registers are packed immediately following all of a port's
  40. * per-GPIO registers.
  41. */
  42. #define TEGRA186_GPIO_INTERRUPT_STATUS_G 0x100
  43. #define TEGRA186_GPIO_INTERRUPT_STATUS_G_STRIDE 4
  44. #define TEGRA186_GPIO_INTERRUPT_STATUS_G_COUNT 8
  45. /*
  46. * The registers for multiple ports are packed together back-to-back to form
  47. * the overall controller.
  48. */
  49. #define TEGRA186_GPIO_PER_PORT_STRIDE 0x200
  50. #endif