rk_gpio.c 4.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2015 Google, Inc
  4. *
  5. * (C) Copyright 2008-2014 Rockchip Electronics
  6. * Peter, Software Engineering, <superpeter.cai@gmail.com>.
  7. */
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <syscon.h>
  11. #include <linux/errno.h>
  12. #include <asm/gpio.h>
  13. #include <asm/io.h>
  14. #include <asm/arch-rockchip/clock.h>
  15. #include <asm/arch-rockchip/gpio.h>
  16. #include <dm/pinctrl.h>
  17. #include <dt-bindings/clock/rk3288-cru.h>
  18. enum {
  19. ROCKCHIP_GPIOS_PER_BANK = 32,
  20. };
  21. #define OFFSET_TO_BIT(bit) (1UL << (bit))
  22. struct rockchip_gpio_priv {
  23. struct rockchip_gpio_regs *regs;
  24. struct udevice *pinctrl;
  25. int bank;
  26. char name[2];
  27. };
  28. static int rockchip_gpio_direction_input(struct udevice *dev, unsigned offset)
  29. {
  30. struct rockchip_gpio_priv *priv = dev_get_priv(dev);
  31. struct rockchip_gpio_regs *regs = priv->regs;
  32. clrbits_le32(&regs->swport_ddr, OFFSET_TO_BIT(offset));
  33. return 0;
  34. }
  35. static int rockchip_gpio_direction_output(struct udevice *dev, unsigned offset,
  36. int value)
  37. {
  38. struct rockchip_gpio_priv *priv = dev_get_priv(dev);
  39. struct rockchip_gpio_regs *regs = priv->regs;
  40. int mask = OFFSET_TO_BIT(offset);
  41. clrsetbits_le32(&regs->swport_dr, mask, value ? mask : 0);
  42. setbits_le32(&regs->swport_ddr, mask);
  43. return 0;
  44. }
  45. static int rockchip_gpio_get_value(struct udevice *dev, unsigned offset)
  46. {
  47. struct rockchip_gpio_priv *priv = dev_get_priv(dev);
  48. struct rockchip_gpio_regs *regs = priv->regs;
  49. return readl(&regs->ext_port) & OFFSET_TO_BIT(offset) ? 1 : 0;
  50. }
  51. static int rockchip_gpio_set_value(struct udevice *dev, unsigned offset,
  52. int value)
  53. {
  54. struct rockchip_gpio_priv *priv = dev_get_priv(dev);
  55. struct rockchip_gpio_regs *regs = priv->regs;
  56. int mask = OFFSET_TO_BIT(offset);
  57. clrsetbits_le32(&regs->swport_dr, mask, value ? mask : 0);
  58. return 0;
  59. }
  60. static int rockchip_gpio_get_function(struct udevice *dev, unsigned offset)
  61. {
  62. #ifdef CONFIG_SPL_BUILD
  63. return -ENODATA;
  64. #else
  65. struct rockchip_gpio_priv *priv = dev_get_priv(dev);
  66. struct rockchip_gpio_regs *regs = priv->regs;
  67. bool is_output;
  68. int ret;
  69. ret = pinctrl_get_gpio_mux(priv->pinctrl, priv->bank, offset);
  70. if (ret)
  71. return ret;
  72. is_output = readl(&regs->swport_ddr) & OFFSET_TO_BIT(offset);
  73. return is_output ? GPIOF_OUTPUT : GPIOF_INPUT;
  74. #endif
  75. }
  76. /* Simple SPL interface to GPIOs */
  77. #ifdef CONFIG_SPL_BUILD
  78. enum {
  79. PULL_NONE_1V8 = 0,
  80. PULL_DOWN_1V8 = 1,
  81. PULL_UP_1V8 = 3,
  82. };
  83. int spl_gpio_set_pull(void *vregs, uint gpio, int pull)
  84. {
  85. u32 *regs = vregs;
  86. uint val;
  87. regs += gpio >> GPIO_BANK_SHIFT;
  88. gpio &= GPIO_OFFSET_MASK;
  89. switch (pull) {
  90. case GPIO_PULL_UP:
  91. val = PULL_UP_1V8;
  92. break;
  93. case GPIO_PULL_DOWN:
  94. val = PULL_DOWN_1V8;
  95. break;
  96. case GPIO_PULL_NORMAL:
  97. default:
  98. val = PULL_NONE_1V8;
  99. break;
  100. }
  101. clrsetbits_le32(regs, 3 << (gpio * 2), val << (gpio * 2));
  102. return 0;
  103. }
  104. int spl_gpio_output(void *vregs, uint gpio, int value)
  105. {
  106. struct rockchip_gpio_regs * const regs = vregs;
  107. clrsetbits_le32(&regs->swport_dr, 1 << gpio, value << gpio);
  108. /* Set direction */
  109. clrsetbits_le32(&regs->swport_ddr, 1 << gpio, 1 << gpio);
  110. return 0;
  111. }
  112. #endif /* CONFIG_SPL_BUILD */
  113. static int rockchip_gpio_probe(struct udevice *dev)
  114. {
  115. struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
  116. struct rockchip_gpio_priv *priv = dev_get_priv(dev);
  117. char *end;
  118. int ret;
  119. priv->regs = dev_read_addr_ptr(dev);
  120. ret = uclass_first_device_err(UCLASS_PINCTRL, &priv->pinctrl);
  121. if (ret)
  122. return ret;
  123. uc_priv->gpio_count = ROCKCHIP_GPIOS_PER_BANK;
  124. end = strrchr(dev->name, '@');
  125. priv->bank = trailing_strtoln(dev->name, end);
  126. priv->name[0] = 'A' + priv->bank;
  127. uc_priv->bank_name = priv->name;
  128. return 0;
  129. }
  130. static const struct dm_gpio_ops gpio_rockchip_ops = {
  131. .direction_input = rockchip_gpio_direction_input,
  132. .direction_output = rockchip_gpio_direction_output,
  133. .get_value = rockchip_gpio_get_value,
  134. .set_value = rockchip_gpio_set_value,
  135. .get_function = rockchip_gpio_get_function,
  136. };
  137. static const struct udevice_id rockchip_gpio_ids[] = {
  138. { .compatible = "rockchip,gpio-bank" },
  139. { }
  140. };
  141. U_BOOT_DRIVER(rockchip_gpio_bank) = {
  142. .name = "rockchip_gpio_bank",
  143. .id = UCLASS_GPIO,
  144. .of_match = rockchip_gpio_ids,
  145. .ops = &gpio_rockchip_ops,
  146. .priv_auto = sizeof(struct rockchip_gpio_priv),
  147. .probe = rockchip_gpio_probe,
  148. };