nx_gpio.c 5.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2016 Nexell
  4. * DeokJin, Lee <truevirtue@nexell.co.kr>
  5. */
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <errno.h>
  9. #include <malloc.h>
  10. #include <asm/global_data.h>
  11. #include <asm/io.h>
  12. #include <asm/gpio.h>
  13. DECLARE_GLOBAL_DATA_PTR;
  14. struct nx_gpio_regs {
  15. u32 data; /* Data register */
  16. u32 outputenb; /* Output Enable register */
  17. u32 detmode[2]; /* Detect Mode Register */
  18. u32 intenb; /* Interrupt Enable Register */
  19. u32 det; /* Event Detect Register */
  20. u32 pad; /* Pad Status Register */
  21. };
  22. struct nx_alive_gpio_regs {
  23. u32 pwrgate; /* Power Gating Register */
  24. u32 reserved0[28]; /* Reserved0 */
  25. u32 outputenb_reset;/* Alive GPIO Output Enable Reset Register */
  26. u32 outputenb; /* Alive GPIO Output Enable Register */
  27. u32 outputenb_read; /* Alive GPIO Output Read Register */
  28. u32 reserved1[3]; /* Reserved1 */
  29. u32 pad_reset; /* Alive GPIO Output Reset Register */
  30. u32 data; /* Alive GPIO Output Register */
  31. u32 pad_read; /* Alive GPIO Pad Read Register */
  32. u32 reserved2[33]; /* Reserved2 */
  33. u32 pad; /* Alive GPIO Input Value Register */
  34. };
  35. struct nx_gpio_plat {
  36. void *regs;
  37. int gpio_count;
  38. const char *bank_name;
  39. };
  40. static int nx_alive_gpio_is_check(struct udevice *dev)
  41. {
  42. struct nx_gpio_plat *plat = dev_get_plat(dev);
  43. const char *bank_name = plat->bank_name;
  44. if (!strcmp(bank_name, "gpio_alv"))
  45. return 1;
  46. return 0;
  47. }
  48. static int nx_alive_gpio_direction_input(struct udevice *dev, unsigned int pin)
  49. {
  50. struct nx_gpio_plat *plat = dev_get_plat(dev);
  51. struct nx_alive_gpio_regs *const regs = plat->regs;
  52. setbits_le32(&regs->outputenb_reset, 1 << pin);
  53. return 0;
  54. }
  55. static int nx_alive_gpio_direction_output(struct udevice *dev, unsigned int pin,
  56. int val)
  57. {
  58. struct nx_gpio_plat *plat = dev_get_plat(dev);
  59. struct nx_alive_gpio_regs *const regs = plat->regs;
  60. if (val)
  61. setbits_le32(&regs->data, 1 << pin);
  62. else
  63. setbits_le32(&regs->pad_reset, 1 << pin);
  64. setbits_le32(&regs->outputenb, 1 << pin);
  65. return 0;
  66. }
  67. static int nx_alive_gpio_get_value(struct udevice *dev, unsigned int pin)
  68. {
  69. struct nx_gpio_plat *plat = dev_get_plat(dev);
  70. struct nx_alive_gpio_regs *const regs = plat->regs;
  71. unsigned int mask = 1UL << pin;
  72. unsigned int value;
  73. value = (readl(&regs->pad_read) & mask) >> pin;
  74. return value;
  75. }
  76. static int nx_alive_gpio_set_value(struct udevice *dev, unsigned int pin,
  77. int val)
  78. {
  79. struct nx_gpio_plat *plat = dev_get_plat(dev);
  80. struct nx_alive_gpio_regs *const regs = plat->regs;
  81. if (val)
  82. setbits_le32(&regs->data, 1 << pin);
  83. else
  84. clrbits_le32(&regs->pad_reset, 1 << pin);
  85. return 0;
  86. }
  87. static int nx_alive_gpio_get_function(struct udevice *dev, unsigned int pin)
  88. {
  89. struct nx_gpio_plat *plat = dev_get_plat(dev);
  90. struct nx_alive_gpio_regs *const regs = plat->regs;
  91. unsigned int mask = (1UL << pin);
  92. unsigned int output;
  93. output = readl(&regs->outputenb_read) & mask;
  94. if (output)
  95. return GPIOF_OUTPUT;
  96. else
  97. return GPIOF_INPUT;
  98. }
  99. static int nx_gpio_direction_input(struct udevice *dev, unsigned int pin)
  100. {
  101. struct nx_gpio_plat *plat = dev_get_plat(dev);
  102. struct nx_gpio_regs *const regs = plat->regs;
  103. if (nx_alive_gpio_is_check(dev))
  104. return nx_alive_gpio_direction_input(dev, pin);
  105. clrbits_le32(&regs->outputenb, 1 << pin);
  106. return 0;
  107. }
  108. static int nx_gpio_direction_output(struct udevice *dev, unsigned int pin,
  109. int val)
  110. {
  111. struct nx_gpio_plat *plat = dev_get_plat(dev);
  112. struct nx_gpio_regs *const regs = plat->regs;
  113. if (nx_alive_gpio_is_check(dev))
  114. return nx_alive_gpio_direction_output(dev, pin, val);
  115. if (val)
  116. setbits_le32(&regs->data, 1 << pin);
  117. else
  118. clrbits_le32(&regs->data, 1 << pin);
  119. setbits_le32(&regs->outputenb, 1 << pin);
  120. return 0;
  121. }
  122. static int nx_gpio_get_value(struct udevice *dev, unsigned int pin)
  123. {
  124. struct nx_gpio_plat *plat = dev_get_plat(dev);
  125. struct nx_gpio_regs *const regs = plat->regs;
  126. unsigned int mask = 1UL << pin;
  127. unsigned int value;
  128. if (nx_alive_gpio_is_check(dev))
  129. return nx_alive_gpio_get_value(dev, pin);
  130. value = (readl(&regs->pad) & mask) >> pin;
  131. return value;
  132. }
  133. static int nx_gpio_set_value(struct udevice *dev, unsigned int pin, int val)
  134. {
  135. struct nx_gpio_plat *plat = dev_get_plat(dev);
  136. struct nx_gpio_regs *const regs = plat->regs;
  137. if (nx_alive_gpio_is_check(dev))
  138. return nx_alive_gpio_set_value(dev, pin, val);
  139. if (val)
  140. setbits_le32(&regs->data, 1 << pin);
  141. else
  142. clrbits_le32(&regs->data, 1 << pin);
  143. return 0;
  144. }
  145. static int nx_gpio_get_function(struct udevice *dev, unsigned int pin)
  146. {
  147. struct nx_gpio_plat *plat = dev_get_plat(dev);
  148. struct nx_gpio_regs *const regs = plat->regs;
  149. unsigned int mask = (1UL << pin);
  150. unsigned int output;
  151. if (nx_alive_gpio_is_check(dev))
  152. return nx_alive_gpio_get_function(dev, pin);
  153. output = readl(&regs->outputenb) & mask;
  154. if (output)
  155. return GPIOF_OUTPUT;
  156. else
  157. return GPIOF_INPUT;
  158. }
  159. static int nx_gpio_probe(struct udevice *dev)
  160. {
  161. struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
  162. struct nx_gpio_plat *plat = dev_get_plat(dev);
  163. uc_priv->gpio_count = plat->gpio_count;
  164. uc_priv->bank_name = plat->bank_name;
  165. return 0;
  166. }
  167. static int nx_gpio_of_to_plat(struct udevice *dev)
  168. {
  169. struct nx_gpio_plat *plat = dev_get_plat(dev);
  170. plat->regs = map_physmem(devfdt_get_addr(dev),
  171. sizeof(struct nx_gpio_regs),
  172. MAP_NOCACHE);
  173. plat->gpio_count = dev_read_s32_default(dev, "nexell,gpio-bank-width",
  174. 32);
  175. plat->bank_name = dev_read_string(dev, "gpio-bank-name");
  176. return 0;
  177. }
  178. static const struct dm_gpio_ops nx_gpio_ops = {
  179. .direction_input = nx_gpio_direction_input,
  180. .direction_output = nx_gpio_direction_output,
  181. .get_value = nx_gpio_get_value,
  182. .set_value = nx_gpio_set_value,
  183. .get_function = nx_gpio_get_function,
  184. };
  185. static const struct udevice_id nx_gpio_ids[] = {
  186. { .compatible = "nexell,nexell-gpio" },
  187. { }
  188. };
  189. U_BOOT_DRIVER(nx_gpio) = {
  190. .name = "nx_gpio",
  191. .id = UCLASS_GPIO,
  192. .of_match = nx_gpio_ids,
  193. .ops = &nx_gpio_ops,
  194. .of_to_plat = nx_gpio_of_to_plat,
  195. .plat_auto = sizeof(struct nx_gpio_plat),
  196. .probe = nx_gpio_probe,
  197. };