mxc_gpio.c 9.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2009
  4. * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
  5. *
  6. * Copyright (C) 2011
  7. * Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
  8. */
  9. #include <common.h>
  10. #include <errno.h>
  11. #include <dm.h>
  12. #include <malloc.h>
  13. #include <asm/arch/imx-regs.h>
  14. #include <asm/gpio.h>
  15. #include <asm/io.h>
  16. #include <dt-structs.h>
  17. #include <mapmem.h>
  18. enum mxc_gpio_direction {
  19. MXC_GPIO_DIRECTION_IN,
  20. MXC_GPIO_DIRECTION_OUT,
  21. };
  22. #define GPIO_PER_BANK 32
  23. struct mxc_gpio_plat {
  24. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  25. /* Put this first since driver model will copy the data here */
  26. struct dtd_gpio_mxc dtplat;
  27. #endif
  28. int bank_index;
  29. struct gpio_regs *regs;
  30. };
  31. struct mxc_bank_info {
  32. struct gpio_regs *regs;
  33. };
  34. #if !CONFIG_IS_ENABLED(DM_GPIO)
  35. #define GPIO_TO_PORT(n) ((n) / 32)
  36. /* GPIO port description */
  37. static unsigned long gpio_ports[] = {
  38. [0] = GPIO1_BASE_ADDR,
  39. [1] = GPIO2_BASE_ADDR,
  40. [2] = GPIO3_BASE_ADDR,
  41. #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
  42. defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
  43. defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || \
  44. defined(CONFIG_ARCH_IMX8) || defined(CONFIG_IMXRT1050)
  45. [3] = GPIO4_BASE_ADDR,
  46. #endif
  47. #if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
  48. defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || \
  49. defined(CONFIG_ARCH_IMX8) || defined(CONFIG_IMXRT1050)
  50. [4] = GPIO5_BASE_ADDR,
  51. #if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
  52. defined(CONFIG_IMX8M) || defined(CONFIG_IMXRT1050))
  53. [5] = GPIO6_BASE_ADDR,
  54. #endif
  55. #endif
  56. #if defined(CONFIG_MX53) || defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
  57. defined(CONFIG_ARCH_IMX8)
  58. #if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
  59. [6] = GPIO7_BASE_ADDR,
  60. #endif
  61. #endif
  62. #if defined(CONFIG_ARCH_IMX8)
  63. [7] = GPIO8_BASE_ADDR,
  64. #endif
  65. };
  66. static int mxc_gpio_direction(unsigned int gpio,
  67. enum mxc_gpio_direction direction)
  68. {
  69. unsigned int port = GPIO_TO_PORT(gpio);
  70. struct gpio_regs *regs;
  71. u32 l;
  72. if (port >= ARRAY_SIZE(gpio_ports))
  73. return -1;
  74. gpio &= 0x1f;
  75. regs = (struct gpio_regs *)gpio_ports[port];
  76. l = readl(&regs->gpio_dir);
  77. switch (direction) {
  78. case MXC_GPIO_DIRECTION_OUT:
  79. l |= 1 << gpio;
  80. break;
  81. case MXC_GPIO_DIRECTION_IN:
  82. l &= ~(1 << gpio);
  83. }
  84. writel(l, &regs->gpio_dir);
  85. return 0;
  86. }
  87. int gpio_set_value(unsigned gpio, int value)
  88. {
  89. unsigned int port = GPIO_TO_PORT(gpio);
  90. struct gpio_regs *regs;
  91. u32 l;
  92. if (port >= ARRAY_SIZE(gpio_ports))
  93. return -1;
  94. gpio &= 0x1f;
  95. regs = (struct gpio_regs *)gpio_ports[port];
  96. l = readl(&regs->gpio_dr);
  97. if (value)
  98. l |= 1 << gpio;
  99. else
  100. l &= ~(1 << gpio);
  101. writel(l, &regs->gpio_dr);
  102. return 0;
  103. }
  104. int gpio_get_value(unsigned gpio)
  105. {
  106. unsigned int port = GPIO_TO_PORT(gpio);
  107. struct gpio_regs *regs;
  108. u32 val;
  109. if (port >= ARRAY_SIZE(gpio_ports))
  110. return -1;
  111. gpio &= 0x1f;
  112. regs = (struct gpio_regs *)gpio_ports[port];
  113. val = (readl(&regs->gpio_psr) >> gpio) & 0x01;
  114. return val;
  115. }
  116. int gpio_request(unsigned gpio, const char *label)
  117. {
  118. unsigned int port = GPIO_TO_PORT(gpio);
  119. if (port >= ARRAY_SIZE(gpio_ports))
  120. return -1;
  121. return 0;
  122. }
  123. int gpio_free(unsigned gpio)
  124. {
  125. return 0;
  126. }
  127. int gpio_direction_input(unsigned gpio)
  128. {
  129. return mxc_gpio_direction(gpio, MXC_GPIO_DIRECTION_IN);
  130. }
  131. int gpio_direction_output(unsigned gpio, int value)
  132. {
  133. int ret = gpio_set_value(gpio, value);
  134. if (ret < 0)
  135. return ret;
  136. return mxc_gpio_direction(gpio, MXC_GPIO_DIRECTION_OUT);
  137. }
  138. #endif
  139. #if CONFIG_IS_ENABLED(DM_GPIO)
  140. #include <fdtdec.h>
  141. static int mxc_gpio_is_output(struct gpio_regs *regs, int offset)
  142. {
  143. u32 val;
  144. val = readl(&regs->gpio_dir);
  145. return val & (1 << offset) ? 1 : 0;
  146. }
  147. static void mxc_gpio_bank_direction(struct gpio_regs *regs, int offset,
  148. enum mxc_gpio_direction direction)
  149. {
  150. u32 l;
  151. l = readl(&regs->gpio_dir);
  152. switch (direction) {
  153. case MXC_GPIO_DIRECTION_OUT:
  154. l |= 1 << offset;
  155. break;
  156. case MXC_GPIO_DIRECTION_IN:
  157. l &= ~(1 << offset);
  158. }
  159. writel(l, &regs->gpio_dir);
  160. }
  161. static void mxc_gpio_bank_set_value(struct gpio_regs *regs, int offset,
  162. int value)
  163. {
  164. u32 l;
  165. l = readl(&regs->gpio_dr);
  166. if (value)
  167. l |= 1 << offset;
  168. else
  169. l &= ~(1 << offset);
  170. writel(l, &regs->gpio_dr);
  171. }
  172. static int mxc_gpio_bank_get_value(struct gpio_regs *regs, int offset)
  173. {
  174. return (readl(&regs->gpio_psr) >> offset) & 0x01;
  175. }
  176. /* set GPIO pin 'gpio' as an input */
  177. static int mxc_gpio_direction_input(struct udevice *dev, unsigned offset)
  178. {
  179. struct mxc_bank_info *bank = dev_get_priv(dev);
  180. /* Configure GPIO direction as input. */
  181. mxc_gpio_bank_direction(bank->regs, offset, MXC_GPIO_DIRECTION_IN);
  182. return 0;
  183. }
  184. /* set GPIO pin 'gpio' as an output, with polarity 'value' */
  185. static int mxc_gpio_direction_output(struct udevice *dev, unsigned offset,
  186. int value)
  187. {
  188. struct mxc_bank_info *bank = dev_get_priv(dev);
  189. /* Configure GPIO output value. */
  190. mxc_gpio_bank_set_value(bank->regs, offset, value);
  191. /* Configure GPIO direction as output. */
  192. mxc_gpio_bank_direction(bank->regs, offset, MXC_GPIO_DIRECTION_OUT);
  193. return 0;
  194. }
  195. /* read GPIO IN value of pin 'gpio' */
  196. static int mxc_gpio_get_value(struct udevice *dev, unsigned offset)
  197. {
  198. struct mxc_bank_info *bank = dev_get_priv(dev);
  199. return mxc_gpio_bank_get_value(bank->regs, offset);
  200. }
  201. /* write GPIO OUT value to pin 'gpio' */
  202. static int mxc_gpio_set_value(struct udevice *dev, unsigned offset,
  203. int value)
  204. {
  205. struct mxc_bank_info *bank = dev_get_priv(dev);
  206. mxc_gpio_bank_set_value(bank->regs, offset, value);
  207. return 0;
  208. }
  209. static int mxc_gpio_get_function(struct udevice *dev, unsigned offset)
  210. {
  211. struct mxc_bank_info *bank = dev_get_priv(dev);
  212. /* GPIOF_FUNC is not implemented yet */
  213. if (mxc_gpio_is_output(bank->regs, offset))
  214. return GPIOF_OUTPUT;
  215. else
  216. return GPIOF_INPUT;
  217. }
  218. static const struct dm_gpio_ops gpio_mxc_ops = {
  219. .direction_input = mxc_gpio_direction_input,
  220. .direction_output = mxc_gpio_direction_output,
  221. .get_value = mxc_gpio_get_value,
  222. .set_value = mxc_gpio_set_value,
  223. .get_function = mxc_gpio_get_function,
  224. };
  225. static int mxc_gpio_probe(struct udevice *dev)
  226. {
  227. struct mxc_bank_info *bank = dev_get_priv(dev);
  228. struct mxc_gpio_plat *plat = dev_get_plat(dev);
  229. struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
  230. int banknum;
  231. char name[18], *str;
  232. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  233. struct dtd_gpio_mxc *dtplat = &plat->dtplat;
  234. plat->regs = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
  235. #endif
  236. banknum = plat->bank_index;
  237. if (IS_ENABLED(CONFIG_ARCH_IMX8))
  238. sprintf(name, "GPIO%d_", banknum);
  239. else
  240. sprintf(name, "GPIO%d_", banknum + 1);
  241. str = strdup(name);
  242. if (!str)
  243. return -ENOMEM;
  244. uc_priv->bank_name = str;
  245. uc_priv->gpio_count = GPIO_PER_BANK;
  246. bank->regs = plat->regs;
  247. return 0;
  248. }
  249. static int mxc_gpio_of_to_plat(struct udevice *dev)
  250. {
  251. struct mxc_gpio_plat *plat = dev_get_plat(dev);
  252. if (!CONFIG_IS_ENABLED(OF_PLATDATA)) {
  253. fdt_addr_t addr;
  254. addr = dev_read_addr(dev);
  255. if (addr == FDT_ADDR_T_NONE)
  256. return -EINVAL;
  257. plat->regs = (struct gpio_regs *)addr;
  258. }
  259. plat->bank_index = dev_seq(dev);
  260. return 0;
  261. }
  262. static int mxc_gpio_bind(struct udevice *dev)
  263. {
  264. return 0;
  265. }
  266. static const struct udevice_id mxc_gpio_ids[] = {
  267. { .compatible = "fsl,imx35-gpio" },
  268. { }
  269. };
  270. U_BOOT_DRIVER(gpio_mxc) = {
  271. .name = "gpio_mxc",
  272. .id = UCLASS_GPIO,
  273. .ops = &gpio_mxc_ops,
  274. .probe = mxc_gpio_probe,
  275. .of_to_plat = mxc_gpio_of_to_plat,
  276. .plat_auto = sizeof(struct mxc_gpio_plat),
  277. .priv_auto = sizeof(struct mxc_bank_info),
  278. .of_match = mxc_gpio_ids,
  279. .bind = mxc_gpio_bind,
  280. };
  281. DM_DRIVER_ALIAS(gpio_mxc, fsl_imx6q_gpio)
  282. #if !CONFIG_IS_ENABLED(OF_CONTROL)
  283. static const struct mxc_gpio_plat mxc_plat[] = {
  284. { 0, (struct gpio_regs *)GPIO1_BASE_ADDR },
  285. { 1, (struct gpio_regs *)GPIO2_BASE_ADDR },
  286. { 2, (struct gpio_regs *)GPIO3_BASE_ADDR },
  287. #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
  288. defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
  289. defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8)
  290. { 3, (struct gpio_regs *)GPIO4_BASE_ADDR },
  291. #endif
  292. #if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
  293. defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8)
  294. { 4, (struct gpio_regs *)GPIO5_BASE_ADDR },
  295. #ifndef CONFIG_IMX8M
  296. { 5, (struct gpio_regs *)GPIO6_BASE_ADDR },
  297. #endif
  298. #endif
  299. #if defined(CONFIG_MX53) || defined(CONFIG_MX6) || defined(CONFIG_ARCH_IMX8)
  300. { 6, (struct gpio_regs *)GPIO7_BASE_ADDR },
  301. #endif
  302. #if defined(CONFIG_ARCH_IMX8)
  303. { 7, (struct gpio_regs *)GPIO8_BASE_ADDR },
  304. #endif
  305. };
  306. U_BOOT_DRVINFOS(mxc_gpios) = {
  307. { "gpio_mxc", &mxc_plat[0] },
  308. { "gpio_mxc", &mxc_plat[1] },
  309. { "gpio_mxc", &mxc_plat[2] },
  310. #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
  311. defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
  312. defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8)
  313. { "gpio_mxc", &mxc_plat[3] },
  314. #endif
  315. #if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
  316. defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8)
  317. { "gpio_mxc", &mxc_plat[4] },
  318. #ifndef CONFIG_IMX8M
  319. { "gpio_mxc", &mxc_plat[5] },
  320. #endif
  321. #endif
  322. #if defined(CONFIG_MX53) || defined(CONFIG_MX6) || defined(CONFIG_ARCH_IMX8)
  323. { "gpio_mxc", &mxc_plat[6] },
  324. #endif
  325. #if defined(CONFIG_ARCH_IMX8)
  326. { "gpio_mxc", &mxc_plat[7] },
  327. #endif
  328. };
  329. #endif
  330. #endif