mpc8xxx_gpio.c 6.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2016
  4. * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
  5. *
  6. * based on arch/powerpc/include/asm/mpc85xx_gpio.h, which is
  7. *
  8. * Copyright 2010 eXMeritus, A Boeing Company
  9. * Copyright 2020-2021 NXP
  10. */
  11. #include <common.h>
  12. #include <dm.h>
  13. #include <mapmem.h>
  14. #include <asm/gpio.h>
  15. #include <asm/io.h>
  16. #include <dm/of_access.h>
  17. struct mpc8xxx_gpio_data {
  18. /* The bank's register base in memory */
  19. struct ccsr_gpio __iomem *base;
  20. /* The address of the registers; used to identify the bank */
  21. phys_addr_t addr;
  22. /* The GPIO count of the bank */
  23. uint gpio_count;
  24. /* The GPDAT register cannot be used to determine the value of output
  25. * pins on MPC8572/MPC8536, so we shadow it and use the shadowed value
  26. * for output pins
  27. */
  28. u32 dat_shadow;
  29. ulong type;
  30. bool little_endian;
  31. };
  32. enum {
  33. MPC8XXX_GPIO_TYPE,
  34. MPC5121_GPIO_TYPE,
  35. };
  36. inline u32 gpio_mask(uint gpio)
  37. {
  38. return (1U << (31 - (gpio)));
  39. }
  40. static inline u32 mpc8xxx_gpio_get_val(struct udevice *dev, u32 mask)
  41. {
  42. struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
  43. if (data->little_endian)
  44. return in_le32(&data->base->gpdat) & mask;
  45. else
  46. return in_be32(&data->base->gpdat) & mask;
  47. }
  48. static inline u32 mpc8xxx_gpio_get_dir(struct udevice *dev, u32 mask)
  49. {
  50. struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
  51. if (data->little_endian)
  52. return in_le32(&data->base->gpdir) & mask;
  53. else
  54. return in_be32(&data->base->gpdir) & mask;
  55. }
  56. static inline int mpc8xxx_gpio_open_drain_val(struct udevice *dev, u32 mask)
  57. {
  58. struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
  59. if (data->little_endian)
  60. return in_le32(&data->base->gpodr) & mask;
  61. else
  62. return in_be32(&data->base->gpodr) & mask;
  63. }
  64. static inline void mpc8xxx_gpio_open_drain_on(struct udevice *dev, u32
  65. gpios)
  66. {
  67. struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
  68. /* GPODR register 1 -> open drain on */
  69. if (data->little_endian)
  70. setbits_le32(&data->base->gpodr, gpios);
  71. else
  72. setbits_be32(&data->base->gpodr, gpios);
  73. }
  74. static inline void mpc8xxx_gpio_open_drain_off(struct udevice *dev,
  75. u32 gpios)
  76. {
  77. struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
  78. /* GPODR register 0 -> open drain off (actively driven) */
  79. if (data->little_endian)
  80. clrbits_le32(&data->base->gpodr, gpios);
  81. else
  82. clrbits_be32(&data->base->gpodr, gpios);
  83. }
  84. static int mpc8xxx_gpio_direction_input(struct udevice *dev, uint gpio)
  85. {
  86. struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
  87. u32 mask = gpio_mask(gpio);
  88. /* GPDIR register 0 -> input */
  89. if (data->little_endian)
  90. clrbits_le32(&data->base->gpdir, mask);
  91. else
  92. clrbits_be32(&data->base->gpdir, mask);
  93. return 0;
  94. }
  95. static int mpc8xxx_gpio_set_value(struct udevice *dev, uint gpio, int value)
  96. {
  97. struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
  98. struct ccsr_gpio *base = data->base;
  99. u32 mask = gpio_mask(gpio);
  100. u32 gpdir;
  101. if (value) {
  102. data->dat_shadow |= mask;
  103. } else {
  104. data->dat_shadow &= ~mask;
  105. }
  106. if (data->little_endian)
  107. gpdir = in_le32(&base->gpdir);
  108. else
  109. gpdir = in_be32(&base->gpdir);
  110. gpdir |= gpio_mask(gpio);
  111. if (data->little_endian) {
  112. out_le32(&base->gpdat, gpdir & data->dat_shadow);
  113. out_le32(&base->gpdir, gpdir);
  114. } else {
  115. out_be32(&base->gpdat, gpdir & data->dat_shadow);
  116. out_be32(&base->gpdir, gpdir);
  117. }
  118. return 0;
  119. }
  120. static int mpc8xxx_gpio_direction_output(struct udevice *dev, uint gpio,
  121. int value)
  122. {
  123. struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
  124. /* GPIO 28..31 are input only on MPC5121 */
  125. if (data->type == MPC5121_GPIO_TYPE && gpio >= 28)
  126. return -EINVAL;
  127. return mpc8xxx_gpio_set_value(dev, gpio, value);
  128. }
  129. static int mpc8xxx_gpio_get_value(struct udevice *dev, uint gpio)
  130. {
  131. struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
  132. if (!!mpc8xxx_gpio_get_dir(dev, gpio_mask(gpio))) {
  133. /* Output -> use shadowed value */
  134. return !!(data->dat_shadow & gpio_mask(gpio));
  135. }
  136. /* Input -> read value from GPDAT register */
  137. return !!mpc8xxx_gpio_get_val(dev, gpio_mask(gpio));
  138. }
  139. static int mpc8xxx_gpio_get_function(struct udevice *dev, uint gpio)
  140. {
  141. int dir;
  142. dir = !!mpc8xxx_gpio_get_dir(dev, gpio_mask(gpio));
  143. return dir ? GPIOF_OUTPUT : GPIOF_INPUT;
  144. }
  145. #if CONFIG_IS_ENABLED(OF_CONTROL)
  146. static int mpc8xxx_gpio_of_to_plat(struct udevice *dev)
  147. {
  148. struct mpc8xxx_gpio_plat *plat = dev_get_plat(dev);
  149. struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
  150. if (dev_read_bool(dev, "little-endian"))
  151. data->little_endian = true;
  152. plat->addr = dev_read_addr_size_index(dev, 0, (fdt_size_t *)&plat->size);
  153. plat->ngpios = dev_read_u32_default(dev, "ngpios", 32);
  154. return 0;
  155. }
  156. #endif
  157. static int mpc8xxx_gpio_plat_to_priv(struct udevice *dev)
  158. {
  159. struct mpc8xxx_gpio_data *priv = dev_get_priv(dev);
  160. struct mpc8xxx_gpio_plat *plat = dev_get_plat(dev);
  161. unsigned long size = plat->size;
  162. ulong driver_data = dev_get_driver_data(dev);
  163. if (size == 0)
  164. size = 0x100;
  165. priv->addr = plat->addr;
  166. priv->base = map_sysmem(plat->addr, size);
  167. if (!priv->base)
  168. return -ENOMEM;
  169. priv->gpio_count = plat->ngpios;
  170. priv->dat_shadow = 0;
  171. priv->type = driver_data;
  172. return 0;
  173. }
  174. static int mpc8xxx_gpio_probe(struct udevice *dev)
  175. {
  176. struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
  177. struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
  178. char name[32], *str;
  179. mpc8xxx_gpio_plat_to_priv(dev);
  180. snprintf(name, sizeof(name), "MPC@%.8llx",
  181. (unsigned long long)data->addr);
  182. str = strdup(name);
  183. if (!str)
  184. return -ENOMEM;
  185. if (device_is_compatible(dev, "fsl,qoriq-gpio")) {
  186. if (data->little_endian)
  187. out_le32(&data->base->gpibe, 0xffffffff);
  188. else
  189. out_be32(&data->base->gpibe, 0xffffffff);
  190. }
  191. uc_priv->bank_name = str;
  192. uc_priv->gpio_count = data->gpio_count;
  193. return 0;
  194. }
  195. static const struct dm_gpio_ops gpio_mpc8xxx_ops = {
  196. .direction_input = mpc8xxx_gpio_direction_input,
  197. .direction_output = mpc8xxx_gpio_direction_output,
  198. .get_value = mpc8xxx_gpio_get_value,
  199. .set_value = mpc8xxx_gpio_set_value,
  200. .get_function = mpc8xxx_gpio_get_function,
  201. };
  202. static const struct udevice_id mpc8xxx_gpio_ids[] = {
  203. { .compatible = "fsl,pq3-gpio", .data = MPC8XXX_GPIO_TYPE },
  204. { .compatible = "fsl,mpc8308-gpio", .data = MPC8XXX_GPIO_TYPE },
  205. { .compatible = "fsl,mpc8349-gpio", .data = MPC8XXX_GPIO_TYPE },
  206. { .compatible = "fsl,mpc8572-gpio", .data = MPC8XXX_GPIO_TYPE},
  207. { .compatible = "fsl,mpc8610-gpio", .data = MPC8XXX_GPIO_TYPE},
  208. { .compatible = "fsl,mpc5121-gpio", .data = MPC5121_GPIO_TYPE, },
  209. { .compatible = "fsl,qoriq-gpio", .data = MPC8XXX_GPIO_TYPE },
  210. { /* sentinel */ }
  211. };
  212. U_BOOT_DRIVER(gpio_mpc8xxx) = {
  213. .name = "gpio_mpc8xxx",
  214. .id = UCLASS_GPIO,
  215. .ops = &gpio_mpc8xxx_ops,
  216. #if CONFIG_IS_ENABLED(OF_CONTROL)
  217. .of_to_plat = mpc8xxx_gpio_of_to_plat,
  218. .plat_auto = sizeof(struct mpc8xxx_gpio_plat),
  219. .of_match = mpc8xxx_gpio_ids,
  220. #endif
  221. .probe = mpc8xxx_gpio_probe,
  222. .priv_auto = sizeof(struct mpc8xxx_gpio_data),
  223. };