intel_gpio.c 5.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2019 Google LLC
  4. */
  5. #define LOG_CATEGORY UCLASS_GPIO
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <errno.h>
  9. #include <fdtdec.h>
  10. #include <log.h>
  11. #include <p2sb.h>
  12. #include <pch.h>
  13. #include <pci.h>
  14. #include <syscon.h>
  15. #include <acpi/acpi_device.h>
  16. #include <asm/cpu.h>
  17. #include <asm/gpio.h>
  18. #include <asm/intel_pinctrl.h>
  19. #include <asm/intel_pinctrl_defs.h>
  20. #include <asm/io.h>
  21. #include <asm/pci.h>
  22. #include <asm/arch/gpio.h>
  23. #include <dm/acpi.h>
  24. #include <dm/device-internal.h>
  25. #include <dt-bindings/gpio/x86-gpio.h>
  26. static int intel_gpio_get_value(struct udevice *dev, uint offset)
  27. {
  28. struct udevice *pinctrl = dev_get_parent(dev);
  29. uint mode, rx_tx;
  30. u32 reg;
  31. reg = intel_pinctrl_get_config_reg(pinctrl, offset);
  32. mode = (reg & PAD_CFG0_MODE_MASK) >> PAD_CFG0_MODE_SHIFT;
  33. if (!mode) {
  34. rx_tx = reg & (PAD_CFG0_TX_DISABLE | PAD_CFG0_RX_DISABLE);
  35. if (rx_tx == PAD_CFG0_TX_DISABLE)
  36. return reg & PAD_CFG0_RX_STATE ? 1 : 0;
  37. else if (rx_tx == PAD_CFG0_RX_DISABLE)
  38. return reg & PAD_CFG0_TX_STATE ? 1 : 0;
  39. }
  40. return 0;
  41. }
  42. static int intel_gpio_set_value(struct udevice *dev, unsigned int offset,
  43. int value)
  44. {
  45. struct udevice *pinctrl = dev_get_parent(dev);
  46. uint config_offset;
  47. config_offset = intel_pinctrl_get_config_reg_offset(pinctrl, offset);
  48. pcr_clrsetbits32(pinctrl, config_offset, PAD_CFG0_TX_STATE,
  49. value ? PAD_CFG0_TX_STATE : 0);
  50. return 0;
  51. }
  52. static int intel_gpio_get_function(struct udevice *dev, uint offset)
  53. {
  54. struct udevice *pinctrl = dev_get_parent(dev);
  55. uint mode, rx_tx;
  56. u32 reg;
  57. reg = intel_pinctrl_get_config_reg(pinctrl, offset);
  58. mode = (reg & PAD_CFG0_MODE_MASK) >> PAD_CFG0_MODE_SHIFT;
  59. if (!mode) {
  60. rx_tx = reg & (PAD_CFG0_TX_DISABLE | PAD_CFG0_RX_DISABLE);
  61. if (rx_tx == PAD_CFG0_TX_DISABLE)
  62. return GPIOF_INPUT;
  63. else if (rx_tx == PAD_CFG0_RX_DISABLE)
  64. return GPIOF_OUTPUT;
  65. }
  66. return GPIOF_FUNC;
  67. }
  68. static int intel_gpio_xlate(struct udevice *orig_dev, struct gpio_desc *desc,
  69. struct ofnode_phandle_args *args)
  70. {
  71. struct udevice *pinctrl, *dev;
  72. int gpio, ret;
  73. /*
  74. * GPIO numbers are global in the device tree so it doesn't matter
  75. * which @orig_dev is used
  76. */
  77. gpio = args->args[0];
  78. ret = intel_pinctrl_get_pad(gpio, &pinctrl, &desc->offset);
  79. if (ret)
  80. return log_msg_ret("bad", ret);
  81. device_find_first_child(pinctrl, &dev);
  82. if (!dev)
  83. return log_msg_ret("no child", -ENOENT);
  84. desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
  85. desc->dev = dev;
  86. /*
  87. * Handle the case where the wrong GPIO device was provided, since this
  88. * will not have been probed by the GPIO uclass before calling here
  89. * (see gpio_request_tail()).
  90. */
  91. if (orig_dev != dev) {
  92. ret = device_probe(dev);
  93. if (ret)
  94. return log_msg_ret("probe", ret);
  95. }
  96. return 0;
  97. }
  98. static int intel_gpio_set_flags(struct udevice *dev, unsigned int offset,
  99. ulong flags)
  100. {
  101. struct udevice *pinctrl = dev_get_parent(dev);
  102. u32 bic0 = 0, bic1 = 0;
  103. u32 or0, or1;
  104. uint config_offset;
  105. config_offset = intel_pinctrl_get_config_reg_offset(pinctrl, offset);
  106. if (flags & GPIOD_IS_OUT) {
  107. bic0 |= PAD_CFG0_MODE_MASK | PAD_CFG0_RX_STATE |
  108. PAD_CFG0_TX_DISABLE;
  109. or0 |= PAD_CFG0_MODE_GPIO | PAD_CFG0_RX_DISABLE;
  110. } else if (flags & GPIOD_IS_IN) {
  111. bic0 |= PAD_CFG0_MODE_MASK | PAD_CFG0_TX_STATE |
  112. PAD_CFG0_RX_DISABLE;
  113. or0 |= PAD_CFG0_MODE_GPIO | PAD_CFG0_TX_DISABLE;
  114. }
  115. if (flags & GPIOD_PULL_UP) {
  116. bic1 |= PAD_CFG1_PULL_MASK;
  117. or1 |= PAD_CFG1_PULL_UP_20K;
  118. } else if (flags & GPIOD_PULL_DOWN) {
  119. bic1 |= PAD_CFG1_PULL_MASK;
  120. or1 |= PAD_CFG1_PULL_DN_20K;
  121. }
  122. pcr_clrsetbits32(pinctrl, PAD_CFG0_OFFSET(config_offset), bic0, or0);
  123. pcr_clrsetbits32(pinctrl, PAD_CFG1_OFFSET(config_offset), bic1, or1);
  124. log_debug("%s: flags=%lx, offset=%x, config_offset=%x, %x/%x %x/%x\n",
  125. dev->name, flags, offset, config_offset, bic0, or0, bic1, or1);
  126. return 0;
  127. }
  128. #if CONFIG_IS_ENABLED(ACPIGEN)
  129. static int intel_gpio_get_acpi(const struct gpio_desc *desc,
  130. struct acpi_gpio *gpio)
  131. {
  132. struct udevice *pinctrl;
  133. int ret;
  134. if (!dm_gpio_is_valid(desc))
  135. return -ENOENT;
  136. pinctrl = dev_get_parent(desc->dev);
  137. memset(gpio, '\0', sizeof(*gpio));
  138. gpio->type = ACPI_GPIO_TYPE_IO;
  139. gpio->pull = ACPI_GPIO_PULL_DEFAULT;
  140. gpio->io_restrict = ACPI_GPIO_IO_RESTRICT_OUTPUT;
  141. gpio->polarity = ACPI_GPIO_ACTIVE_HIGH;
  142. gpio->pin_count = 1;
  143. gpio->pins[0] = intel_pinctrl_get_acpi_pin(pinctrl, desc->offset);
  144. gpio->pin0_addr = intel_pinctrl_get_config_reg_addr(pinctrl,
  145. desc->offset);
  146. ret = acpi_get_path(pinctrl, gpio->resource, sizeof(gpio->resource));
  147. if (ret)
  148. return log_msg_ret("resource", ret);
  149. return 0;
  150. }
  151. #endif
  152. static int intel_gpio_probe(struct udevice *dev)
  153. {
  154. return 0;
  155. }
  156. static int intel_gpio_of_to_plat(struct udevice *dev)
  157. {
  158. struct gpio_dev_priv *upriv = dev_get_uclass_priv(dev);
  159. struct intel_pinctrl_priv *pinctrl_priv = dev_get_priv(dev->parent);
  160. const struct pad_community *comm = pinctrl_priv->comm;
  161. upriv->gpio_count = comm->last_pad - comm->first_pad + 1;
  162. upriv->bank_name = dev->name;
  163. return 0;
  164. }
  165. static const struct dm_gpio_ops gpio_intel_ops = {
  166. .get_value = intel_gpio_get_value,
  167. .set_value = intel_gpio_set_value,
  168. .get_function = intel_gpio_get_function,
  169. .xlate = intel_gpio_xlate,
  170. .set_flags = intel_gpio_set_flags,
  171. #if CONFIG_IS_ENABLED(ACPIGEN)
  172. .get_acpi = intel_gpio_get_acpi,
  173. #endif
  174. };
  175. #if !CONFIG_IS_ENABLED(OF_PLATDATA)
  176. static const struct udevice_id intel_intel_gpio_ids[] = {
  177. { .compatible = "intel,gpio" },
  178. { }
  179. };
  180. #endif
  181. U_BOOT_DRIVER(intel_gpio) = {
  182. .name = "intel_gpio",
  183. .id = UCLASS_GPIO,
  184. .of_match = of_match_ptr(intel_intel_gpio_ids),
  185. .ops = &gpio_intel_ops,
  186. .of_to_plat = intel_gpio_of_to_plat,
  187. .probe = intel_gpio_probe,
  188. };