gpio-uniphier.c 4.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016-2017 Socionext Inc.
  4. * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  5. */
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <linux/bitops.h>
  9. #include <linux/io.h>
  10. #include <linux/sizes.h>
  11. #include <linux/errno.h>
  12. #include <asm/global_data.h>
  13. #include <asm/gpio.h>
  14. #include <dt-bindings/gpio/uniphier-gpio.h>
  15. #define UNIPHIER_GPIO_PORT_DATA 0x0 /* data */
  16. #define UNIPHIER_GPIO_PORT_DIR 0x4 /* direction (1:in, 0:out) */
  17. #define UNIPHIER_GPIO_IRQ_EN 0x90 /* irq enable */
  18. struct uniphier_gpio_priv {
  19. void __iomem *regs;
  20. };
  21. static unsigned int uniphier_gpio_bank_to_reg(unsigned int bank)
  22. {
  23. unsigned int reg;
  24. reg = (bank + 1) * 8;
  25. /*
  26. * Unfortunately, the GPIO port registers are not contiguous because
  27. * offset 0x90-0x9f is used for IRQ. Add 0x10 when crossing the region.
  28. */
  29. if (reg >= UNIPHIER_GPIO_IRQ_EN)
  30. reg += 0x10;
  31. return reg;
  32. }
  33. static void uniphier_gpio_get_bank_and_mask(unsigned int offset,
  34. unsigned int *bank, u32 *mask)
  35. {
  36. *bank = offset / UNIPHIER_GPIO_LINES_PER_BANK;
  37. *mask = BIT(offset % UNIPHIER_GPIO_LINES_PER_BANK);
  38. }
  39. static void uniphier_gpio_reg_update(struct uniphier_gpio_priv *priv,
  40. unsigned int reg, u32 mask, u32 val)
  41. {
  42. u32 tmp;
  43. tmp = readl(priv->regs + reg);
  44. tmp &= ~mask;
  45. tmp |= mask & val;
  46. writel(tmp, priv->regs + reg);
  47. }
  48. static void uniphier_gpio_bank_write(struct udevice *dev, unsigned int bank,
  49. unsigned int reg, u32 mask, u32 val)
  50. {
  51. struct uniphier_gpio_priv *priv = dev_get_priv(dev);
  52. if (!mask)
  53. return;
  54. uniphier_gpio_reg_update(priv, uniphier_gpio_bank_to_reg(bank) + reg,
  55. mask, val);
  56. }
  57. static void uniphier_gpio_offset_write(struct udevice *dev, unsigned int offset,
  58. unsigned int reg, int val)
  59. {
  60. unsigned int bank;
  61. u32 mask;
  62. uniphier_gpio_get_bank_and_mask(offset, &bank, &mask);
  63. uniphier_gpio_bank_write(dev, bank, reg, mask, val ? mask : 0);
  64. }
  65. static int uniphier_gpio_offset_read(struct udevice *dev,
  66. unsigned int offset, unsigned int reg)
  67. {
  68. struct uniphier_gpio_priv *priv = dev_get_priv(dev);
  69. unsigned int bank, reg_offset;
  70. u32 mask;
  71. uniphier_gpio_get_bank_and_mask(offset, &bank, &mask);
  72. reg_offset = uniphier_gpio_bank_to_reg(bank) + reg;
  73. return !!(readl(priv->regs + reg_offset) & mask);
  74. }
  75. static int uniphier_gpio_get_function(struct udevice *dev, unsigned int offset)
  76. {
  77. return uniphier_gpio_offset_read(dev, offset, UNIPHIER_GPIO_PORT_DIR) ?
  78. GPIOF_INPUT : GPIOF_OUTPUT;
  79. }
  80. static int uniphier_gpio_direction_input(struct udevice *dev,
  81. unsigned int offset)
  82. {
  83. uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_PORT_DIR, 1);
  84. return 0;
  85. }
  86. static int uniphier_gpio_direction_output(struct udevice *dev,
  87. unsigned int offset, int value)
  88. {
  89. uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_PORT_DATA, value);
  90. uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_PORT_DIR, 0);
  91. return 0;
  92. }
  93. static int uniphier_gpio_get_value(struct udevice *dev, unsigned int offset)
  94. {
  95. return uniphier_gpio_offset_read(dev, offset, UNIPHIER_GPIO_PORT_DATA);
  96. }
  97. static int uniphier_gpio_set_value(struct udevice *dev,
  98. unsigned int offset, int value)
  99. {
  100. uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_PORT_DATA, value);
  101. return 0;
  102. }
  103. static const struct dm_gpio_ops uniphier_gpio_ops = {
  104. .direction_input = uniphier_gpio_direction_input,
  105. .direction_output = uniphier_gpio_direction_output,
  106. .get_value = uniphier_gpio_get_value,
  107. .set_value = uniphier_gpio_set_value,
  108. .get_function = uniphier_gpio_get_function,
  109. };
  110. static int uniphier_gpio_probe(struct udevice *dev)
  111. {
  112. struct uniphier_gpio_priv *priv = dev_get_priv(dev);
  113. struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
  114. fdt_addr_t addr;
  115. addr = dev_read_addr(dev);
  116. if (addr == FDT_ADDR_T_NONE)
  117. return -EINVAL;
  118. priv->regs = devm_ioremap(dev, addr, SZ_512);
  119. if (!priv->regs)
  120. return -ENOMEM;
  121. uc_priv->gpio_count = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
  122. "ngpios", 0);
  123. return 0;
  124. }
  125. static const struct udevice_id uniphier_gpio_match[] = {
  126. { .compatible = "socionext,uniphier-gpio" },
  127. { /* sentinel */ }
  128. };
  129. U_BOOT_DRIVER(uniphier_gpio) = {
  130. .name = "uniphier-gpio",
  131. .id = UCLASS_GPIO,
  132. .of_match = uniphier_gpio_match,
  133. .probe = uniphier_gpio_probe,
  134. .priv_auto = sizeof(struct uniphier_gpio_priv),
  135. .ops = &uniphier_gpio_ops,
  136. };