gpio-rcar.c 5.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
  4. */
  5. #include <common.h>
  6. #include <clk.h>
  7. #include <dm.h>
  8. #include <malloc.h>
  9. #include <asm/global_data.h>
  10. #include <dm/device_compat.h>
  11. #include <dm/pinctrl.h>
  12. #include <errno.h>
  13. #include <asm/gpio.h>
  14. #include <asm/io.h>
  15. #include <linux/bitops.h>
  16. #include "../pinctrl/renesas/sh_pfc.h"
  17. #define GPIO_IOINTSEL 0x00 /* General IO/Interrupt Switching Register */
  18. #define GPIO_INOUTSEL 0x04 /* General Input/Output Switching Register */
  19. #define GPIO_OUTDT 0x08 /* General Output Register */
  20. #define GPIO_INDT 0x0c /* General Input Register */
  21. #define GPIO_INTDT 0x10 /* Interrupt Display Register */
  22. #define GPIO_INTCLR 0x14 /* Interrupt Clear Register */
  23. #define GPIO_INTMSK 0x18 /* Interrupt Mask Register */
  24. #define GPIO_MSKCLR 0x1c /* Interrupt Mask Clear Register */
  25. #define GPIO_POSNEG 0x20 /* Positive/Negative Logic Select Register */
  26. #define GPIO_EDGLEVEL 0x24 /* Edge/level Select Register */
  27. #define GPIO_FILONOFF 0x28 /* Chattering Prevention On/Off Register */
  28. #define GPIO_BOTHEDGE 0x4c /* One Edge/Both Edge Select Register */
  29. #define GPIO_INEN 0x50 /* General Input Enable Register */
  30. #define RCAR_MAX_GPIO_PER_BANK 32
  31. #define RCAR_GPIO_HAS_INEN BIT(0)
  32. DECLARE_GLOBAL_DATA_PTR;
  33. struct rcar_gpio_priv {
  34. void __iomem *regs;
  35. u32 quirks;
  36. int pfc_offset;
  37. };
  38. static int rcar_gpio_get_value(struct udevice *dev, unsigned offset)
  39. {
  40. struct rcar_gpio_priv *priv = dev_get_priv(dev);
  41. const u32 bit = BIT(offset);
  42. /*
  43. * Testing on r8a7790 shows that INDT does not show correct pin state
  44. * when configured as output, so use OUTDT in case of output pins.
  45. */
  46. if (readl(priv->regs + GPIO_INOUTSEL) & bit)
  47. return !!(readl(priv->regs + GPIO_OUTDT) & bit);
  48. else
  49. return !!(readl(priv->regs + GPIO_INDT) & bit);
  50. }
  51. static int rcar_gpio_set_value(struct udevice *dev, unsigned offset,
  52. int value)
  53. {
  54. struct rcar_gpio_priv *priv = dev_get_priv(dev);
  55. if (value)
  56. setbits_le32(priv->regs + GPIO_OUTDT, BIT(offset));
  57. else
  58. clrbits_le32(priv->regs + GPIO_OUTDT, BIT(offset));
  59. return 0;
  60. }
  61. static void rcar_gpio_set_direction(struct udevice *dev, unsigned offset,
  62. bool output)
  63. {
  64. struct rcar_gpio_priv *priv = dev_get_priv(dev);
  65. void __iomem *regs = priv->regs;
  66. /*
  67. * follow steps in the GPIO documentation for
  68. * "Setting General Output Mode" and
  69. * "Setting General Input Mode"
  70. */
  71. /* Configure postive logic in POSNEG */
  72. clrbits_le32(regs + GPIO_POSNEG, BIT(offset));
  73. /* Select "Input Enable/Disable" in INEN */
  74. if (priv->quirks & RCAR_GPIO_HAS_INEN) {
  75. if (output)
  76. clrbits_le32(regs + GPIO_INEN, BIT(offset));
  77. else
  78. setbits_le32(regs + GPIO_INEN, BIT(offset));
  79. }
  80. /* Select "General Input/Output Mode" in IOINTSEL */
  81. clrbits_le32(regs + GPIO_IOINTSEL, BIT(offset));
  82. /* Select Input Mode or Output Mode in INOUTSEL */
  83. if (output)
  84. setbits_le32(regs + GPIO_INOUTSEL, BIT(offset));
  85. else
  86. clrbits_le32(regs + GPIO_INOUTSEL, BIT(offset));
  87. }
  88. static int rcar_gpio_direction_input(struct udevice *dev, unsigned offset)
  89. {
  90. rcar_gpio_set_direction(dev, offset, false);
  91. return 0;
  92. }
  93. static int rcar_gpio_direction_output(struct udevice *dev, unsigned offset,
  94. int value)
  95. {
  96. /* write GPIO value to output before selecting output mode of pin */
  97. rcar_gpio_set_value(dev, offset, value);
  98. rcar_gpio_set_direction(dev, offset, true);
  99. return 0;
  100. }
  101. static int rcar_gpio_get_function(struct udevice *dev, unsigned offset)
  102. {
  103. struct rcar_gpio_priv *priv = dev_get_priv(dev);
  104. if (readl(priv->regs + GPIO_INOUTSEL) & BIT(offset))
  105. return GPIOF_OUTPUT;
  106. else
  107. return GPIOF_INPUT;
  108. }
  109. static int rcar_gpio_request(struct udevice *dev, unsigned offset,
  110. const char *label)
  111. {
  112. return pinctrl_gpio_request(dev, offset);
  113. }
  114. static int rcar_gpio_free(struct udevice *dev, unsigned offset)
  115. {
  116. return pinctrl_gpio_free(dev, offset);
  117. }
  118. static const struct dm_gpio_ops rcar_gpio_ops = {
  119. .request = rcar_gpio_request,
  120. .rfree = rcar_gpio_free,
  121. .direction_input = rcar_gpio_direction_input,
  122. .direction_output = rcar_gpio_direction_output,
  123. .get_value = rcar_gpio_get_value,
  124. .set_value = rcar_gpio_set_value,
  125. .get_function = rcar_gpio_get_function,
  126. };
  127. static int rcar_gpio_probe(struct udevice *dev)
  128. {
  129. struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
  130. struct rcar_gpio_priv *priv = dev_get_priv(dev);
  131. struct fdtdec_phandle_args args;
  132. struct clk clk;
  133. int node = dev_of_offset(dev);
  134. int ret;
  135. priv->regs = dev_read_addr_ptr(dev);
  136. priv->quirks = dev_get_driver_data(dev);
  137. uc_priv->bank_name = dev->name;
  138. ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, node, "gpio-ranges",
  139. NULL, 3, 0, &args);
  140. priv->pfc_offset = ret == 0 ? args.args[1] : -1;
  141. uc_priv->gpio_count = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK;
  142. ret = clk_get_by_index(dev, 0, &clk);
  143. if (ret < 0) {
  144. dev_err(dev, "Failed to get GPIO bank clock\n");
  145. return ret;
  146. }
  147. ret = clk_enable(&clk);
  148. clk_free(&clk);
  149. if (ret) {
  150. dev_err(dev, "Failed to enable GPIO bank clock\n");
  151. return ret;
  152. }
  153. return 0;
  154. }
  155. static const struct udevice_id rcar_gpio_ids[] = {
  156. { .compatible = "renesas,gpio-r8a7795" },
  157. { .compatible = "renesas,gpio-r8a7796" },
  158. { .compatible = "renesas,gpio-r8a77965" },
  159. { .compatible = "renesas,gpio-r8a77970" },
  160. { .compatible = "renesas,gpio-r8a77990" },
  161. { .compatible = "renesas,gpio-r8a77995" },
  162. { .compatible = "renesas,gpio-r8a779a0", .data = RCAR_GPIO_HAS_INEN },
  163. { .compatible = "renesas,rcar-gen2-gpio" },
  164. { .compatible = "renesas,rcar-gen3-gpio" },
  165. { /* sentinel */ }
  166. };
  167. U_BOOT_DRIVER(rcar_gpio) = {
  168. .name = "rcar-gpio",
  169. .id = UCLASS_GPIO,
  170. .of_match = rcar_gpio_ids,
  171. .ops = &rcar_gpio_ops,
  172. .priv_auto = sizeof(struct rcar_gpio_priv),
  173. .probe = rcar_gpio_probe,
  174. };