cortina_gpio.c 2.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2020 Cortina-Access
  4. *
  5. * GPIO Driver for Cortina Access CAxxxx Line of SoCs
  6. */
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <log.h>
  10. #include <asm/io.h>
  11. #include <asm/gpio.h>
  12. #include <linux/bitops.h>
  13. #include <linux/compat.h>
  14. #include <linux/compiler.h>
  15. /* GPIO Register Map */
  16. #define CORTINA_GPIO_CFG 0x00
  17. #define CORTINA_GPIO_OUT 0x04
  18. #define CORTINA_GPIO_IN 0x08
  19. #define CORTINA_GPIO_LVL 0x0C
  20. #define CORTINA_GPIO_EDGE 0x10
  21. #define CORTINA_GPIO_BOTHEDGE 0x14
  22. #define CORTINA_GPIO_IE 0x18
  23. #define CORTINA_GPIO_INT 0x1C
  24. #define CORTINA_GPIO_STAT 0x20
  25. struct cortina_gpio_bank {
  26. void __iomem *base;
  27. };
  28. #ifdef CONFIG_DM_GPIO
  29. static int ca_gpio_direction_input(struct udevice *dev, unsigned int offset)
  30. {
  31. struct cortina_gpio_bank *priv = dev_get_priv(dev);
  32. setbits_32(priv->base, BIT(offset));
  33. return 0;
  34. }
  35. static int
  36. ca_gpio_direction_output(struct udevice *dev, unsigned int offset, int value)
  37. {
  38. struct cortina_gpio_bank *priv = dev_get_priv(dev);
  39. clrbits_32(priv->base, BIT(offset));
  40. return 0;
  41. }
  42. static int ca_gpio_get_value(struct udevice *dev, unsigned int offset)
  43. {
  44. struct cortina_gpio_bank *priv = dev_get_priv(dev);
  45. return readl(priv->base + CORTINA_GPIO_IN) & BIT(offset);
  46. }
  47. static int ca_gpio_set_value(struct udevice *dev, unsigned int offset,
  48. int value)
  49. {
  50. struct cortina_gpio_bank *priv = dev_get_priv(dev);
  51. setbits_32(priv->base + CORTINA_GPIO_OUT, BIT(offset));
  52. return 0;
  53. }
  54. static int ca_gpio_get_function(struct udevice *dev, unsigned int offset)
  55. {
  56. struct cortina_gpio_bank *priv = dev_get_priv(dev);
  57. if (readl(priv->base) & BIT(offset))
  58. return GPIOF_INPUT;
  59. else
  60. return GPIOF_OUTPUT;
  61. }
  62. static const struct dm_gpio_ops gpio_cortina_ops = {
  63. .direction_input = ca_gpio_direction_input,
  64. .direction_output = ca_gpio_direction_output,
  65. .get_value = ca_gpio_get_value,
  66. .set_value = ca_gpio_set_value,
  67. .get_function = ca_gpio_get_function,
  68. };
  69. static int ca_gpio_probe(struct udevice *dev)
  70. {
  71. struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
  72. struct cortina_gpio_bank *priv = dev_get_priv(dev);
  73. priv->base = dev_remap_addr_index(dev, 0);
  74. if (!priv->base)
  75. return -EINVAL;
  76. uc_priv->gpio_count = dev_read_u32_default(dev, "ngpios", 32);
  77. uc_priv->bank_name = dev->name;
  78. debug("Done Cortina GPIO init\n");
  79. return 0;
  80. }
  81. static const struct udevice_id ca_gpio_ids[] = {
  82. {.compatible = "cortina,ca-gpio"},
  83. {}
  84. };
  85. U_BOOT_DRIVER(cortina_gpio) = {
  86. .name = "cortina-gpio",
  87. .id = UCLASS_GPIO,
  88. .ops = &gpio_cortina_ops,
  89. .probe = ca_gpio_probe,
  90. .priv_auto = sizeof(struct cortina_gpio_bank),
  91. .of_match = ca_gpio_ids,
  92. };
  93. #endif /* CONFIG_DM_GPIO */