atmel_pio4.c 8.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Atmel PIO4 device driver
  4. *
  5. * Copyright (C) 2015 Atmel Corporation
  6. * Wenyou.Yang <wenyou.yang@atmel.com>
  7. */
  8. #include <common.h>
  9. #include <clk.h>
  10. #include <dm.h>
  11. #include <fdtdec.h>
  12. #include <malloc.h>
  13. #include <asm/arch/hardware.h>
  14. #include <asm/global_data.h>
  15. #include <asm/gpio.h>
  16. #include <linux/bitops.h>
  17. #include <mach/gpio.h>
  18. #include <mach/atmel_pio4.h>
  19. DECLARE_GLOBAL_DATA_PTR;
  20. static struct atmel_pio4_port *atmel_pio4_port_base(u32 port)
  21. {
  22. struct atmel_pio4_port *base = NULL;
  23. switch (port) {
  24. case AT91_PIO_PORTA:
  25. base = (struct atmel_pio4_port *)ATMEL_BASE_PIOA;
  26. break;
  27. case AT91_PIO_PORTB:
  28. base = (struct atmel_pio4_port *)ATMEL_BASE_PIOB;
  29. break;
  30. case AT91_PIO_PORTC:
  31. base = (struct atmel_pio4_port *)ATMEL_BASE_PIOC;
  32. break;
  33. case AT91_PIO_PORTD:
  34. base = (struct atmel_pio4_port *)ATMEL_BASE_PIOD;
  35. break;
  36. default:
  37. printf("Error: Atmel PIO4: Failed to get PIO base of port#%d!\n",
  38. port);
  39. break;
  40. }
  41. return base;
  42. }
  43. static int atmel_pio4_config_io_func(u32 port, u32 pin,
  44. u32 func, u32 config)
  45. {
  46. struct atmel_pio4_port *port_base;
  47. u32 reg, mask;
  48. if (pin >= ATMEL_PIO_NPINS_PER_BANK)
  49. return -EINVAL;
  50. port_base = atmel_pio4_port_base(port);
  51. if (!port_base)
  52. return -EINVAL;
  53. mask = 1 << pin;
  54. reg = func;
  55. reg |= config;
  56. writel(mask, &port_base->mskr);
  57. writel(reg, &port_base->cfgr);
  58. return 0;
  59. }
  60. int atmel_pio4_set_gpio(u32 port, u32 pin, u32 config)
  61. {
  62. return atmel_pio4_config_io_func(port, pin,
  63. ATMEL_PIO_CFGR_FUNC_GPIO,
  64. config);
  65. }
  66. int atmel_pio4_set_a_periph(u32 port, u32 pin, u32 config)
  67. {
  68. return atmel_pio4_config_io_func(port, pin,
  69. ATMEL_PIO_CFGR_FUNC_PERIPH_A,
  70. config);
  71. }
  72. int atmel_pio4_set_b_periph(u32 port, u32 pin, u32 config)
  73. {
  74. return atmel_pio4_config_io_func(port, pin,
  75. ATMEL_PIO_CFGR_FUNC_PERIPH_B,
  76. config);
  77. }
  78. int atmel_pio4_set_c_periph(u32 port, u32 pin, u32 config)
  79. {
  80. return atmel_pio4_config_io_func(port, pin,
  81. ATMEL_PIO_CFGR_FUNC_PERIPH_C,
  82. config);
  83. }
  84. int atmel_pio4_set_d_periph(u32 port, u32 pin, u32 config)
  85. {
  86. return atmel_pio4_config_io_func(port, pin,
  87. ATMEL_PIO_CFGR_FUNC_PERIPH_D,
  88. config);
  89. }
  90. int atmel_pio4_set_e_periph(u32 port, u32 pin, u32 config)
  91. {
  92. return atmel_pio4_config_io_func(port, pin,
  93. ATMEL_PIO_CFGR_FUNC_PERIPH_E,
  94. config);
  95. }
  96. int atmel_pio4_set_f_periph(u32 port, u32 pin, u32 config)
  97. {
  98. return atmel_pio4_config_io_func(port, pin,
  99. ATMEL_PIO_CFGR_FUNC_PERIPH_F,
  100. config);
  101. }
  102. int atmel_pio4_set_g_periph(u32 port, u32 pin, u32 config)
  103. {
  104. return atmel_pio4_config_io_func(port, pin,
  105. ATMEL_PIO_CFGR_FUNC_PERIPH_G,
  106. config);
  107. }
  108. int atmel_pio4_set_pio_output(u32 port, u32 pin, u32 value)
  109. {
  110. struct atmel_pio4_port *port_base;
  111. u32 reg, mask;
  112. if (pin >= ATMEL_PIO_NPINS_PER_BANK)
  113. return -EINVAL;
  114. port_base = atmel_pio4_port_base(port);
  115. if (!port_base)
  116. return -EINVAL;
  117. mask = 0x01 << pin;
  118. reg = ATMEL_PIO_CFGR_FUNC_GPIO | ATMEL_PIO_DIR_MASK;
  119. writel(mask, &port_base->mskr);
  120. writel(reg, &port_base->cfgr);
  121. if (value)
  122. writel(mask, &port_base->sodr);
  123. else
  124. writel(mask, &port_base->codr);
  125. return 0;
  126. }
  127. int atmel_pio4_get_pio_input(u32 port, u32 pin)
  128. {
  129. struct atmel_pio4_port *port_base;
  130. u32 reg, mask;
  131. if (pin >= ATMEL_PIO_NPINS_PER_BANK)
  132. return -EINVAL;
  133. port_base = atmel_pio4_port_base(port);
  134. if (!port_base)
  135. return -EINVAL;
  136. mask = 0x01 << pin;
  137. reg = ATMEL_PIO_CFGR_FUNC_GPIO;
  138. writel(mask, &port_base->mskr);
  139. writel(reg, &port_base->cfgr);
  140. return (readl(&port_base->pdsr) & mask) ? 1 : 0;
  141. }
  142. #if CONFIG_IS_ENABLED(DM_GPIO)
  143. /**
  144. * struct atmel_pioctrl_data - Atmel PIO controller (pinmux + gpio) data struct
  145. * @nbanks: number of PIO banks
  146. * @last_bank_count: number of lines in the last bank (can be less than
  147. * the rest of the banks).
  148. */
  149. struct atmel_pioctrl_data {
  150. u32 nbanks;
  151. u32 last_bank_count;
  152. };
  153. struct atmel_pio4_plat {
  154. struct atmel_pio4_port *reg_base;
  155. };
  156. static struct atmel_pio4_port *atmel_pio4_bank_base(struct udevice *dev,
  157. u32 bank)
  158. {
  159. struct atmel_pio4_plat *plat = dev_get_plat(dev);
  160. struct atmel_pio4_port *port_base =
  161. (struct atmel_pio4_port *)((u32)plat->reg_base +
  162. ATMEL_PIO_BANK_OFFSET * bank);
  163. return port_base;
  164. }
  165. static int atmel_pio4_direction_input(struct udevice *dev, unsigned offset)
  166. {
  167. u32 bank = ATMEL_PIO_BANK(offset);
  168. u32 line = ATMEL_PIO_LINE(offset);
  169. struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank);
  170. u32 mask = BIT(line);
  171. writel(mask, &port_base->mskr);
  172. clrbits_le32(&port_base->cfgr,
  173. ATMEL_PIO_CFGR_FUNC_MASK | ATMEL_PIO_DIR_MASK);
  174. return 0;
  175. }
  176. static int atmel_pio4_direction_output(struct udevice *dev,
  177. unsigned offset, int value)
  178. {
  179. u32 bank = ATMEL_PIO_BANK(offset);
  180. u32 line = ATMEL_PIO_LINE(offset);
  181. struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank);
  182. u32 mask = BIT(line);
  183. writel(mask, &port_base->mskr);
  184. clrsetbits_le32(&port_base->cfgr,
  185. ATMEL_PIO_CFGR_FUNC_MASK, ATMEL_PIO_DIR_MASK);
  186. if (value)
  187. writel(mask, &port_base->sodr);
  188. else
  189. writel(mask, &port_base->codr);
  190. return 0;
  191. }
  192. static int atmel_pio4_get_value(struct udevice *dev, unsigned offset)
  193. {
  194. u32 bank = ATMEL_PIO_BANK(offset);
  195. u32 line = ATMEL_PIO_LINE(offset);
  196. struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank);
  197. u32 mask = BIT(line);
  198. return (readl(&port_base->pdsr) & mask) ? 1 : 0;
  199. }
  200. static int atmel_pio4_set_value(struct udevice *dev,
  201. unsigned offset, int value)
  202. {
  203. u32 bank = ATMEL_PIO_BANK(offset);
  204. u32 line = ATMEL_PIO_LINE(offset);
  205. struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank);
  206. u32 mask = BIT(line);
  207. if (value)
  208. writel(mask, &port_base->sodr);
  209. else
  210. writel(mask, &port_base->codr);
  211. return 0;
  212. }
  213. static int atmel_pio4_get_function(struct udevice *dev, unsigned offset)
  214. {
  215. u32 bank = ATMEL_PIO_BANK(offset);
  216. u32 line = ATMEL_PIO_LINE(offset);
  217. struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank);
  218. u32 mask = BIT(line);
  219. writel(mask, &port_base->mskr);
  220. return (readl(&port_base->cfgr) &
  221. ATMEL_PIO_DIR_MASK) ? GPIOF_OUTPUT : GPIOF_INPUT;
  222. }
  223. static const struct dm_gpio_ops atmel_pio4_ops = {
  224. .direction_input = atmel_pio4_direction_input,
  225. .direction_output = atmel_pio4_direction_output,
  226. .get_value = atmel_pio4_get_value,
  227. .set_value = atmel_pio4_set_value,
  228. .get_function = atmel_pio4_get_function,
  229. };
  230. static int atmel_pio4_bind(struct udevice *dev)
  231. {
  232. return dm_scan_fdt_dev(dev);
  233. }
  234. static int atmel_pio4_probe(struct udevice *dev)
  235. {
  236. struct atmel_pio4_plat *plat = dev_get_plat(dev);
  237. struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
  238. struct atmel_pioctrl_data *pioctrl_data;
  239. struct clk clk;
  240. fdt_addr_t addr_base;
  241. u32 nbanks;
  242. int ret;
  243. ret = clk_get_by_index(dev, 0, &clk);
  244. if (ret)
  245. return ret;
  246. ret = clk_enable(&clk);
  247. if (ret)
  248. return ret;
  249. clk_free(&clk);
  250. addr_base = dev_read_addr(dev);
  251. if (addr_base == FDT_ADDR_T_NONE)
  252. return -EINVAL;
  253. plat->reg_base = (struct atmel_pio4_port *)addr_base;
  254. pioctrl_data = (struct atmel_pioctrl_data *)dev_get_driver_data(dev);
  255. nbanks = pioctrl_data->nbanks;
  256. uc_priv->bank_name = fdt_get_name(gd->fdt_blob, dev_of_offset(dev),
  257. NULL);
  258. uc_priv->gpio_count = nbanks * ATMEL_PIO_NPINS_PER_BANK;
  259. /* if last bank has limited number of pins, adjust accordingly */
  260. if (pioctrl_data->last_bank_count != ATMEL_PIO_NPINS_PER_BANK) {
  261. uc_priv->gpio_count -= ATMEL_PIO_NPINS_PER_BANK;
  262. uc_priv->gpio_count += pioctrl_data->last_bank_count;
  263. }
  264. return 0;
  265. }
  266. /*
  267. * The number of banks can be different from a SoC to another one.
  268. * We can have up to 16 banks.
  269. */
  270. static const struct atmel_pioctrl_data atmel_sama5d2_pioctrl_data = {
  271. .nbanks = 4,
  272. .last_bank_count = ATMEL_PIO_NPINS_PER_BANK,
  273. };
  274. static const struct atmel_pioctrl_data microchip_sama7g5_pioctrl_data = {
  275. .nbanks = 5,
  276. .last_bank_count = 8, /* 5th bank has only 8 lines on sama7g5 */
  277. };
  278. static const struct udevice_id atmel_pio4_ids[] = {
  279. {
  280. .compatible = "atmel,sama5d2-gpio",
  281. .data = (ulong)&atmel_sama5d2_pioctrl_data,
  282. }, {
  283. .compatible = "microchip,sama7g5-gpio",
  284. .data = (ulong)&microchip_sama7g5_pioctrl_data,
  285. },
  286. {}
  287. };
  288. U_BOOT_DRIVER(gpio_atmel_pio4) = {
  289. .name = "gpio_atmel_pio4",
  290. .id = UCLASS_GPIO,
  291. .ops = &atmel_pio4_ops,
  292. .probe = atmel_pio4_probe,
  293. .bind = atmel_pio4_bind,
  294. .of_match = atmel_pio4_ids,
  295. .plat_auto = sizeof(struct atmel_pio4_plat),
  296. };
  297. #endif