zynqpl.c 14 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2012-2013, Xilinx, Michal Simek
  4. *
  5. * (C) Copyright 2012
  6. * Joe Hershberger <joe.hershberger@ni.com>
  7. */
  8. #include <common.h>
  9. #include <console.h>
  10. #include <cpu_func.h>
  11. #include <log.h>
  12. #include <asm/cache.h>
  13. #include <asm/io.h>
  14. #include <fs.h>
  15. #include <zynqpl.h>
  16. #include <linux/delay.h>
  17. #include <linux/sizes.h>
  18. #include <asm/arch/hardware.h>
  19. #include <asm/arch/sys_proto.h>
  20. #define DEVCFG_CTRL_PCFG_PROG_B 0x40000000
  21. #define DEVCFG_CTRL_PCFG_AES_EFUSE_MASK 0x00001000
  22. #define DEVCFG_CTRL_PCAP_RATE_EN_MASK 0x02000000
  23. #define DEVCFG_CTRL_PCFG_AES_EN_MASK 0x00000E00
  24. #define DEVCFG_ISR_FATAL_ERROR_MASK 0x00740040
  25. #define DEVCFG_ISR_ERROR_FLAGS_MASK 0x00340840
  26. #define DEVCFG_ISR_RX_FIFO_OV 0x00040000
  27. #define DEVCFG_ISR_DMA_DONE 0x00002000
  28. #define DEVCFG_ISR_PCFG_DONE 0x00000004
  29. #define DEVCFG_STATUS_DMA_CMD_Q_F 0x80000000
  30. #define DEVCFG_STATUS_DMA_CMD_Q_E 0x40000000
  31. #define DEVCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000
  32. #define DEVCFG_STATUS_PCFG_INIT 0x00000010
  33. #define DEVCFG_MCTRL_PCAP_LPBK 0x00000010
  34. #define DEVCFG_MCTRL_RFIFO_FLUSH 0x00000002
  35. #define DEVCFG_MCTRL_WFIFO_FLUSH 0x00000001
  36. #ifndef CONFIG_SYS_FPGA_WAIT
  37. #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
  38. #endif
  39. #ifndef CONFIG_SYS_FPGA_PROG_TIME
  40. #define CONFIG_SYS_FPGA_PROG_TIME (CONFIG_SYS_HZ * 4) /* 4 s */
  41. #endif
  42. #define DUMMY_WORD 0xffffffff
  43. /* Xilinx binary format header */
  44. static const u32 bin_format[] = {
  45. DUMMY_WORD, /* Dummy words */
  46. DUMMY_WORD,
  47. DUMMY_WORD,
  48. DUMMY_WORD,
  49. DUMMY_WORD,
  50. DUMMY_WORD,
  51. DUMMY_WORD,
  52. DUMMY_WORD,
  53. 0x000000bb, /* Sync word */
  54. 0x11220044, /* Sync word */
  55. DUMMY_WORD,
  56. DUMMY_WORD,
  57. 0xaa995566, /* Sync word */
  58. };
  59. #define SWAP_NO 1
  60. #define SWAP_DONE 2
  61. /*
  62. * Load the whole word from unaligned buffer
  63. * Keep in your mind that it is byte loading on little-endian system
  64. */
  65. static u32 load_word(const void *buf, u32 swap)
  66. {
  67. u32 word = 0;
  68. u8 *bitc = (u8 *)buf;
  69. int p;
  70. if (swap == SWAP_NO) {
  71. for (p = 0; p < 4; p++) {
  72. word <<= 8;
  73. word |= bitc[p];
  74. }
  75. } else {
  76. for (p = 3; p >= 0; p--) {
  77. word <<= 8;
  78. word |= bitc[p];
  79. }
  80. }
  81. return word;
  82. }
  83. static u32 check_header(const void *buf)
  84. {
  85. u32 i, pattern;
  86. int swap = SWAP_NO;
  87. u32 *test = (u32 *)buf;
  88. debug("%s: Let's check bitstream header\n", __func__);
  89. /* Checking that passing bin is not a bitstream */
  90. for (i = 0; i < ARRAY_SIZE(bin_format); i++) {
  91. pattern = load_word(&test[i], swap);
  92. /*
  93. * Bitstreams in binary format are swapped
  94. * compare to regular bistream.
  95. * Do not swap dummy word but if swap is done assume
  96. * that parsing buffer is binary format
  97. */
  98. if ((__swab32(pattern) != DUMMY_WORD) &&
  99. (__swab32(pattern) == bin_format[i])) {
  100. pattern = __swab32(pattern);
  101. swap = SWAP_DONE;
  102. debug("%s: data swapped - let's swap\n", __func__);
  103. }
  104. debug("%s: %d/%x: pattern %x/%x bin_format\n", __func__, i,
  105. (u32)&test[i], pattern, bin_format[i]);
  106. if (pattern != bin_format[i]) {
  107. debug("%s: Bitstream is not recognized\n", __func__);
  108. return 0;
  109. }
  110. }
  111. debug("%s: Found bitstream header at %x %s swapinng\n", __func__,
  112. (u32)buf, swap == SWAP_NO ? "without" : "with");
  113. return swap;
  114. }
  115. static void *check_data(u8 *buf, size_t bsize, u32 *swap)
  116. {
  117. u32 word, p = 0; /* possition */
  118. /* Because buf doesn't need to be aligned let's read it by chars */
  119. for (p = 0; p < bsize; p++) {
  120. word = load_word(&buf[p], SWAP_NO);
  121. debug("%s: word %x %x/%x\n", __func__, word, p, (u32)&buf[p]);
  122. /* Find the first bitstream dummy word */
  123. if (word == DUMMY_WORD) {
  124. debug("%s: Found dummy word at position %x/%x\n",
  125. __func__, p, (u32)&buf[p]);
  126. *swap = check_header(&buf[p]);
  127. if (*swap) {
  128. /* FIXME add full bitstream checking here */
  129. return &buf[p];
  130. }
  131. }
  132. /* Loop can be huge - support CTRL + C */
  133. if (ctrlc())
  134. return NULL;
  135. }
  136. return NULL;
  137. }
  138. static int zynq_dma_transfer(u32 srcbuf, u32 srclen, u32 dstbuf, u32 dstlen)
  139. {
  140. unsigned long ts;
  141. u32 isr_status;
  142. /* Set up the transfer */
  143. writel((u32)srcbuf, &devcfg_base->dma_src_addr);
  144. writel(dstbuf, &devcfg_base->dma_dst_addr);
  145. writel(srclen, &devcfg_base->dma_src_len);
  146. writel(dstlen, &devcfg_base->dma_dst_len);
  147. isr_status = readl(&devcfg_base->int_sts);
  148. /* Polling the PCAP_INIT status for Set */
  149. ts = get_timer(0);
  150. while (!(isr_status & DEVCFG_ISR_DMA_DONE)) {
  151. if (isr_status & DEVCFG_ISR_ERROR_FLAGS_MASK) {
  152. debug("%s: Error: isr = 0x%08X\n", __func__,
  153. isr_status);
  154. debug("%s: Write count = 0x%08X\n", __func__,
  155. readl(&devcfg_base->write_count));
  156. debug("%s: Read count = 0x%08X\n", __func__,
  157. readl(&devcfg_base->read_count));
  158. return FPGA_FAIL;
  159. }
  160. if (get_timer(ts) > CONFIG_SYS_FPGA_PROG_TIME) {
  161. printf("%s: Timeout wait for DMA to complete\n",
  162. __func__);
  163. return FPGA_FAIL;
  164. }
  165. isr_status = readl(&devcfg_base->int_sts);
  166. }
  167. debug("%s: DMA transfer is done\n", __func__);
  168. /* Clear out the DMA status */
  169. writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts);
  170. return FPGA_SUCCESS;
  171. }
  172. static int zynq_dma_xfer_init(bitstream_type bstype)
  173. {
  174. u32 status, control, isr_status;
  175. unsigned long ts;
  176. /* Clear loopback bit */
  177. clrbits_le32(&devcfg_base->mctrl, DEVCFG_MCTRL_PCAP_LPBK);
  178. if (bstype != BIT_PARTIAL && bstype != BIT_NONE) {
  179. zynq_slcr_devcfg_disable();
  180. /* Setting PCFG_PROG_B signal to high */
  181. control = readl(&devcfg_base->ctrl);
  182. writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
  183. /*
  184. * Delay is required if AES efuse is selected as
  185. * key source.
  186. */
  187. if (control & DEVCFG_CTRL_PCFG_AES_EFUSE_MASK)
  188. mdelay(5);
  189. /* Setting PCFG_PROG_B signal to low */
  190. writel(control & ~DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
  191. /*
  192. * Delay is required if AES efuse is selected as
  193. * key source.
  194. */
  195. if (control & DEVCFG_CTRL_PCFG_AES_EFUSE_MASK)
  196. mdelay(5);
  197. /* Polling the PCAP_INIT status for Reset */
  198. ts = get_timer(0);
  199. while (readl(&devcfg_base->status) & DEVCFG_STATUS_PCFG_INIT) {
  200. if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
  201. printf("%s: Timeout wait for INIT to clear\n",
  202. __func__);
  203. return FPGA_FAIL;
  204. }
  205. }
  206. /* Setting PCFG_PROG_B signal to high */
  207. writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
  208. /* Polling the PCAP_INIT status for Set */
  209. ts = get_timer(0);
  210. while (!(readl(&devcfg_base->status) &
  211. DEVCFG_STATUS_PCFG_INIT)) {
  212. if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
  213. printf("%s: Timeout wait for INIT to set\n",
  214. __func__);
  215. return FPGA_FAIL;
  216. }
  217. }
  218. }
  219. isr_status = readl(&devcfg_base->int_sts);
  220. /* Clear it all, so if Boot ROM comes back, it can proceed */
  221. writel(0xFFFFFFFF, &devcfg_base->int_sts);
  222. if (isr_status & DEVCFG_ISR_FATAL_ERROR_MASK) {
  223. debug("%s: Fatal errors in PCAP 0x%X\n", __func__, isr_status);
  224. /* If RX FIFO overflow, need to flush RX FIFO first */
  225. if (isr_status & DEVCFG_ISR_RX_FIFO_OV) {
  226. writel(DEVCFG_MCTRL_RFIFO_FLUSH, &devcfg_base->mctrl);
  227. writel(0xFFFFFFFF, &devcfg_base->int_sts);
  228. }
  229. return FPGA_FAIL;
  230. }
  231. status = readl(&devcfg_base->status);
  232. debug("%s: Status = 0x%08X\n", __func__, status);
  233. if (status & DEVCFG_STATUS_DMA_CMD_Q_F) {
  234. debug("%s: Error: device busy\n", __func__);
  235. return FPGA_FAIL;
  236. }
  237. debug("%s: Device ready\n", __func__);
  238. if (!(status & DEVCFG_STATUS_DMA_CMD_Q_E)) {
  239. if (!(readl(&devcfg_base->int_sts) & DEVCFG_ISR_DMA_DONE)) {
  240. /* Error state, transfer cannot occur */
  241. debug("%s: ISR indicates error\n", __func__);
  242. return FPGA_FAIL;
  243. } else {
  244. /* Clear out the status */
  245. writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts);
  246. }
  247. }
  248. if (status & DEVCFG_STATUS_DMA_DONE_CNT_MASK) {
  249. /* Clear the count of completed DMA transfers */
  250. writel(DEVCFG_STATUS_DMA_DONE_CNT_MASK, &devcfg_base->status);
  251. }
  252. return FPGA_SUCCESS;
  253. }
  254. static u32 *zynq_align_dma_buffer(u32 *buf, u32 len, u32 swap)
  255. {
  256. u32 *new_buf;
  257. u32 i;
  258. if ((u32)buf != ALIGN((u32)buf, ARCH_DMA_MINALIGN)) {
  259. new_buf = (u32 *)ALIGN((u32)buf, ARCH_DMA_MINALIGN);
  260. /*
  261. * This might be dangerous but permits to flash if
  262. * ARCH_DMA_MINALIGN is greater than header size
  263. */
  264. if (new_buf > buf) {
  265. debug("%s: Aligned buffer is after buffer start\n",
  266. __func__);
  267. new_buf = (u32 *)((u32)new_buf - ARCH_DMA_MINALIGN);
  268. }
  269. printf("%s: Align buffer at %x to %x(swap %d)\n", __func__,
  270. (u32)buf, (u32)new_buf, swap);
  271. for (i = 0; i < (len/4); i++)
  272. new_buf[i] = load_word(&buf[i], swap);
  273. buf = new_buf;
  274. } else if (swap != SWAP_DONE) {
  275. /* For bitstream which are aligned */
  276. u32 *new_buf = (u32 *)buf;
  277. printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__,
  278. swap);
  279. for (i = 0; i < (len/4); i++)
  280. new_buf[i] = load_word(&buf[i], swap);
  281. }
  282. return buf;
  283. }
  284. static int zynq_validate_bitstream(xilinx_desc *desc, const void *buf,
  285. size_t bsize, u32 blocksize, u32 *swap,
  286. bitstream_type *bstype)
  287. {
  288. u32 *buf_start;
  289. u32 diff;
  290. buf_start = check_data((u8 *)buf, blocksize, swap);
  291. if (!buf_start)
  292. return FPGA_FAIL;
  293. /* Check if data is postpone from start */
  294. diff = (u32)buf_start - (u32)buf;
  295. if (diff) {
  296. printf("%s: Bitstream is not validated yet (diff %x)\n",
  297. __func__, diff);
  298. return FPGA_FAIL;
  299. }
  300. if ((u32)buf < SZ_1M) {
  301. printf("%s: Bitstream has to be placed up to 1MB (%x)\n",
  302. __func__, (u32)buf);
  303. return FPGA_FAIL;
  304. }
  305. if (zynq_dma_xfer_init(*bstype))
  306. return FPGA_FAIL;
  307. return 0;
  308. }
  309. static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize,
  310. bitstream_type bstype)
  311. {
  312. unsigned long ts; /* Timestamp */
  313. u32 isr_status, swap;
  314. /*
  315. * send bsize inplace of blocksize as it was not a bitstream
  316. * in chunks
  317. */
  318. if (zynq_validate_bitstream(desc, buf, bsize, bsize, &swap,
  319. &bstype))
  320. return FPGA_FAIL;
  321. buf = zynq_align_dma_buffer((u32 *)buf, bsize, swap);
  322. debug("%s: Source = 0x%08X\n", __func__, (u32)buf);
  323. debug("%s: Size = %zu\n", __func__, bsize);
  324. /* flush(clean & invalidate) d-cache range buf */
  325. flush_dcache_range((u32)buf, (u32)buf +
  326. roundup(bsize, ARCH_DMA_MINALIGN));
  327. if (zynq_dma_transfer((u32)buf | 1, bsize >> 2, 0xffffffff, 0))
  328. return FPGA_FAIL;
  329. isr_status = readl(&devcfg_base->int_sts);
  330. /* Check FPGA configuration completion */
  331. ts = get_timer(0);
  332. while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) {
  333. if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
  334. printf("%s: Timeout wait for FPGA to config\n",
  335. __func__);
  336. return FPGA_FAIL;
  337. }
  338. isr_status = readl(&devcfg_base->int_sts);
  339. }
  340. debug("%s: FPGA config done\n", __func__);
  341. if (bstype != BIT_PARTIAL)
  342. zynq_slcr_devcfg_enable();
  343. puts("INFO:post config was not run, please run manually if needed\n");
  344. return FPGA_SUCCESS;
  345. }
  346. #if defined(CONFIG_CMD_FPGA_LOADFS) && !defined(CONFIG_SPL_BUILD)
  347. static int zynq_loadfs(xilinx_desc *desc, const void *buf, size_t bsize,
  348. fpga_fs_info *fsinfo)
  349. {
  350. unsigned long ts; /* Timestamp */
  351. u32 isr_status, swap;
  352. u32 partialbit = 0;
  353. loff_t blocksize, actread;
  354. loff_t pos = 0;
  355. int fstype;
  356. char *interface, *dev_part;
  357. const char *filename;
  358. blocksize = fsinfo->blocksize;
  359. interface = fsinfo->interface;
  360. dev_part = fsinfo->dev_part;
  361. filename = fsinfo->filename;
  362. fstype = fsinfo->fstype;
  363. if (fs_set_blk_dev(interface, dev_part, fstype))
  364. return FPGA_FAIL;
  365. if (fs_read(filename, (u32) buf, pos, blocksize, &actread) < 0)
  366. return FPGA_FAIL;
  367. if (zynq_validate_bitstream(desc, buf, bsize, blocksize, &swap,
  368. &partialbit))
  369. return FPGA_FAIL;
  370. dcache_disable();
  371. do {
  372. buf = zynq_align_dma_buffer((u32 *)buf, blocksize, swap);
  373. if (zynq_dma_transfer((u32)buf | 1, blocksize >> 2,
  374. 0xffffffff, 0))
  375. return FPGA_FAIL;
  376. bsize -= blocksize;
  377. pos += blocksize;
  378. if (fs_set_blk_dev(interface, dev_part, fstype))
  379. return FPGA_FAIL;
  380. if (bsize > blocksize) {
  381. if (fs_read(filename, (u32) buf, pos, blocksize, &actread) < 0)
  382. return FPGA_FAIL;
  383. } else {
  384. if (fs_read(filename, (u32) buf, pos, bsize, &actread) < 0)
  385. return FPGA_FAIL;
  386. }
  387. } while (bsize > blocksize);
  388. buf = zynq_align_dma_buffer((u32 *)buf, blocksize, swap);
  389. if (zynq_dma_transfer((u32)buf | 1, bsize >> 2, 0xffffffff, 0))
  390. return FPGA_FAIL;
  391. dcache_enable();
  392. isr_status = readl(&devcfg_base->int_sts);
  393. /* Check FPGA configuration completion */
  394. ts = get_timer(0);
  395. while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) {
  396. if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
  397. printf("%s: Timeout wait for FPGA to config\n",
  398. __func__);
  399. return FPGA_FAIL;
  400. }
  401. isr_status = readl(&devcfg_base->int_sts);
  402. }
  403. debug("%s: FPGA config done\n", __func__);
  404. if (!partialbit)
  405. zynq_slcr_devcfg_enable();
  406. return FPGA_SUCCESS;
  407. }
  408. #endif
  409. struct xilinx_fpga_op zynq_op = {
  410. .load = zynq_load,
  411. #if defined(CONFIG_CMD_FPGA_LOADFS) && !defined(CONFIG_SPL_BUILD)
  412. .loadfs = zynq_loadfs,
  413. #endif
  414. };
  415. #ifdef CONFIG_CMD_ZYNQ_AES
  416. /*
  417. * Load the encrypted image from src addr and decrypt the image and
  418. * place it back the decrypted image into dstaddr.
  419. */
  420. int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen,
  421. u8 bstype)
  422. {
  423. u32 isr_status, ts;
  424. if (srcaddr < SZ_1M || dstaddr < SZ_1M) {
  425. printf("%s: src and dst addr should be > 1M\n",
  426. __func__);
  427. return FPGA_FAIL;
  428. }
  429. /* Check AES engine is enabled */
  430. if (!(readl(&devcfg_base->ctrl) &
  431. DEVCFG_CTRL_PCFG_AES_EN_MASK)) {
  432. printf("%s: AES engine is not enabled\n", __func__);
  433. return FPGA_FAIL;
  434. }
  435. if (zynq_dma_xfer_init(bstype)) {
  436. printf("%s: zynq_dma_xfer_init FAIL\n", __func__);
  437. return FPGA_FAIL;
  438. }
  439. writel((readl(&devcfg_base->ctrl) | DEVCFG_CTRL_PCAP_RATE_EN_MASK),
  440. &devcfg_base->ctrl);
  441. debug("%s: Source = 0x%08X\n", __func__, (u32)srcaddr);
  442. debug("%s: Size = %zu\n", __func__, srclen);
  443. /* flush(clean & invalidate) d-cache range buf */
  444. flush_dcache_range((u32)srcaddr, (u32)srcaddr +
  445. roundup(srclen << 2, ARCH_DMA_MINALIGN));
  446. /*
  447. * Flush destination address range only if image is not
  448. * bitstream.
  449. */
  450. if (bstype == BIT_NONE && dstaddr != 0xFFFFFFFF)
  451. flush_dcache_range((u32)dstaddr, (u32)dstaddr +
  452. roundup(dstlen << 2, ARCH_DMA_MINALIGN));
  453. if (zynq_dma_transfer(srcaddr | 1, srclen, dstaddr | 1, dstlen))
  454. return FPGA_FAIL;
  455. if (bstype == BIT_FULL) {
  456. isr_status = readl(&devcfg_base->int_sts);
  457. /* Check FPGA configuration completion */
  458. ts = get_timer(0);
  459. while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) {
  460. if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
  461. printf("%s: Timeout wait for FPGA to config\n",
  462. __func__);
  463. return FPGA_FAIL;
  464. }
  465. isr_status = readl(&devcfg_base->int_sts);
  466. }
  467. printf("%s: FPGA config done\n", __func__);
  468. zynq_slcr_devcfg_enable();
  469. }
  470. return FPGA_SUCCESS;
  471. }
  472. #endif