zynqmppl.c 7.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * (C) Copyright 2015 - 2016, Xilinx, Inc,
  4. * Michal Simek <michal.simek@xilinx.com>
  5. * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
  6. */
  7. #include <console.h>
  8. #include <common.h>
  9. #include <compiler.h>
  10. #include <cpu_func.h>
  11. #include <log.h>
  12. #include <zynqmppl.h>
  13. #include <zynqmp_firmware.h>
  14. #include <asm/cache.h>
  15. #include <linux/bitops.h>
  16. #include <linux/sizes.h>
  17. #include <asm/arch/sys_proto.h>
  18. #include <memalign.h>
  19. #define DUMMY_WORD 0xffffffff
  20. /* Xilinx binary format header */
  21. static const u32 bin_format[] = {
  22. DUMMY_WORD, /* Dummy words */
  23. DUMMY_WORD,
  24. DUMMY_WORD,
  25. DUMMY_WORD,
  26. DUMMY_WORD,
  27. DUMMY_WORD,
  28. DUMMY_WORD,
  29. DUMMY_WORD,
  30. DUMMY_WORD,
  31. DUMMY_WORD,
  32. DUMMY_WORD,
  33. DUMMY_WORD,
  34. DUMMY_WORD,
  35. DUMMY_WORD,
  36. DUMMY_WORD,
  37. DUMMY_WORD,
  38. 0x000000bb, /* Sync word */
  39. 0x11220044, /* Sync word */
  40. DUMMY_WORD,
  41. DUMMY_WORD,
  42. 0xaa995566, /* Sync word */
  43. };
  44. #define SWAP_NO 1
  45. #define SWAP_DONE 2
  46. /*
  47. * Load the whole word from unaligned buffer
  48. * Keep in your mind that it is byte loading on little-endian system
  49. */
  50. static u32 load_word(const void *buf, u32 swap)
  51. {
  52. u32 word = 0;
  53. u8 *bitc = (u8 *)buf;
  54. int p;
  55. if (swap == SWAP_NO) {
  56. for (p = 0; p < 4; p++) {
  57. word <<= 8;
  58. word |= bitc[p];
  59. }
  60. } else {
  61. for (p = 3; p >= 0; p--) {
  62. word <<= 8;
  63. word |= bitc[p];
  64. }
  65. }
  66. return word;
  67. }
  68. static u32 check_header(const void *buf)
  69. {
  70. u32 i, pattern;
  71. int swap = SWAP_NO;
  72. u32 *test = (u32 *)buf;
  73. debug("%s: Let's check bitstream header\n", __func__);
  74. /* Checking that passing bin is not a bitstream */
  75. for (i = 0; i < ARRAY_SIZE(bin_format); i++) {
  76. pattern = load_word(&test[i], swap);
  77. /*
  78. * Bitstreams in binary format are swapped
  79. * compare to regular bistream.
  80. * Do not swap dummy word but if swap is done assume
  81. * that parsing buffer is binary format
  82. */
  83. if ((__swab32(pattern) != DUMMY_WORD) &&
  84. (__swab32(pattern) == bin_format[i])) {
  85. swap = SWAP_DONE;
  86. debug("%s: data swapped - let's swap\n", __func__);
  87. }
  88. debug("%s: %d/%px: pattern %x/%x bin_format\n", __func__, i,
  89. &test[i], pattern, bin_format[i]);
  90. }
  91. debug("%s: Found bitstream header at %px %s swapinng\n", __func__,
  92. buf, swap == SWAP_NO ? "without" : "with");
  93. return swap;
  94. }
  95. static void *check_data(u8 *buf, size_t bsize, u32 *swap)
  96. {
  97. u32 word, p = 0; /* possition */
  98. /* Because buf doesn't need to be aligned let's read it by chars */
  99. for (p = 0; p < bsize; p++) {
  100. word = load_word(&buf[p], SWAP_NO);
  101. debug("%s: word %x %x/%px\n", __func__, word, p, &buf[p]);
  102. /* Find the first bitstream dummy word */
  103. if (word == DUMMY_WORD) {
  104. debug("%s: Found dummy word at position %x/%px\n",
  105. __func__, p, &buf[p]);
  106. *swap = check_header(&buf[p]);
  107. if (*swap) {
  108. /* FIXME add full bitstream checking here */
  109. return &buf[p];
  110. }
  111. }
  112. /* Loop can be huge - support CTRL + C */
  113. if (ctrlc())
  114. return NULL;
  115. }
  116. return NULL;
  117. }
  118. static ulong zynqmp_align_dma_buffer(u32 *buf, u32 len, u32 swap)
  119. {
  120. u32 *new_buf;
  121. u32 i;
  122. if ((ulong)buf != ALIGN((ulong)buf, ARCH_DMA_MINALIGN)) {
  123. new_buf = (u32 *)ALIGN((ulong)buf, ARCH_DMA_MINALIGN);
  124. /*
  125. * This might be dangerous but permits to flash if
  126. * ARCH_DMA_MINALIGN is greater than header size
  127. */
  128. if (new_buf > (u32 *)buf) {
  129. debug("%s: Aligned buffer is after buffer start\n",
  130. __func__);
  131. new_buf -= ARCH_DMA_MINALIGN;
  132. }
  133. printf("%s: Align buffer at %px to %px(swap %d)\n", __func__,
  134. buf, new_buf, swap);
  135. for (i = 0; i < (len/4); i++)
  136. new_buf[i] = load_word(&buf[i], swap);
  137. buf = new_buf;
  138. } else if ((swap != SWAP_DONE) &&
  139. (zynqmp_firmware_version() <= PMUFW_V1_0)) {
  140. /* For bitstream which are aligned */
  141. new_buf = buf;
  142. printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__,
  143. swap);
  144. for (i = 0; i < (len/4); i++)
  145. new_buf[i] = load_word(&buf[i], swap);
  146. }
  147. return (ulong)buf;
  148. }
  149. static int zynqmp_validate_bitstream(xilinx_desc *desc, const void *buf,
  150. size_t bsize, u32 blocksize, u32 *swap)
  151. {
  152. ulong *buf_start;
  153. ulong diff;
  154. buf_start = check_data((u8 *)buf, blocksize, swap);
  155. if (!buf_start)
  156. return FPGA_FAIL;
  157. /* Check if data is postpone from start */
  158. diff = (ulong)buf_start - (ulong)buf;
  159. if (diff) {
  160. printf("%s: Bitstream is not validated yet (diff %lx)\n",
  161. __func__, diff);
  162. return FPGA_FAIL;
  163. }
  164. if ((ulong)buf < SZ_1M) {
  165. printf("%s: Bitstream has to be placed up to 1MB (%px)\n",
  166. __func__, buf);
  167. return FPGA_FAIL;
  168. }
  169. return 0;
  170. }
  171. static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize,
  172. bitstream_type bstype)
  173. {
  174. ALLOC_CACHE_ALIGN_BUFFER(u32, bsizeptr, 1);
  175. u32 swap = 0;
  176. ulong bin_buf;
  177. int ret;
  178. u32 buf_lo, buf_hi;
  179. u32 ret_payload[PAYLOAD_ARG_CNT];
  180. bool xilfpga_old = false;
  181. if (zynqmp_firmware_version() <= PMUFW_V1_0) {
  182. puts("WARN: PMUFW v1.0 or less is detected\n");
  183. puts("WARN: Not all bitstream formats are supported\n");
  184. puts("WARN: Please upgrade PMUFW\n");
  185. xilfpga_old = true;
  186. if (zynqmp_validate_bitstream(desc, buf, bsize, bsize, &swap))
  187. return FPGA_FAIL;
  188. bsizeptr = (u32 *)&bsize;
  189. flush_dcache_range((ulong)bsizeptr,
  190. (ulong)bsizeptr + sizeof(size_t));
  191. bstype |= BIT(ZYNQMP_FPGA_BIT_NS);
  192. }
  193. bin_buf = zynqmp_align_dma_buffer((u32 *)buf, bsize, swap);
  194. debug("%s called!\n", __func__);
  195. flush_dcache_range(bin_buf, bin_buf + bsize);
  196. buf_lo = (u32)bin_buf;
  197. buf_hi = upper_32_bits(bin_buf);
  198. if (xilfpga_old)
  199. ret = xilinx_pm_request(PM_FPGA_LOAD, buf_lo,
  200. buf_hi, (u32)(uintptr_t)bsizeptr,
  201. bstype, ret_payload);
  202. else
  203. ret = xilinx_pm_request(PM_FPGA_LOAD, buf_lo,
  204. buf_hi, (u32)bsize, 0, ret_payload);
  205. if (ret)
  206. printf("PL FPGA LOAD failed with err: 0x%08x\n", ret);
  207. return ret;
  208. }
  209. #if defined(CONFIG_CMD_FPGA_LOAD_SECURE) && !defined(CONFIG_SPL_BUILD)
  210. static int zynqmp_loads(xilinx_desc *desc, const void *buf, size_t bsize,
  211. struct fpga_secure_info *fpga_sec_info)
  212. {
  213. int ret;
  214. u32 buf_lo, buf_hi;
  215. u32 ret_payload[PAYLOAD_ARG_CNT];
  216. u8 flag = 0;
  217. flush_dcache_range((ulong)buf, (ulong)buf +
  218. ALIGN(bsize, CONFIG_SYS_CACHELINE_SIZE));
  219. if (!fpga_sec_info->encflag)
  220. flag |= BIT(ZYNQMP_FPGA_BIT_ENC_DEV_KEY);
  221. if (fpga_sec_info->userkey_addr &&
  222. fpga_sec_info->encflag == FPGA_ENC_USR_KEY) {
  223. flush_dcache_range((ulong)fpga_sec_info->userkey_addr,
  224. (ulong)fpga_sec_info->userkey_addr +
  225. ALIGN(KEY_PTR_LEN,
  226. CONFIG_SYS_CACHELINE_SIZE));
  227. flag |= BIT(ZYNQMP_FPGA_BIT_ENC_USR_KEY);
  228. }
  229. if (!fpga_sec_info->authflag)
  230. flag |= BIT(ZYNQMP_FPGA_BIT_AUTH_OCM);
  231. if (fpga_sec_info->authflag == ZYNQMP_FPGA_AUTH_DDR)
  232. flag |= BIT(ZYNQMP_FPGA_BIT_AUTH_DDR);
  233. buf_lo = lower_32_bits((ulong)buf);
  234. buf_hi = upper_32_bits((ulong)buf);
  235. ret = xilinx_pm_request(PM_FPGA_LOAD, buf_lo,
  236. buf_hi,
  237. (u32)(uintptr_t)fpga_sec_info->userkey_addr,
  238. flag, ret_payload);
  239. if (ret)
  240. puts("PL FPGA LOAD fail\n");
  241. else
  242. puts("Bitstream successfully loaded\n");
  243. return ret;
  244. }
  245. #endif
  246. static int zynqmp_pcap_info(xilinx_desc *desc)
  247. {
  248. int ret;
  249. u32 ret_payload[PAYLOAD_ARG_CNT];
  250. ret = xilinx_pm_request(PM_FPGA_GET_STATUS, 0, 0, 0,
  251. 0, ret_payload);
  252. if (!ret)
  253. printf("PCAP status\t0x%x\n", ret_payload[1]);
  254. return ret;
  255. }
  256. struct xilinx_fpga_op zynqmp_op = {
  257. .load = zynqmp_load,
  258. #if defined(CONFIG_CMD_FPGA_LOAD_SECURE) && !defined(CONFIG_SPL_BUILD)
  259. .loads = zynqmp_loads,
  260. #endif
  261. .info = zynqmp_pcap_info,
  262. };