virtex2.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2002
  4. * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
  5. * Keith Outwater, keith_outwater@mvis.com
  6. *
  7. * Copyright (c) 2019 SED Systems, a division of Calian Ltd.
  8. */
  9. /*
  10. * Configuration support for Xilinx Virtex2 devices. Based
  11. * on spartan2.c (Rich Ireland, rireland@enterasys.com).
  12. */
  13. #include <common.h>
  14. #include <console.h>
  15. #include <virtex2.h>
  16. #include <linux/delay.h>
  17. #if 0
  18. #define FPGA_DEBUG
  19. #endif
  20. #ifdef FPGA_DEBUG
  21. #define PRINTF(fmt, args...) printf(fmt, ##args)
  22. #else
  23. #define PRINTF(fmt, args...)
  24. #endif
  25. /*
  26. * If the SelectMap interface can be overrun by the processor, define
  27. * CONFIG_SYS_FPGA_CHECK_BUSY and/or CONFIG_FPGA_DELAY in the board
  28. * configuration file and add board-specific support for checking BUSY status.
  29. * By default, assume that the SelectMap interface cannot be overrun.
  30. */
  31. #ifndef CONFIG_SYS_FPGA_CHECK_BUSY
  32. #undef CONFIG_SYS_FPGA_CHECK_BUSY
  33. #endif
  34. #ifndef CONFIG_FPGA_DELAY
  35. #define CONFIG_FPGA_DELAY()
  36. #endif
  37. #ifndef CONFIG_SYS_FPGA_PROG_FEEDBACK
  38. #define CONFIG_SYS_FPGA_PROG_FEEDBACK
  39. #endif
  40. /*
  41. * Don't allow config cycle to be interrupted
  42. */
  43. #ifndef CONFIG_SYS_FPGA_CHECK_CTRLC
  44. #undef CONFIG_SYS_FPGA_CHECK_CTRLC
  45. #endif
  46. /*
  47. * Check for errors during configuration by default
  48. */
  49. #ifndef CONFIG_SYS_FPGA_CHECK_ERROR
  50. #define CONFIG_SYS_FPGA_CHECK_ERROR
  51. #endif
  52. /*
  53. * The default timeout in mS for INIT_B to deassert after PROG_B has
  54. * been deasserted. Per the latest Virtex II Handbook (page 347), the
  55. * max time from PORG_B deassertion to INIT_B deassertion is 4uS per
  56. * data frame for the XC2V8000. The XC2V8000 has 2860 data frames
  57. * which yields 11.44 mS. So let's make it bigger in order to handle
  58. * an XC2V1000, if anyone can ever get ahold of one.
  59. */
  60. #ifndef CONFIG_SYS_FPGA_WAIT_INIT
  61. #define CONFIG_SYS_FPGA_WAIT_INIT CONFIG_SYS_HZ / 2 /* 500 ms */
  62. #endif
  63. /*
  64. * The default timeout for waiting for BUSY to deassert during configuration.
  65. * This is normally not necessary since for most reasonable configuration
  66. * clock frequencies (i.e. 66 MHz or less), BUSY monitoring is unnecessary.
  67. */
  68. #ifndef CONFIG_SYS_FPGA_WAIT_BUSY
  69. #define CONFIG_SYS_FPGA_WAIT_BUSY CONFIG_SYS_HZ / 200 /* 5 ms*/
  70. #endif
  71. /* Default timeout for waiting for FPGA to enter operational mode after
  72. * configuration data has been written.
  73. */
  74. #ifndef CONFIG_SYS_FPGA_WAIT_CONFIG
  75. #define CONFIG_SYS_FPGA_WAIT_CONFIG CONFIG_SYS_HZ / 5 /* 200 ms */
  76. #endif
  77. static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize);
  78. static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize);
  79. static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize);
  80. static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize);
  81. static int virtex2_load(xilinx_desc *desc, const void *buf, size_t bsize,
  82. bitstream_type bstype)
  83. {
  84. int ret_val = FPGA_FAIL;
  85. switch (desc->iface) {
  86. case slave_serial:
  87. PRINTF("%s: Launching Slave Serial Load\n", __func__);
  88. ret_val = virtex2_ss_load(desc, buf, bsize);
  89. break;
  90. case slave_selectmap:
  91. PRINTF("%s: Launching Slave Parallel Load\n", __func__);
  92. ret_val = virtex2_ssm_load(desc, buf, bsize);
  93. break;
  94. default:
  95. printf("%s: Unsupported interface type, %d\n",
  96. __func__, desc->iface);
  97. }
  98. return ret_val;
  99. }
  100. static int virtex2_dump(xilinx_desc *desc, const void *buf, size_t bsize)
  101. {
  102. int ret_val = FPGA_FAIL;
  103. switch (desc->iface) {
  104. case slave_serial:
  105. PRINTF("%s: Launching Slave Serial Dump\n", __func__);
  106. ret_val = virtex2_ss_dump(desc, buf, bsize);
  107. break;
  108. case slave_parallel:
  109. PRINTF("%s: Launching Slave Parallel Dump\n", __func__);
  110. ret_val = virtex2_ssm_dump(desc, buf, bsize);
  111. break;
  112. default:
  113. printf("%s: Unsupported interface type, %d\n",
  114. __func__, desc->iface);
  115. }
  116. return ret_val;
  117. }
  118. static int virtex2_info(xilinx_desc *desc)
  119. {
  120. return FPGA_SUCCESS;
  121. }
  122. /*
  123. * Virtex-II Slave SelectMap or Serial configuration loader. Configuration
  124. * is as follows:
  125. * 1. Set the FPGA's PROG_B line low.
  126. * 2. Set the FPGA's PROG_B line high. Wait for INIT_B to go high.
  127. * 3. Write data to the SelectMap port. If INIT_B goes low at any time
  128. * this process, a configuration error (most likely CRC failure) has
  129. * ocurred. At this point a status word may be read from the
  130. * SelectMap interface to determine the source of the problem (You
  131. * could, for instance, put this in your 'abort' function handler).
  132. * 4. After all data has been written, test the state of the FPGA
  133. * INIT_B and DONE lines. If both are high, configuration has
  134. * succeeded. Congratulations!
  135. */
  136. static int virtex2_slave_pre(xilinx_virtex2_slave_fns *fn, int cookie)
  137. {
  138. unsigned long ts;
  139. PRINTF("%s:%d: Start with interface functions @ 0x%p\n",
  140. __func__, __LINE__, fn);
  141. if (!fn) {
  142. printf("%s:%d: NULL Interface function table!\n",
  143. __func__, __LINE__);
  144. return FPGA_FAIL;
  145. }
  146. /* Gotta split this one up (so the stack won't blow??) */
  147. PRINTF("%s:%d: Function Table:\n"
  148. " base 0x%p\n"
  149. " struct 0x%p\n"
  150. " pre 0x%p\n"
  151. " prog 0x%p\n"
  152. " init 0x%p\n"
  153. " error 0x%p\n",
  154. __func__, __LINE__,
  155. &fn, fn, fn->pre, fn->pgm, fn->init, fn->err);
  156. PRINTF(" clock 0x%p\n"
  157. " cs 0x%p\n"
  158. " write 0x%p\n"
  159. " rdata 0x%p\n"
  160. " wdata 0x%p\n"
  161. " busy 0x%p\n"
  162. " abort 0x%p\n"
  163. " post 0x%p\n\n",
  164. fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata,
  165. fn->busy, fn->abort, fn->post);
  166. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  167. printf("Initializing FPGA Device %d...\n", cookie);
  168. #endif
  169. /*
  170. * Run the pre configuration function if there is one.
  171. */
  172. if (*fn->pre)
  173. (*fn->pre)(cookie);
  174. /*
  175. * Assert the program line. The minimum pulse width for
  176. * Virtex II devices is 300 nS (Tprogram parameter in datasheet).
  177. * There is no maximum value for the pulse width. Check to make
  178. * sure that INIT_B goes low after assertion of PROG_B
  179. */
  180. (*fn->pgm)(true, true, cookie);
  181. udelay(10);
  182. ts = get_timer(0);
  183. do {
  184. if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_INIT) {
  185. printf("%s:%d: ** Timeout after %d ticks waiting for INIT to assert.\n",
  186. __func__, __LINE__, CONFIG_SYS_FPGA_WAIT_INIT);
  187. (*fn->abort)(cookie);
  188. return FPGA_FAIL;
  189. }
  190. } while (!(*fn->init)(cookie));
  191. (*fn->pgm)(false, true, cookie);
  192. CONFIG_FPGA_DELAY();
  193. if (fn->clk)
  194. (*fn->clk)(true, true, cookie);
  195. /*
  196. * Start a timer and wait for INIT_B to go high
  197. */
  198. ts = get_timer(0);
  199. do {
  200. CONFIG_FPGA_DELAY();
  201. if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_INIT) {
  202. printf("%s:%d: ** Timeout after %d ticks waiting for INIT to deassert.\n",
  203. __func__, __LINE__, CONFIG_SYS_FPGA_WAIT_INIT);
  204. (*fn->abort)(cookie);
  205. return FPGA_FAIL;
  206. }
  207. } while ((*fn->init)(cookie) && (*fn->busy)(cookie));
  208. if (fn->wr)
  209. (*fn->wr)(true, true, cookie);
  210. if (fn->cs)
  211. (*fn->cs)(true, true, cookie);
  212. mdelay(10);
  213. return FPGA_SUCCESS;
  214. }
  215. static int virtex2_slave_post(xilinx_virtex2_slave_fns *fn,
  216. int cookie)
  217. {
  218. int ret_val = FPGA_SUCCESS;
  219. int num_done = 0;
  220. unsigned long ts;
  221. /*
  222. * Finished writing the data; deassert FPGA CS_B and WRITE_B signals.
  223. */
  224. CONFIG_FPGA_DELAY();
  225. if (fn->cs)
  226. (*fn->cs)(false, true, cookie);
  227. if (fn->wr)
  228. (*fn->wr)(false, true, cookie);
  229. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  230. putc('\n');
  231. #endif
  232. /*
  233. * Check for successful configuration. FPGA INIT_B and DONE
  234. * should both be high upon successful configuration. Continue pulsing
  235. * clock with data set to all ones until DONE is asserted and for 8
  236. * clock cycles afterwards.
  237. */
  238. ts = get_timer(0);
  239. while (true) {
  240. if ((*fn->done)(cookie) == FPGA_SUCCESS &&
  241. !((*fn->init)(cookie))) {
  242. if (num_done++ >= 8)
  243. break;
  244. }
  245. if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_CONFIG) {
  246. printf("%s:%d: ** Timeout after %d ticks waiting for DONE to assert and INIT to deassert\n",
  247. __func__, __LINE__, CONFIG_SYS_FPGA_WAIT_CONFIG);
  248. (*fn->abort)(cookie);
  249. ret_val = FPGA_FAIL;
  250. break;
  251. }
  252. if (fn->wbulkdata) {
  253. unsigned char dummy = 0xff;
  254. (*fn->wbulkdata)(&dummy, 1, true, cookie);
  255. } else {
  256. (*fn->wdata)(0xff, true, cookie);
  257. CONFIG_FPGA_DELAY();
  258. (*fn->clk)(false, true, cookie);
  259. CONFIG_FPGA_DELAY();
  260. (*fn->clk)(true, true, cookie);
  261. }
  262. }
  263. if (ret_val == FPGA_SUCCESS) {
  264. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  265. printf("Initialization of FPGA device %d complete\n", cookie);
  266. #endif
  267. /*
  268. * Run the post configuration function if there is one.
  269. */
  270. if (*fn->post)
  271. (*fn->post)(cookie);
  272. } else {
  273. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  274. printf("** Initialization of FPGA device %d FAILED\n",
  275. cookie);
  276. #endif
  277. }
  278. return ret_val;
  279. }
  280. static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize)
  281. {
  282. int ret_val = FPGA_FAIL;
  283. xilinx_virtex2_slave_fns *fn = desc->iface_fns;
  284. size_t bytecount = 0;
  285. unsigned char *data = (unsigned char *)buf;
  286. int cookie = desc->cookie;
  287. ret_val = virtex2_slave_pre(fn, cookie);
  288. if (ret_val != FPGA_SUCCESS)
  289. return ret_val;
  290. /*
  291. * Load the data byte by byte
  292. */
  293. while (bytecount < bsize) {
  294. #ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
  295. if (ctrlc()) {
  296. (*fn->abort)(cookie);
  297. return FPGA_FAIL;
  298. }
  299. #endif
  300. if ((*fn->done)(cookie) == FPGA_SUCCESS) {
  301. PRINTF("%s:%d:done went active early, bytecount = %d\n",
  302. __func__, __LINE__, bytecount);
  303. break;
  304. }
  305. #ifdef CONFIG_SYS_FPGA_CHECK_ERROR
  306. if ((*fn->init)(cookie)) {
  307. printf("\n%s:%d: ** Error: INIT asserted during configuration\n",
  308. __func__, __LINE__);
  309. printf("%zu = buffer offset, %zu = buffer size\n",
  310. bytecount, bsize);
  311. (*fn->abort)(cookie);
  312. return FPGA_FAIL;
  313. }
  314. #endif
  315. (*fn->wdata)(data[bytecount++], true, cookie);
  316. CONFIG_FPGA_DELAY();
  317. /*
  318. * Cycle the clock pin
  319. */
  320. (*fn->clk)(false, true, cookie);
  321. CONFIG_FPGA_DELAY();
  322. (*fn->clk)(true, true, cookie);
  323. #ifdef CONFIG_SYS_FPGA_CHECK_BUSY
  324. ts = get_timer(0);
  325. while ((*fn->busy)(cookie)) {
  326. if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_BUSY) {
  327. printf("%s:%d: ** Timeout after %d ticks waiting for BUSY to deassert\n",
  328. __func__, __LINE__,
  329. CONFIG_SYS_FPGA_WAIT_BUSY);
  330. (*fn->abort)(cookie);
  331. return FPGA_FAIL;
  332. }
  333. }
  334. #endif
  335. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  336. if (bytecount % (bsize / 40) == 0)
  337. putc('.');
  338. #endif
  339. }
  340. return virtex2_slave_post(fn, cookie);
  341. }
  342. /*
  343. * Read the FPGA configuration data
  344. */
  345. static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize)
  346. {
  347. int ret_val = FPGA_FAIL;
  348. xilinx_virtex2_slave_fns *fn = desc->iface_fns;
  349. if (fn) {
  350. unsigned char *data = (unsigned char *)buf;
  351. size_t bytecount = 0;
  352. int cookie = desc->cookie;
  353. printf("Starting Dump of FPGA Device %d...\n", cookie);
  354. (*fn->cs)(true, true, cookie);
  355. (*fn->clk)(true, true, cookie);
  356. while (bytecount < bsize) {
  357. #ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
  358. if (ctrlc()) {
  359. (*fn->abort)(cookie);
  360. return FPGA_FAIL;
  361. }
  362. #endif
  363. /*
  364. * Cycle the clock and read the data
  365. */
  366. (*fn->clk)(false, true, cookie);
  367. (*fn->clk)(true, true, cookie);
  368. (*fn->rdata)(&data[bytecount++], cookie);
  369. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  370. if (bytecount % (bsize / 40) == 0)
  371. putc('.');
  372. #endif
  373. }
  374. /*
  375. * Deassert CS_B and cycle the clock to deselect the device.
  376. */
  377. (*fn->cs)(false, false, cookie);
  378. (*fn->clk)(false, true, cookie);
  379. (*fn->clk)(true, true, cookie);
  380. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  381. putc('\n');
  382. #endif
  383. puts("Done.\n");
  384. } else {
  385. printf("%s:%d: NULL Interface function table!\n",
  386. __func__, __LINE__);
  387. }
  388. return ret_val;
  389. }
  390. static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
  391. {
  392. int ret_val = FPGA_FAIL;
  393. xilinx_virtex2_slave_fns *fn = desc->iface_fns;
  394. unsigned char *data = (unsigned char *)buf;
  395. int cookie = desc->cookie;
  396. ret_val = virtex2_slave_pre(fn, cookie);
  397. if (ret_val != FPGA_SUCCESS)
  398. return ret_val;
  399. if (fn->wbulkdata) {
  400. /* Load the data in a single chunk */
  401. (*fn->wbulkdata)(data, bsize, true, cookie);
  402. } else {
  403. size_t bytecount = 0;
  404. /*
  405. * Load the data bit by bit
  406. */
  407. while (bytecount < bsize) {
  408. unsigned char curr_data = data[bytecount++];
  409. int bit;
  410. #ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
  411. if (ctrlc()) {
  412. (*fn->abort) (cookie);
  413. return FPGA_FAIL;
  414. }
  415. #endif
  416. if ((*fn->done)(cookie) == FPGA_SUCCESS) {
  417. PRINTF("%s:%d:done went active early, bytecount = %d\n",
  418. __func__, __LINE__, bytecount);
  419. break;
  420. }
  421. #ifdef CONFIG_SYS_FPGA_CHECK_ERROR
  422. if ((*fn->init)(cookie)) {
  423. printf("\n%s:%d: ** Error: INIT asserted during configuration\n",
  424. __func__, __LINE__);
  425. printf("%zu = buffer offset, %zu = buffer size\n",
  426. bytecount, bsize);
  427. (*fn->abort)(cookie);
  428. return FPGA_FAIL;
  429. }
  430. #endif
  431. for (bit = 7; bit >= 0; --bit) {
  432. unsigned char curr_bit = (curr_data >> bit) & 1;
  433. (*fn->wdata)(curr_bit, true, cookie);
  434. CONFIG_FPGA_DELAY();
  435. (*fn->clk)(false, true, cookie);
  436. CONFIG_FPGA_DELAY();
  437. (*fn->clk)(true, true, cookie);
  438. }
  439. /* Slave serial never uses a busy pin */
  440. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  441. if (bytecount % (bsize / 40) == 0)
  442. putc('.');
  443. #endif
  444. }
  445. }
  446. return virtex2_slave_post(fn, cookie);
  447. }
  448. static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize)
  449. {
  450. printf("%s: Slave Serial Dumping is unsupported\n", __func__);
  451. return FPGA_FAIL;
  452. }
  453. /* vim: set ts=4 tw=78: */
  454. struct xilinx_fpga_op virtex2_op = {
  455. .load = virtex2_load,
  456. .dump = virtex2_dump,
  457. .info = virtex2_info,
  458. };