spartan2.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2002
  4. * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
  5. */
  6. #include <common.h> /* core U-Boot definitions */
  7. #include <spartan2.h> /* Spartan-II device family */
  8. /* Define FPGA_DEBUG to get debug printf's */
  9. #ifdef FPGA_DEBUG
  10. #define PRINTF(fmt,args...) printf (fmt ,##args)
  11. #else
  12. #define PRINTF(fmt,args...)
  13. #endif
  14. #undef CONFIG_SYS_FPGA_CHECK_BUSY
  15. #undef CONFIG_SYS_FPGA_PROG_FEEDBACK
  16. /* Note: The assumption is that we cannot possibly run fast enough to
  17. * overrun the device (the Slave Parallel mode can free run at 50MHz).
  18. * If there is a need to operate slower, define CONFIG_FPGA_DELAY in
  19. * the board config file to slow things down.
  20. */
  21. #ifndef CONFIG_FPGA_DELAY
  22. #define CONFIG_FPGA_DELAY()
  23. #endif
  24. #ifndef CONFIG_SYS_FPGA_WAIT
  25. #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
  26. #endif
  27. static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize);
  28. static int spartan2_sp_dump(xilinx_desc *desc, const void *buf, size_t bsize);
  29. /* static int spartan2_sp_info(xilinx_desc *desc ); */
  30. static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize);
  31. static int spartan2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize);
  32. /* static int spartan2_ss_info(xilinx_desc *desc ); */
  33. /* ------------------------------------------------------------------------- */
  34. /* Spartan-II Generic Implementation */
  35. static int spartan2_load(xilinx_desc *desc, const void *buf, size_t bsize,
  36. bitstream_type bstype)
  37. {
  38. int ret_val = FPGA_FAIL;
  39. switch (desc->iface) {
  40. case slave_serial:
  41. PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__);
  42. ret_val = spartan2_ss_load(desc, buf, bsize);
  43. break;
  44. case slave_parallel:
  45. PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__);
  46. ret_val = spartan2_sp_load(desc, buf, bsize);
  47. break;
  48. default:
  49. printf ("%s: Unsupported interface type, %d\n",
  50. __FUNCTION__, desc->iface);
  51. }
  52. return ret_val;
  53. }
  54. static int spartan2_dump(xilinx_desc *desc, const void *buf, size_t bsize)
  55. {
  56. int ret_val = FPGA_FAIL;
  57. switch (desc->iface) {
  58. case slave_serial:
  59. PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__);
  60. ret_val = spartan2_ss_dump(desc, buf, bsize);
  61. break;
  62. case slave_parallel:
  63. PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__);
  64. ret_val = spartan2_sp_dump(desc, buf, bsize);
  65. break;
  66. default:
  67. printf ("%s: Unsupported interface type, %d\n",
  68. __FUNCTION__, desc->iface);
  69. }
  70. return ret_val;
  71. }
  72. static int spartan2_info(xilinx_desc *desc)
  73. {
  74. return FPGA_SUCCESS;
  75. }
  76. /* ------------------------------------------------------------------------- */
  77. /* Spartan-II Slave Parallel Generic Implementation */
  78. static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize)
  79. {
  80. int ret_val = FPGA_FAIL; /* assume the worst */
  81. xilinx_spartan2_slave_parallel_fns *fn = desc->iface_fns;
  82. PRINTF ("%s: start with interface functions @ 0x%p\n",
  83. __FUNCTION__, fn);
  84. if (fn) {
  85. size_t bytecount = 0;
  86. unsigned char *data = (unsigned char *) buf;
  87. int cookie = desc->cookie; /* make a local copy */
  88. unsigned long ts; /* timestamp */
  89. PRINTF ("%s: Function Table:\n"
  90. "ptr:\t0x%p\n"
  91. "struct: 0x%p\n"
  92. "pre: 0x%p\n"
  93. "pgm:\t0x%p\n"
  94. "init:\t0x%p\n"
  95. "err:\t0x%p\n"
  96. "clk:\t0x%p\n"
  97. "cs:\t0x%p\n"
  98. "wr:\t0x%p\n"
  99. "read data:\t0x%p\n"
  100. "write data:\t0x%p\n"
  101. "busy:\t0x%p\n"
  102. "abort:\t0x%p\n",
  103. "post:\t0x%p\n\n",
  104. __FUNCTION__, &fn, fn, fn->pre, fn->pgm, fn->init, fn->err,
  105. fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata, fn->busy,
  106. fn->abort, fn->post);
  107. /*
  108. * This code is designed to emulate the "Express Style"
  109. * Continuous Data Loading in Slave Parallel Mode for
  110. * the Spartan-II Family.
  111. */
  112. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  113. printf ("Loading FPGA Device %d...\n", cookie);
  114. #endif
  115. /*
  116. * Run the pre configuration function if there is one.
  117. */
  118. if (*fn->pre) {
  119. (*fn->pre) (cookie);
  120. }
  121. /* Establish the initial state */
  122. (*fn->pgm) (true, true, cookie); /* Assert the program, commit */
  123. /* Get ready for the burn */
  124. CONFIG_FPGA_DELAY ();
  125. (*fn->pgm) (false, true, cookie); /* Deassert the program, commit */
  126. ts = get_timer (0); /* get current time */
  127. /* Now wait for INIT and BUSY to go high */
  128. do {
  129. CONFIG_FPGA_DELAY ();
  130. if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
  131. puts ("** Timeout waiting for INIT to clear.\n");
  132. (*fn->abort) (cookie); /* abort the burn */
  133. return FPGA_FAIL;
  134. }
  135. } while ((*fn->init) (cookie) && (*fn->busy) (cookie));
  136. (*fn->wr) (true, true, cookie); /* Assert write, commit */
  137. (*fn->cs) (true, true, cookie); /* Assert chip select, commit */
  138. (*fn->clk) (true, true, cookie); /* Assert the clock pin */
  139. /* Load the data */
  140. while (bytecount < bsize) {
  141. /* XXX - do we check for an Ctrl-C press in here ??? */
  142. /* XXX - Check the error bit? */
  143. (*fn->wdata) (data[bytecount++], true, cookie); /* write the data */
  144. CONFIG_FPGA_DELAY ();
  145. (*fn->clk) (false, true, cookie); /* Deassert the clock pin */
  146. CONFIG_FPGA_DELAY ();
  147. (*fn->clk) (true, true, cookie); /* Assert the clock pin */
  148. #ifdef CONFIG_SYS_FPGA_CHECK_BUSY
  149. ts = get_timer (0); /* get current time */
  150. while ((*fn->busy) (cookie)) {
  151. /* XXX - we should have a check in here somewhere to
  152. * make sure we aren't busy forever... */
  153. CONFIG_FPGA_DELAY ();
  154. (*fn->clk) (false, true, cookie); /* Deassert the clock pin */
  155. CONFIG_FPGA_DELAY ();
  156. (*fn->clk) (true, true, cookie); /* Assert the clock pin */
  157. if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
  158. puts ("** Timeout waiting for BUSY to clear.\n");
  159. (*fn->abort) (cookie); /* abort the burn */
  160. return FPGA_FAIL;
  161. }
  162. }
  163. #endif
  164. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  165. if (bytecount % (bsize / 40) == 0)
  166. putc ('.'); /* let them know we are alive */
  167. #endif
  168. }
  169. CONFIG_FPGA_DELAY ();
  170. (*fn->cs) (false, true, cookie); /* Deassert the chip select */
  171. (*fn->wr) (false, true, cookie); /* Deassert the write pin */
  172. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  173. putc ('\n'); /* terminate the dotted line */
  174. #endif
  175. /* now check for done signal */
  176. ts = get_timer (0); /* get current time */
  177. ret_val = FPGA_SUCCESS;
  178. while ((*fn->done) (cookie) == FPGA_FAIL) {
  179. CONFIG_FPGA_DELAY ();
  180. (*fn->clk) (false, true, cookie); /* Deassert the clock pin */
  181. CONFIG_FPGA_DELAY ();
  182. (*fn->clk) (true, true, cookie); /* Assert the clock pin */
  183. if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
  184. puts ("** Timeout waiting for DONE to clear.\n");
  185. (*fn->abort) (cookie); /* abort the burn */
  186. ret_val = FPGA_FAIL;
  187. break;
  188. }
  189. }
  190. /*
  191. * Run the post configuration function if there is one.
  192. */
  193. if (*fn->post)
  194. (*fn->post) (cookie);
  195. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  196. if (ret_val == FPGA_SUCCESS)
  197. puts ("Done.\n");
  198. else
  199. puts ("Fail.\n");
  200. #endif
  201. } else {
  202. printf ("%s: NULL Interface function table!\n", __FUNCTION__);
  203. }
  204. return ret_val;
  205. }
  206. static int spartan2_sp_dump(xilinx_desc *desc, const void *buf, size_t bsize)
  207. {
  208. int ret_val = FPGA_FAIL; /* assume the worst */
  209. xilinx_spartan2_slave_parallel_fns *fn = desc->iface_fns;
  210. if (fn) {
  211. unsigned char *data = (unsigned char *) buf;
  212. size_t bytecount = 0;
  213. int cookie = desc->cookie; /* make a local copy */
  214. printf ("Starting Dump of FPGA Device %d...\n", cookie);
  215. (*fn->cs) (true, true, cookie); /* Assert chip select, commit */
  216. (*fn->clk) (true, true, cookie); /* Assert the clock pin */
  217. /* dump the data */
  218. while (bytecount < bsize) {
  219. /* XXX - do we check for an Ctrl-C press in here ??? */
  220. (*fn->clk) (false, true, cookie); /* Deassert the clock pin */
  221. (*fn->clk) (true, true, cookie); /* Assert the clock pin */
  222. (*fn->rdata) (&(data[bytecount++]), cookie); /* read the data */
  223. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  224. if (bytecount % (bsize / 40) == 0)
  225. putc ('.'); /* let them know we are alive */
  226. #endif
  227. }
  228. (*fn->cs) (false, false, cookie); /* Deassert the chip select */
  229. (*fn->clk) (false, true, cookie); /* Deassert the clock pin */
  230. (*fn->clk) (true, true, cookie); /* Assert the clock pin */
  231. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  232. putc ('\n'); /* terminate the dotted line */
  233. #endif
  234. puts ("Done.\n");
  235. /* XXX - checksum the data? */
  236. } else {
  237. printf ("%s: NULL Interface function table!\n", __FUNCTION__);
  238. }
  239. return ret_val;
  240. }
  241. /* ------------------------------------------------------------------------- */
  242. static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
  243. {
  244. int ret_val = FPGA_FAIL; /* assume the worst */
  245. xilinx_spartan2_slave_serial_fns *fn = desc->iface_fns;
  246. int i;
  247. unsigned char val;
  248. PRINTF ("%s: start with interface functions @ 0x%p\n",
  249. __FUNCTION__, fn);
  250. if (fn) {
  251. size_t bytecount = 0;
  252. unsigned char *data = (unsigned char *) buf;
  253. int cookie = desc->cookie; /* make a local copy */
  254. unsigned long ts; /* timestamp */
  255. PRINTF ("%s: Function Table:\n"
  256. "ptr:\t0x%p\n"
  257. "struct: 0x%p\n"
  258. "pgm:\t0x%p\n"
  259. "init:\t0x%p\n"
  260. "clk:\t0x%p\n"
  261. "wr:\t0x%p\n"
  262. "done:\t0x%p\n\n",
  263. __FUNCTION__, &fn, fn, fn->pgm, fn->init,
  264. fn->clk, fn->wr, fn->done);
  265. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  266. printf ("Loading FPGA Device %d...\n", cookie);
  267. #endif
  268. /*
  269. * Run the pre configuration function if there is one.
  270. */
  271. if (*fn->pre) {
  272. (*fn->pre) (cookie);
  273. }
  274. /* Establish the initial state */
  275. (*fn->pgm) (true, true, cookie); /* Assert the program, commit */
  276. /* Wait for INIT state (init low) */
  277. ts = get_timer (0); /* get current time */
  278. do {
  279. CONFIG_FPGA_DELAY ();
  280. if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
  281. puts ("** Timeout waiting for INIT to start.\n");
  282. return FPGA_FAIL;
  283. }
  284. } while (!(*fn->init) (cookie));
  285. /* Get ready for the burn */
  286. CONFIG_FPGA_DELAY ();
  287. (*fn->pgm) (false, true, cookie); /* Deassert the program, commit */
  288. ts = get_timer (0); /* get current time */
  289. /* Now wait for INIT to go high */
  290. do {
  291. CONFIG_FPGA_DELAY ();
  292. if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
  293. puts ("** Timeout waiting for INIT to clear.\n");
  294. return FPGA_FAIL;
  295. }
  296. } while ((*fn->init) (cookie));
  297. /* Load the data */
  298. while (bytecount < bsize) {
  299. /* Xilinx detects an error if INIT goes low (active)
  300. while DONE is low (inactive) */
  301. if ((*fn->done) (cookie) == 0 && (*fn->init) (cookie)) {
  302. puts ("** CRC error during FPGA load.\n");
  303. return (FPGA_FAIL);
  304. }
  305. val = data [bytecount ++];
  306. i = 8;
  307. do {
  308. /* Deassert the clock */
  309. (*fn->clk) (false, true, cookie);
  310. CONFIG_FPGA_DELAY ();
  311. /* Write data */
  312. (*fn->wr) ((val & 0x80), true, cookie);
  313. CONFIG_FPGA_DELAY ();
  314. /* Assert the clock */
  315. (*fn->clk) (true, true, cookie);
  316. CONFIG_FPGA_DELAY ();
  317. val <<= 1;
  318. i --;
  319. } while (i > 0);
  320. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  321. if (bytecount % (bsize / 40) == 0)
  322. putc ('.'); /* let them know we are alive */
  323. #endif
  324. }
  325. CONFIG_FPGA_DELAY ();
  326. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  327. putc ('\n'); /* terminate the dotted line */
  328. #endif
  329. /* now check for done signal */
  330. ts = get_timer (0); /* get current time */
  331. ret_val = FPGA_SUCCESS;
  332. (*fn->wr) (true, true, cookie);
  333. while (! (*fn->done) (cookie)) {
  334. CONFIG_FPGA_DELAY ();
  335. (*fn->clk) (false, true, cookie); /* Deassert the clock pin */
  336. CONFIG_FPGA_DELAY ();
  337. (*fn->clk) (true, true, cookie); /* Assert the clock pin */
  338. putc ('*');
  339. if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
  340. puts ("** Timeout waiting for DONE to clear.\n");
  341. ret_val = FPGA_FAIL;
  342. break;
  343. }
  344. }
  345. putc ('\n'); /* terminate the dotted line */
  346. /*
  347. * Run the post configuration function if there is one.
  348. */
  349. if (*fn->post)
  350. (*fn->post) (cookie);
  351. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  352. if (ret_val == FPGA_SUCCESS)
  353. puts ("Done.\n");
  354. else
  355. puts ("Fail.\n");
  356. #endif
  357. } else {
  358. printf ("%s: NULL Interface function table!\n", __FUNCTION__);
  359. }
  360. return ret_val;
  361. }
  362. static int spartan2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize)
  363. {
  364. /* Readback is only available through the Slave Parallel and */
  365. /* boundary-scan interfaces. */
  366. printf ("%s: Slave Serial Dumping is unavailable\n",
  367. __FUNCTION__);
  368. return FPGA_FAIL;
  369. }
  370. struct xilinx_fpga_op spartan2_op = {
  371. .load = spartan2_load,
  372. .dump = spartan2_dump,
  373. .info = spartan2_info,
  374. };