intel_sdm_mb.c 9.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2018 Intel Corporation <www.intel.com>
  4. */
  5. #include <common.h>
  6. #include <altera.h>
  7. #include <log.h>
  8. #include <watchdog.h>
  9. #include <asm/arch/mailbox_s10.h>
  10. #include <asm/arch/smc_api.h>
  11. #include <linux/delay.h>
  12. #include <linux/intel-smc.h>
  13. #define RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS 60000
  14. #define RECONFIG_STATUS_INTERVAL_DELAY_US 1000000
  15. #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
  16. #define BITSTREAM_CHUNK_SIZE 0xFFFF0
  17. #define RECONFIG_STATUS_POLL_RETRY_MAX 100
  18. /*
  19. * Polling the FPGA configuration status.
  20. * Return 0 for success, non-zero for error.
  21. */
  22. static int reconfig_status_polling_resp(void)
  23. {
  24. int ret;
  25. unsigned long start = get_timer(0);
  26. while (1) {
  27. ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_ISDONE, NULL, 0,
  28. NULL, 0);
  29. if (!ret)
  30. return 0; /* configuration success */
  31. if (ret != INTEL_SIP_SMC_STATUS_BUSY)
  32. return ret;
  33. if (get_timer(start) > RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS)
  34. return -ETIMEDOUT; /* time out */
  35. puts(".");
  36. udelay(RECONFIG_STATUS_INTERVAL_DELAY_US);
  37. WATCHDOG_RESET();
  38. }
  39. return -ETIMEDOUT;
  40. }
  41. static int send_bitstream(const void *rbf_data, size_t rbf_size)
  42. {
  43. int i;
  44. u64 res_buf[3];
  45. u64 args[2];
  46. u32 xfer_count = 0;
  47. int ret, wr_ret = 0, retry = 0;
  48. size_t buf_size = (rbf_size > BITSTREAM_CHUNK_SIZE) ?
  49. BITSTREAM_CHUNK_SIZE : rbf_size;
  50. while (rbf_size || xfer_count) {
  51. if (!wr_ret && rbf_size) {
  52. args[0] = (u64)rbf_data;
  53. args[1] = buf_size;
  54. wr_ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_WRITE,
  55. args, 2, NULL, 0);
  56. debug("wr_ret = %d, rbf_data = %p, buf_size = %08lx\n",
  57. wr_ret, rbf_data, buf_size);
  58. if (wr_ret)
  59. continue;
  60. rbf_size -= buf_size;
  61. rbf_data += buf_size;
  62. if (buf_size >= rbf_size)
  63. buf_size = rbf_size;
  64. xfer_count++;
  65. puts(".");
  66. } else {
  67. ret = invoke_smc(
  68. INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE,
  69. NULL, 0, res_buf, ARRAY_SIZE(res_buf));
  70. if (!ret) {
  71. for (i = 0; i < ARRAY_SIZE(res_buf); i++) {
  72. if (!res_buf[i])
  73. break;
  74. xfer_count--;
  75. wr_ret = 0;
  76. retry = 0;
  77. }
  78. } else if (ret !=
  79. INTEL_SIP_SMC_STATUS_BUSY)
  80. return ret;
  81. else if (!xfer_count)
  82. return INTEL_SIP_SMC_STATUS_ERROR;
  83. if (++retry >= RECONFIG_STATUS_POLL_RETRY_MAX)
  84. return -ETIMEDOUT;
  85. udelay(20000);
  86. }
  87. WATCHDOG_RESET();
  88. }
  89. return 0;
  90. }
  91. /*
  92. * This is the interface used by FPGA driver.
  93. * Return 0 for success, non-zero for error.
  94. */
  95. int intel_sdm_mb_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
  96. {
  97. int ret;
  98. u64 arg = 1;
  99. debug("Invoking FPGA_CONFIG_START...\n");
  100. ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_START, &arg, 1, NULL, 0);
  101. if (ret) {
  102. puts("Failure in RECONFIG mailbox command!\n");
  103. return ret;
  104. }
  105. ret = send_bitstream(rbf_data, rbf_size);
  106. if (ret) {
  107. puts("Error sending bitstream!\n");
  108. return ret;
  109. }
  110. /* Make sure we don't send MBOX_RECONFIG_STATUS too fast */
  111. udelay(RECONFIG_STATUS_INTERVAL_DELAY_US);
  112. debug("Polling with MBOX_RECONFIG_STATUS...\n");
  113. ret = reconfig_status_polling_resp();
  114. if (ret) {
  115. puts("FPGA reconfiguration failed!");
  116. return ret;
  117. }
  118. puts("FPGA reconfiguration OK!\n");
  119. return ret;
  120. }
  121. #else
  122. static const struct mbox_cfgstat_state {
  123. int err_no;
  124. const char *error_name;
  125. } mbox_cfgstat_state[] = {
  126. {MBOX_CFGSTAT_STATE_IDLE, "FPGA in idle mode."},
  127. {MBOX_CFGSTAT_STATE_CONFIG, "FPGA in config mode."},
  128. {MBOX_CFGSTAT_STATE_FAILACK, "Acknowledgment failed!"},
  129. {MBOX_CFGSTAT_STATE_ERROR_INVALID, "Invalid bitstream!"},
  130. {MBOX_CFGSTAT_STATE_ERROR_CORRUPT, "Corrupted bitstream!"},
  131. {MBOX_CFGSTAT_STATE_ERROR_AUTH, "Authentication failed!"},
  132. {MBOX_CFGSTAT_STATE_ERROR_CORE_IO, "I/O error!"},
  133. {MBOX_CFGSTAT_STATE_ERROR_HARDWARE, "Hardware error!"},
  134. {MBOX_CFGSTAT_STATE_ERROR_FAKE, "Fake error!"},
  135. {MBOX_CFGSTAT_STATE_ERROR_BOOT_INFO, "Error in boot info!"},
  136. {MBOX_CFGSTAT_STATE_ERROR_QSPI_ERROR, "Error in QSPI!"},
  137. {MBOX_RESP_ERROR, "Mailbox general error!"},
  138. {-ETIMEDOUT, "I/O timeout error"},
  139. {-1, "Unknown error!"}
  140. };
  141. #define MBOX_CFGSTAT_MAX ARRAY_SIZE(mbox_cfgstat_state)
  142. static const char *mbox_cfgstat_to_str(int err)
  143. {
  144. int i;
  145. for (i = 0; i < MBOX_CFGSTAT_MAX - 1; i++) {
  146. if (mbox_cfgstat_state[i].err_no == err)
  147. return mbox_cfgstat_state[i].error_name;
  148. }
  149. return mbox_cfgstat_state[MBOX_CFGSTAT_MAX - 1].error_name;
  150. }
  151. /*
  152. * Add the ongoing transaction's command ID into pending list and return
  153. * the command ID for next transfer.
  154. */
  155. static u8 add_transfer(u32 *xfer_pending_list, size_t list_size, u8 id)
  156. {
  157. int i;
  158. for (i = 0; i < list_size; i++) {
  159. if (xfer_pending_list[i])
  160. continue;
  161. xfer_pending_list[i] = id;
  162. debug("ID(%d) added to transaction pending list\n", id);
  163. /*
  164. * Increment command ID for next transaction.
  165. * Valid command ID (4 bits) is from 1 to 15.
  166. */
  167. id = (id % 15) + 1;
  168. break;
  169. }
  170. return id;
  171. }
  172. /*
  173. * Check whether response ID match the command ID in the transfer
  174. * pending list. If a match is found in the transfer pending list,
  175. * it clears the transfer pending list and return the matched
  176. * command ID.
  177. */
  178. static int get_and_clr_transfer(u32 *xfer_pending_list, size_t list_size,
  179. u8 id)
  180. {
  181. int i;
  182. for (i = 0; i < list_size; i++) {
  183. if (id != xfer_pending_list[i])
  184. continue;
  185. xfer_pending_list[i] = 0;
  186. return id;
  187. }
  188. return 0;
  189. }
  190. /*
  191. * Polling the FPGA configuration status.
  192. * Return 0 for success, non-zero for error.
  193. */
  194. static int reconfig_status_polling_resp(void)
  195. {
  196. int ret;
  197. unsigned long start = get_timer(0);
  198. while (1) {
  199. ret = mbox_get_fpga_config_status(MBOX_RECONFIG_STATUS);
  200. if (!ret)
  201. return 0; /* configuration success */
  202. if (ret != MBOX_CFGSTAT_STATE_CONFIG)
  203. return ret;
  204. if (get_timer(start) > RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS)
  205. break; /* time out */
  206. puts(".");
  207. udelay(RECONFIG_STATUS_INTERVAL_DELAY_US);
  208. WATCHDOG_RESET();
  209. }
  210. return -ETIMEDOUT;
  211. }
  212. static u32 get_resp_hdr(u32 *r_index, u32 *w_index, u32 *resp_count,
  213. u32 *resp_buf, u32 buf_size, u32 client_id)
  214. {
  215. u32 buf[MBOX_RESP_BUFFER_SIZE];
  216. u32 mbox_hdr;
  217. u32 resp_len;
  218. u32 hdr_len;
  219. u32 i;
  220. if (*resp_count < buf_size) {
  221. u32 rcv_len_max = buf_size - *resp_count;
  222. if (rcv_len_max > MBOX_RESP_BUFFER_SIZE)
  223. rcv_len_max = MBOX_RESP_BUFFER_SIZE;
  224. resp_len = mbox_rcv_resp(buf, rcv_len_max);
  225. for (i = 0; i < resp_len; i++) {
  226. resp_buf[(*w_index)++] = buf[i];
  227. *w_index %= buf_size;
  228. (*resp_count)++;
  229. }
  230. }
  231. /* No response in buffer */
  232. if (*resp_count == 0)
  233. return 0;
  234. mbox_hdr = resp_buf[*r_index];
  235. hdr_len = MBOX_RESP_LEN_GET(mbox_hdr);
  236. /* Insufficient header length to return a mailbox header */
  237. if ((*resp_count - 1) < hdr_len)
  238. return 0;
  239. *r_index += (hdr_len + 1);
  240. *r_index %= buf_size;
  241. *resp_count -= (hdr_len + 1);
  242. /* Make sure response belongs to us */
  243. if (MBOX_RESP_CLIENT_GET(mbox_hdr) != client_id)
  244. return 0;
  245. return mbox_hdr;
  246. }
  247. /* Send bit stream data to SDM via RECONFIG_DATA mailbox command */
  248. static int send_reconfig_data(const void *rbf_data, size_t rbf_size,
  249. u32 xfer_max, u32 buf_size_max)
  250. {
  251. u32 response_buffer[MBOX_RESP_BUFFER_SIZE];
  252. u32 xfer_pending[MBOX_RESP_BUFFER_SIZE];
  253. u32 resp_rindex = 0;
  254. u32 resp_windex = 0;
  255. u32 resp_count = 0;
  256. u32 xfer_count = 0;
  257. int resp_err = 0;
  258. u8 cmd_id = 1;
  259. u32 args[3];
  260. int ret;
  261. debug("SDM xfer_max = %d\n", xfer_max);
  262. debug("SDM buf_size_max = %x\n\n", buf_size_max);
  263. memset(xfer_pending, 0, sizeof(xfer_pending));
  264. while (rbf_size || xfer_count) {
  265. if (!resp_err && rbf_size && xfer_count < xfer_max) {
  266. args[0] = MBOX_ARG_DESC_COUNT(1);
  267. args[1] = (u64)rbf_data;
  268. if (rbf_size >= buf_size_max) {
  269. args[2] = buf_size_max;
  270. rbf_size -= buf_size_max;
  271. rbf_data += buf_size_max;
  272. } else {
  273. args[2] = (u64)rbf_size;
  274. rbf_size = 0;
  275. }
  276. resp_err = mbox_send_cmd_only(cmd_id, MBOX_RECONFIG_DATA,
  277. MBOX_CMD_INDIRECT, 3, args);
  278. if (!resp_err) {
  279. xfer_count++;
  280. cmd_id = add_transfer(xfer_pending,
  281. MBOX_RESP_BUFFER_SIZE,
  282. cmd_id);
  283. }
  284. puts(".");
  285. } else {
  286. u32 resp_hdr = get_resp_hdr(&resp_rindex, &resp_windex,
  287. &resp_count,
  288. response_buffer,
  289. MBOX_RESP_BUFFER_SIZE,
  290. MBOX_CLIENT_ID_UBOOT);
  291. /*
  292. * If no valid response header found or
  293. * non-zero length from RECONFIG_DATA
  294. */
  295. if (!resp_hdr || MBOX_RESP_LEN_GET(resp_hdr))
  296. continue;
  297. /* Check for response's status */
  298. if (!resp_err) {
  299. resp_err = MBOX_RESP_ERR_GET(resp_hdr);
  300. debug("Response error code: %08x\n", resp_err);
  301. }
  302. ret = get_and_clr_transfer(xfer_pending,
  303. MBOX_RESP_BUFFER_SIZE,
  304. MBOX_RESP_ID_GET(resp_hdr));
  305. if (ret) {
  306. /* Claim and reuse the ID */
  307. cmd_id = (u8)ret;
  308. xfer_count--;
  309. }
  310. if (resp_err && !xfer_count)
  311. return resp_err;
  312. }
  313. WATCHDOG_RESET();
  314. }
  315. return 0;
  316. }
  317. /*
  318. * This is the interface used by FPGA driver.
  319. * Return 0 for success, non-zero for error.
  320. */
  321. int intel_sdm_mb_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
  322. {
  323. int ret;
  324. u32 resp_len = 2;
  325. u32 resp_buf[2];
  326. debug("Sending MBOX_RECONFIG...\n");
  327. ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_RECONFIG, MBOX_CMD_DIRECT, 0,
  328. NULL, 0, &resp_len, resp_buf);
  329. if (ret) {
  330. puts("Failure in RECONFIG mailbox command!\n");
  331. return ret;
  332. }
  333. ret = send_reconfig_data(rbf_data, rbf_size, resp_buf[0], resp_buf[1]);
  334. if (ret) {
  335. printf("RECONFIG_DATA error: %08x, %s\n", ret,
  336. mbox_cfgstat_to_str(ret));
  337. return ret;
  338. }
  339. /* Make sure we don't send MBOX_RECONFIG_STATUS too fast */
  340. udelay(RECONFIG_STATUS_INTERVAL_DELAY_US);
  341. debug("Polling with MBOX_RECONFIG_STATUS...\n");
  342. ret = reconfig_status_polling_resp();
  343. if (ret) {
  344. printf("RECONFIG_STATUS Error: %08x, %s\n", ret,
  345. mbox_cfgstat_to_str(ret));
  346. return ret;
  347. }
  348. puts("FPGA reconfiguration OK!\n");
  349. return ret;
  350. }
  351. #endif