ti_sci.h 56 KB

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  1. /* SPDX-License-Identifier: BSD-3-Clause */
  2. /*
  3. * Texas Instruments System Control Interface (TISCI) Protocol
  4. *
  5. * Communication protocol with TI SCI hardware
  6. * The system works in a message response protocol
  7. * See: http://processors.wiki.ti.com/index.php/TISCI for details
  8. *
  9. * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
  10. * Based on drivers/firmware/ti_sci.h from Linux.
  11. *
  12. */
  13. #ifndef __TI_SCI_H
  14. #define __TI_SCI_H
  15. /* Generic Messages */
  16. #include <linux/bitops.h>
  17. #define TI_SCI_MSG_ENABLE_WDT 0x0000
  18. #define TI_SCI_MSG_WAKE_RESET 0x0001
  19. #define TI_SCI_MSG_VERSION 0x0002
  20. #define TI_SCI_MSG_WAKE_REASON 0x0003
  21. #define TI_SCI_MSG_GOODBYE 0x0004
  22. #define TI_SCI_MSG_SYS_RESET 0x0005
  23. #define TI_SCI_MSG_BOARD_CONFIG 0x000b
  24. #define TI_SCI_MSG_BOARD_CONFIG_RM 0x000c
  25. #define TI_SCI_MSG_BOARD_CONFIG_SECURITY 0x000d
  26. #define TI_SCI_MSG_BOARD_CONFIG_PM 0x000e
  27. #define TISCI_MSG_QUERY_MSMC 0x0020
  28. /* Device requests */
  29. #define TI_SCI_MSG_SET_DEVICE_STATE 0x0200
  30. #define TI_SCI_MSG_GET_DEVICE_STATE 0x0201
  31. #define TI_SCI_MSG_SET_DEVICE_RESETS 0x0202
  32. /* Clock requests */
  33. #define TI_SCI_MSG_SET_CLOCK_STATE 0x0100
  34. #define TI_SCI_MSG_GET_CLOCK_STATE 0x0101
  35. #define TI_SCI_MSG_SET_CLOCK_PARENT 0x0102
  36. #define TI_SCI_MSG_GET_CLOCK_PARENT 0x0103
  37. #define TI_SCI_MSG_GET_NUM_CLOCK_PARENTS 0x0104
  38. #define TI_SCI_MSG_SET_CLOCK_FREQ 0x010c
  39. #define TI_SCI_MSG_QUERY_CLOCK_FREQ 0x010d
  40. #define TI_SCI_MSG_GET_CLOCK_FREQ 0x010e
  41. /* Processor Control Messages */
  42. #define TISCI_MSG_PROC_REQUEST 0xc000
  43. #define TISCI_MSG_PROC_RELEASE 0xc001
  44. #define TISCI_MSG_PROC_HANDOVER 0xc005
  45. #define TISCI_MSG_SET_PROC_BOOT_CONFIG 0xc100
  46. #define TISCI_MSG_SET_PROC_BOOT_CTRL 0xc101
  47. #define TISCI_MSG_PROC_AUTH_BOOT_IMIAGE 0xc120
  48. #define TISCI_MSG_GET_PROC_BOOT_STATUS 0xc400
  49. #define TISCI_MSG_WAIT_PROC_BOOT_STATUS 0xc401
  50. /* Resource Management Requests */
  51. #define TI_SCI_MSG_GET_RESOURCE_RANGE 0x1500
  52. /* NAVSS resource management */
  53. /* Ringacc requests */
  54. #define TI_SCI_MSG_RM_RING_CFG 0x1110
  55. /* PSI-L requests */
  56. #define TI_SCI_MSG_RM_PSIL_PAIR 0x1280
  57. #define TI_SCI_MSG_RM_PSIL_UNPAIR 0x1281
  58. #define TI_SCI_MSG_RM_UDMAP_TX_ALLOC 0x1200
  59. #define TI_SCI_MSG_RM_UDMAP_TX_FREE 0x1201
  60. #define TI_SCI_MSG_RM_UDMAP_RX_ALLOC 0x1210
  61. #define TI_SCI_MSG_RM_UDMAP_RX_FREE 0x1211
  62. #define TI_SCI_MSG_RM_UDMAP_FLOW_CFG 0x1220
  63. #define TI_SCI_MSG_RM_UDMAP_OPT_FLOW_CFG 0x1221
  64. #define TISCI_MSG_RM_UDMAP_TX_CH_CFG 0x1205
  65. #define TISCI_MSG_RM_UDMAP_RX_CH_CFG 0x1215
  66. #define TISCI_MSG_RM_UDMAP_FLOW_CFG 0x1230
  67. #define TISCI_MSG_RM_UDMAP_FLOW_SIZE_THRESH_CFG 0x1231
  68. #define TISCI_MSG_FWL_SET 0x9000
  69. #define TISCI_MSG_FWL_GET 0x9001
  70. #define TISCI_MSG_FWL_CHANGE_OWNER 0x9002
  71. /**
  72. * struct ti_sci_msg_hdr - Generic Message Header for All messages and responses
  73. * @type: Type of messages: One of TI_SCI_MSG* values
  74. * @host: Host of the message
  75. * @seq: Message identifier indicating a transfer sequence
  76. * @flags: Flag for the message
  77. */
  78. struct ti_sci_msg_hdr {
  79. u16 type;
  80. u8 host;
  81. u8 seq;
  82. #define TI_SCI_MSG_FLAG(val) (1 << (val))
  83. #define TI_SCI_FLAG_REQ_GENERIC_NORESPONSE 0x0
  84. #define TI_SCI_FLAG_REQ_ACK_ON_RECEIVED TI_SCI_MSG_FLAG(0)
  85. #define TI_SCI_FLAG_REQ_ACK_ON_PROCESSED TI_SCI_MSG_FLAG(1)
  86. #define TI_SCI_FLAG_RESP_GENERIC_NACK 0x0
  87. #define TI_SCI_FLAG_RESP_GENERIC_ACK TI_SCI_MSG_FLAG(1)
  88. /* Additional Flags */
  89. u32 flags;
  90. } __packed;
  91. /**
  92. * struct ti_sci_secure_msg_hdr - Header that prefixes all TISCI messages sent
  93. * via secure transport.
  94. * @checksum: crc16 checksum for the entire message
  95. * @reserved: Reserved for future use.
  96. */
  97. struct ti_sci_secure_msg_hdr {
  98. u16 checksum;
  99. u16 reserved;
  100. } __packed;
  101. /**
  102. * struct ti_sci_msg_resp_version - Response for a message
  103. * @hdr: Generic header
  104. * @firmware_description: String describing the firmware
  105. * @firmware_revision: Firmware revision
  106. * @abi_major: Major version of the ABI that firmware supports
  107. * @abi_minor: Minor version of the ABI that firmware supports
  108. *
  109. * In general, ABI version changes follow the rule that minor version increments
  110. * are backward compatible. Major revision changes in ABI may not be
  111. * backward compatible.
  112. *
  113. * Response to a generic message with message type TI_SCI_MSG_VERSION
  114. */
  115. struct ti_sci_msg_resp_version {
  116. struct ti_sci_msg_hdr hdr;
  117. char firmware_description[32];
  118. u16 firmware_revision;
  119. u8 abi_major;
  120. u8 abi_minor;
  121. } __packed;
  122. /**
  123. * struct ti_sci_msg_req_reboot - Reboot the SoC
  124. * @hdr: Generic Header
  125. * @domain: Domain to be reset, 0 for full SoC reboot.
  126. *
  127. * Request type is TI_SCI_MSG_SYS_RESET, responded with a generic
  128. * ACK/NACK message.
  129. */
  130. struct ti_sci_msg_req_reboot {
  131. struct ti_sci_msg_hdr hdr;
  132. u8 domain;
  133. } __packed;
  134. /**
  135. * struct ti_sci_msg_board_config - Board configuration message
  136. * @hdr: Generic Header
  137. * @boardcfgp_low: Lower 32 bit of the pointer pointing to the board
  138. * configuration data
  139. * @boardcfgp_high: Upper 32 bit of the pointer pointing to the board
  140. * configuration data
  141. * @boardcfg_size: Size of board configuration data object
  142. * Request type is TI_SCI_MSG_BOARD_CONFIG, responded with a generic
  143. * ACK/NACK message.
  144. */
  145. struct ti_sci_msg_board_config {
  146. struct ti_sci_msg_hdr hdr;
  147. u32 boardcfgp_low;
  148. u32 boardcfgp_high;
  149. u16 boardcfg_size;
  150. } __packed;
  151. /**
  152. * struct ti_sci_msg_resp_query_msmc - Query msmc message response structure
  153. * @hdr: Generic Header
  154. * @msmc_start_low: Lower 32 bit of msmc start
  155. * @msmc_start_high: Upper 32 bit of msmc start
  156. * @msmc_end_low: Lower 32 bit of msmc end
  157. * @msmc_end_high: Upper 32 bit of msmc end
  158. *
  159. * Response to a generic message with message type TISCI_MSG_QUERY_MSMC
  160. */
  161. struct ti_sci_msg_resp_query_msmc {
  162. struct ti_sci_msg_hdr hdr;
  163. u32 msmc_start_low;
  164. u32 msmc_start_high;
  165. u32 msmc_end_low;
  166. u32 msmc_end_high;
  167. } __packed;
  168. /**
  169. * struct ti_sci_msg_req_set_device_state - Set the desired state of the device
  170. * @hdr: Generic header
  171. * @id: Indicates which device to modify
  172. * @reserved: Reserved space in message, must be 0 for backward compatibility
  173. * @state: The desired state of the device.
  174. *
  175. * Certain flags can also be set to alter the device state:
  176. * + MSG_FLAG_DEVICE_WAKE_ENABLED - Configure the device to be a wake source.
  177. * The meaning of this flag will vary slightly from device to device and from
  178. * SoC to SoC but it generally allows the device to wake the SoC out of deep
  179. * suspend states.
  180. * + MSG_FLAG_DEVICE_RESET_ISO - Enable reset isolation for this device.
  181. * + MSG_FLAG_DEVICE_EXCLUSIVE - Claim this device exclusively. When passed
  182. * with STATE_RETENTION or STATE_ON, it will claim the device exclusively.
  183. * If another host already has this device set to STATE_RETENTION or STATE_ON,
  184. * the message will fail. Once successful, other hosts attempting to set
  185. * STATE_RETENTION or STATE_ON will fail.
  186. *
  187. * Request type is TI_SCI_MSG_SET_DEVICE_STATE, responded with a generic
  188. * ACK/NACK message.
  189. */
  190. struct ti_sci_msg_req_set_device_state {
  191. /* Additional hdr->flags options */
  192. #define MSG_FLAG_DEVICE_WAKE_ENABLED TI_SCI_MSG_FLAG(8)
  193. #define MSG_FLAG_DEVICE_RESET_ISO TI_SCI_MSG_FLAG(9)
  194. #define MSG_FLAG_DEVICE_EXCLUSIVE TI_SCI_MSG_FLAG(10)
  195. struct ti_sci_msg_hdr hdr;
  196. u32 id;
  197. u32 reserved;
  198. #define MSG_DEVICE_SW_STATE_AUTO_OFF 0
  199. #define MSG_DEVICE_SW_STATE_RETENTION 1
  200. #define MSG_DEVICE_SW_STATE_ON 2
  201. u8 state;
  202. } __packed;
  203. /**
  204. * struct ti_sci_msg_req_get_device_state - Request to get device.
  205. * @hdr: Generic header
  206. * @id: Device Identifier
  207. *
  208. * Request type is TI_SCI_MSG_GET_DEVICE_STATE, responded device state
  209. * information
  210. */
  211. struct ti_sci_msg_req_get_device_state {
  212. struct ti_sci_msg_hdr hdr;
  213. u32 id;
  214. } __packed;
  215. /**
  216. * struct ti_sci_msg_resp_get_device_state - Response to get device request.
  217. * @hdr: Generic header
  218. * @context_loss_count: Indicates how many times the device has lost context. A
  219. * driver can use this monotonic counter to determine if the device has
  220. * lost context since the last time this message was exchanged.
  221. * @resets: Programmed state of the reset lines.
  222. * @programmed_state: The state as programmed by set_device.
  223. * - Uses the MSG_DEVICE_SW_* macros
  224. * @current_state: The actual state of the hardware.
  225. *
  226. * Response to request TI_SCI_MSG_GET_DEVICE_STATE.
  227. */
  228. struct ti_sci_msg_resp_get_device_state {
  229. struct ti_sci_msg_hdr hdr;
  230. u32 context_loss_count;
  231. u32 resets;
  232. u8 programmed_state;
  233. #define MSG_DEVICE_HW_STATE_OFF 0
  234. #define MSG_DEVICE_HW_STATE_ON 1
  235. #define MSG_DEVICE_HW_STATE_TRANS 2
  236. u8 current_state;
  237. } __packed;
  238. /**
  239. * struct ti_sci_msg_req_set_device_resets - Set the desired resets
  240. * configuration of the device
  241. * @hdr: Generic header
  242. * @id: Indicates which device to modify
  243. * @resets: A bit field of resets for the device. The meaning, behavior,
  244. * and usage of the reset flags are device specific. 0 for a bit
  245. * indicates releasing the reset represented by that bit while 1
  246. * indicates keeping it held.
  247. *
  248. * Request type is TI_SCI_MSG_SET_DEVICE_RESETS, responded with a generic
  249. * ACK/NACK message.
  250. */
  251. struct ti_sci_msg_req_set_device_resets {
  252. struct ti_sci_msg_hdr hdr;
  253. u32 id;
  254. u32 resets;
  255. } __packed;
  256. /**
  257. * struct ti_sci_msg_req_set_clock_state - Request to setup a Clock state
  258. * @hdr: Generic Header, Certain flags can be set specific to the clocks:
  259. * MSG_FLAG_CLOCK_ALLOW_SSC: Allow this clock to be modified
  260. * via spread spectrum clocking.
  261. * MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE: Allow this clock's
  262. * frequency to be changed while it is running so long as it
  263. * is within the min/max limits.
  264. * MSG_FLAG_CLOCK_INPUT_TERM: Enable input termination, this
  265. * is only applicable to clock inputs on the SoC pseudo-device.
  266. * @dev_id: Device identifier this request is for
  267. * @clk_id: Clock identifier for the device for this request.
  268. * Each device has it's own set of clock inputs. This indexes
  269. * which clock input to modify.
  270. * @request_state: Request the state for the clock to be set to.
  271. * MSG_CLOCK_SW_STATE_UNREQ: The IP does not require this clock,
  272. * it can be disabled, regardless of the state of the device
  273. * MSG_CLOCK_SW_STATE_AUTO: Allow the System Controller to
  274. * automatically manage the state of this clock. If the device
  275. * is enabled, then the clock is enabled. If the device is set
  276. * to off or retention, then the clock is internally set as not
  277. * being required by the device.(default)
  278. * MSG_CLOCK_SW_STATE_REQ: Configure the clock to be enabled,
  279. * regardless of the state of the device.
  280. *
  281. * Normally, all required clocks are managed by TISCI entity, this is used
  282. * only for specific control *IF* required. Auto managed state is
  283. * MSG_CLOCK_SW_STATE_AUTO, in other states, TISCI entity assume remote
  284. * will explicitly control.
  285. *
  286. * Request type is TI_SCI_MSG_SET_CLOCK_STATE, response is a generic
  287. * ACK or NACK message.
  288. */
  289. struct ti_sci_msg_req_set_clock_state {
  290. /* Additional hdr->flags options */
  291. #define MSG_FLAG_CLOCK_ALLOW_SSC TI_SCI_MSG_FLAG(8)
  292. #define MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE TI_SCI_MSG_FLAG(9)
  293. #define MSG_FLAG_CLOCK_INPUT_TERM TI_SCI_MSG_FLAG(10)
  294. struct ti_sci_msg_hdr hdr;
  295. u32 dev_id;
  296. u8 clk_id;
  297. #define MSG_CLOCK_SW_STATE_UNREQ 0
  298. #define MSG_CLOCK_SW_STATE_AUTO 1
  299. #define MSG_CLOCK_SW_STATE_REQ 2
  300. u8 request_state;
  301. } __packed;
  302. /**
  303. * struct ti_sci_msg_req_get_clock_state - Request for clock state
  304. * @hdr: Generic Header
  305. * @dev_id: Device identifier this request is for
  306. * @clk_id: Clock identifier for the device for this request.
  307. * Each device has it's own set of clock inputs. This indexes
  308. * which clock input to get state of.
  309. *
  310. * Request type is TI_SCI_MSG_GET_CLOCK_STATE, response is state
  311. * of the clock
  312. */
  313. struct ti_sci_msg_req_get_clock_state {
  314. struct ti_sci_msg_hdr hdr;
  315. u32 dev_id;
  316. u8 clk_id;
  317. } __packed;
  318. /**
  319. * struct ti_sci_msg_resp_get_clock_state - Response to get clock state
  320. * @hdr: Generic Header
  321. * @programmed_state: Any programmed state of the clock. This is one of
  322. * MSG_CLOCK_SW_STATE* values.
  323. * @current_state: Current state of the clock. This is one of:
  324. * MSG_CLOCK_HW_STATE_NOT_READY: Clock is not ready
  325. * MSG_CLOCK_HW_STATE_READY: Clock is ready
  326. *
  327. * Response to TI_SCI_MSG_GET_CLOCK_STATE.
  328. */
  329. struct ti_sci_msg_resp_get_clock_state {
  330. struct ti_sci_msg_hdr hdr;
  331. u8 programmed_state;
  332. #define MSG_CLOCK_HW_STATE_NOT_READY 0
  333. #define MSG_CLOCK_HW_STATE_READY 1
  334. u8 current_state;
  335. } __packed;
  336. /**
  337. * struct ti_sci_msg_req_set_clock_parent - Set the clock parent
  338. * @hdr: Generic Header
  339. * @dev_id: Device identifier this request is for
  340. * @clk_id: Clock identifier for the device for this request.
  341. * Each device has it's own set of clock inputs. This indexes
  342. * which clock input to modify.
  343. * @parent_id: The new clock parent is selectable by an index via this
  344. * parameter.
  345. *
  346. * Request type is TI_SCI_MSG_SET_CLOCK_PARENT, response is generic
  347. * ACK / NACK message.
  348. */
  349. struct ti_sci_msg_req_set_clock_parent {
  350. struct ti_sci_msg_hdr hdr;
  351. u32 dev_id;
  352. u8 clk_id;
  353. u8 parent_id;
  354. } __packed;
  355. /**
  356. * struct ti_sci_msg_req_get_clock_parent - Get the clock parent
  357. * @hdr: Generic Header
  358. * @dev_id: Device identifier this request is for
  359. * @clk_id: Clock identifier for the device for this request.
  360. * Each device has it's own set of clock inputs. This indexes
  361. * which clock input to get the parent for.
  362. *
  363. * Request type is TI_SCI_MSG_GET_CLOCK_PARENT, response is parent information
  364. */
  365. struct ti_sci_msg_req_get_clock_parent {
  366. struct ti_sci_msg_hdr hdr;
  367. u32 dev_id;
  368. u8 clk_id;
  369. } __packed;
  370. /**
  371. * struct ti_sci_msg_resp_get_clock_parent - Response with clock parent
  372. * @hdr: Generic Header
  373. * @parent_id: The current clock parent
  374. *
  375. * Response to TI_SCI_MSG_GET_CLOCK_PARENT.
  376. */
  377. struct ti_sci_msg_resp_get_clock_parent {
  378. struct ti_sci_msg_hdr hdr;
  379. u8 parent_id;
  380. } __packed;
  381. /**
  382. * struct ti_sci_msg_req_get_clock_num_parents - Request to get clock parents
  383. * @hdr: Generic header
  384. * @dev_id: Device identifier this request is for
  385. * @clk_id: Clock identifier for the device for this request.
  386. *
  387. * This request provides information about how many clock parent options
  388. * are available for a given clock to a device. This is typically used
  389. * for input clocks.
  390. *
  391. * Request type is TI_SCI_MSG_GET_NUM_CLOCK_PARENTS, response is appropriate
  392. * message, or NACK in case of inability to satisfy request.
  393. */
  394. struct ti_sci_msg_req_get_clock_num_parents {
  395. struct ti_sci_msg_hdr hdr;
  396. u32 dev_id;
  397. u8 clk_id;
  398. } __packed;
  399. /**
  400. * struct ti_sci_msg_resp_get_clock_num_parents - Response for get clk parents
  401. * @hdr: Generic header
  402. * @num_parents: Number of clock parents
  403. *
  404. * Response to TI_SCI_MSG_GET_NUM_CLOCK_PARENTS
  405. */
  406. struct ti_sci_msg_resp_get_clock_num_parents {
  407. struct ti_sci_msg_hdr hdr;
  408. u8 num_parents;
  409. } __packed;
  410. /**
  411. * struct ti_sci_msg_req_query_clock_freq - Request to query a frequency
  412. * @hdr: Generic Header
  413. * @dev_id: Device identifier this request is for
  414. * @min_freq_hz: The minimum allowable frequency in Hz. This is the minimum
  415. * allowable programmed frequency and does not account for clock
  416. * tolerances and jitter.
  417. * @target_freq_hz: The target clock frequency. A frequency will be found
  418. * as close to this target frequency as possible.
  419. * @max_freq_hz: The maximum allowable frequency in Hz. This is the maximum
  420. * allowable programmed frequency and does not account for clock
  421. * tolerances and jitter.
  422. * @clk_id: Clock identifier for the device for this request.
  423. *
  424. * NOTE: Normally clock frequency management is automatically done by TISCI
  425. * entity. In case of specific requests, TISCI evaluates capability to achieve
  426. * requested frequency within provided range and responds with
  427. * result message.
  428. *
  429. * Request type is TI_SCI_MSG_QUERY_CLOCK_FREQ, response is appropriate message,
  430. * or NACK in case of inability to satisfy request.
  431. */
  432. struct ti_sci_msg_req_query_clock_freq {
  433. struct ti_sci_msg_hdr hdr;
  434. u32 dev_id;
  435. u64 min_freq_hz;
  436. u64 target_freq_hz;
  437. u64 max_freq_hz;
  438. u8 clk_id;
  439. } __packed;
  440. /**
  441. * struct ti_sci_msg_resp_query_clock_freq - Response to a clock frequency query
  442. * @hdr: Generic Header
  443. * @freq_hz: Frequency that is the best match in Hz.
  444. *
  445. * Response to request type TI_SCI_MSG_QUERY_CLOCK_FREQ. NOTE: if the request
  446. * cannot be satisfied, the message will be of type NACK.
  447. */
  448. struct ti_sci_msg_resp_query_clock_freq {
  449. struct ti_sci_msg_hdr hdr;
  450. u64 freq_hz;
  451. } __packed;
  452. /**
  453. * struct ti_sci_msg_req_set_clock_freq - Request to setup a clock frequency
  454. * @hdr: Generic Header
  455. * @dev_id: Device identifier this request is for
  456. * @min_freq_hz: The minimum allowable frequency in Hz. This is the minimum
  457. * allowable programmed frequency and does not account for clock
  458. * tolerances and jitter.
  459. * @target_freq_hz: The target clock frequency. The clock will be programmed
  460. * at a rate as close to this target frequency as possible.
  461. * @max_freq_hz: The maximum allowable frequency in Hz. This is the maximum
  462. * allowable programmed frequency and does not account for clock
  463. * tolerances and jitter.
  464. * @clk_id: Clock identifier for the device for this request.
  465. *
  466. * NOTE: Normally clock frequency management is automatically done by TISCI
  467. * entity. In case of specific requests, TISCI evaluates capability to achieve
  468. * requested range and responds with success/failure message.
  469. *
  470. * This sets the desired frequency for a clock within an allowable
  471. * range. This message will fail on an enabled clock unless
  472. * MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE is set for the clock. Additionally,
  473. * if other clocks have their frequency modified due to this message,
  474. * they also must have the MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE or be disabled.
  475. *
  476. * Calling set frequency on a clock input to the SoC pseudo-device will
  477. * inform the PMMC of that clock's frequency. Setting a frequency of
  478. * zero will indicate the clock is disabled.
  479. *
  480. * Calling set frequency on clock outputs from the SoC pseudo-device will
  481. * function similarly to setting the clock frequency on a device.
  482. *
  483. * Request type is TI_SCI_MSG_SET_CLOCK_FREQ, response is a generic ACK/NACK
  484. * message.
  485. */
  486. struct ti_sci_msg_req_set_clock_freq {
  487. struct ti_sci_msg_hdr hdr;
  488. u32 dev_id;
  489. u64 min_freq_hz;
  490. u64 target_freq_hz;
  491. u64 max_freq_hz;
  492. u8 clk_id;
  493. } __packed;
  494. /**
  495. * struct ti_sci_msg_req_get_clock_freq - Request to get the clock frequency
  496. * @hdr: Generic Header
  497. * @dev_id: Device identifier this request is for
  498. * @clk_id: Clock identifier for the device for this request.
  499. *
  500. * NOTE: Normally clock frequency management is automatically done by TISCI
  501. * entity. In some cases, clock frequencies are configured by host.
  502. *
  503. * Request type is TI_SCI_MSG_GET_CLOCK_FREQ, responded with clock frequency
  504. * that the clock is currently at.
  505. */
  506. struct ti_sci_msg_req_get_clock_freq {
  507. struct ti_sci_msg_hdr hdr;
  508. u32 dev_id;
  509. u8 clk_id;
  510. } __packed;
  511. /**
  512. * struct ti_sci_msg_resp_get_clock_freq - Response of clock frequency request
  513. * @hdr: Generic Header
  514. * @freq_hz: Frequency that the clock is currently on, in Hz.
  515. *
  516. * Response to request type TI_SCI_MSG_GET_CLOCK_FREQ.
  517. */
  518. struct ti_sci_msg_resp_get_clock_freq {
  519. struct ti_sci_msg_hdr hdr;
  520. u64 freq_hz;
  521. } __packed;
  522. #define TI_SCI_IRQ_SECONDARY_HOST_INVALID 0xff
  523. /**
  524. * struct ti_sci_msg_req_get_resource_range - Request to get a host's assigned
  525. * range of resources.
  526. * @hdr: Generic Header
  527. * @type: Unique resource assignment type
  528. * @subtype: Resource assignment subtype within the resource type.
  529. * @secondary_host: Host processing entity to which the resources are
  530. * allocated. This is required only when the destination
  531. * host id id different from ti sci interface host id,
  532. * else TI_SCI_IRQ_SECONDARY_HOST_INVALID can be passed.
  533. *
  534. * Request type is TI_SCI_MSG_GET_RESOURCE_RANGE. Responded with requested
  535. * resource range which is of type TI_SCI_MSG_GET_RESOURCE_RANGE.
  536. */
  537. struct ti_sci_msg_req_get_resource_range {
  538. struct ti_sci_msg_hdr hdr;
  539. #define MSG_RM_RESOURCE_TYPE_MASK GENMASK(9, 0)
  540. #define MSG_RM_RESOURCE_SUBTYPE_MASK GENMASK(5, 0)
  541. u16 type;
  542. u8 subtype;
  543. u8 secondary_host;
  544. } __packed;
  545. /**
  546. * struct ti_sci_msg_resp_get_resource_range - Response to resource get range.
  547. * @hdr: Generic Header
  548. * @range_start: Start index of the resource range.
  549. * @range_num: Number of resources in the range.
  550. *
  551. * Response to request TI_SCI_MSG_GET_RESOURCE_RANGE.
  552. */
  553. struct ti_sci_msg_resp_get_resource_range {
  554. struct ti_sci_msg_hdr hdr;
  555. u16 range_start;
  556. u16 range_num;
  557. } __packed;
  558. #define TISCI_ADDR_LOW_MASK GENMASK_ULL(31, 0)
  559. #define TISCI_ADDR_HIGH_MASK GENMASK_ULL(63, 32)
  560. #define TISCI_ADDR_HIGH_SHIFT 32
  561. /**
  562. * struct ti_sci_msg_req_proc_request - Request a processor
  563. *
  564. * @hdr: Generic Header
  565. * @processor_id: ID of processor
  566. *
  567. * Request type is TISCI_MSG_PROC_REQUEST, response is a generic ACK/NACK
  568. * message.
  569. */
  570. struct ti_sci_msg_req_proc_request {
  571. struct ti_sci_msg_hdr hdr;
  572. u8 processor_id;
  573. } __packed;
  574. /**
  575. * struct ti_sci_msg_req_proc_release - Release a processor
  576. *
  577. * @hdr: Generic Header
  578. * @processor_id: ID of processor
  579. *
  580. * Request type is TISCI_MSG_PROC_RELEASE, response is a generic ACK/NACK
  581. * message.
  582. */
  583. struct ti_sci_msg_req_proc_release {
  584. struct ti_sci_msg_hdr hdr;
  585. u8 processor_id;
  586. } __packed;
  587. /**
  588. * struct ti_sci_msg_req_proc_handover - Handover a processor to a host
  589. *
  590. * @hdr: Generic Header
  591. * @processor_id: ID of processor
  592. * @host_id: New Host we want to give control to
  593. *
  594. * Request type is TISCI_MSG_PROC_HANDOVER, response is a generic ACK/NACK
  595. * message.
  596. */
  597. struct ti_sci_msg_req_proc_handover {
  598. struct ti_sci_msg_hdr hdr;
  599. u8 processor_id;
  600. u8 host_id;
  601. } __packed;
  602. /* A53 Config Flags */
  603. #define PROC_BOOT_CFG_FLAG_ARMV8_DBG_EN 0x00000001
  604. #define PROC_BOOT_CFG_FLAG_ARMV8_DBG_NIDEN 0x00000002
  605. #define PROC_BOOT_CFG_FLAG_ARMV8_DBG_SPIDEN 0x00000004
  606. #define PROC_BOOT_CFG_FLAG_ARMV8_DBG_SPNIDEN 0x00000008
  607. #define PROC_BOOT_CFG_FLAG_ARMV8_AARCH32 0x00000100
  608. /* R5 Config Flags */
  609. #define PROC_BOOT_CFG_FLAG_R5_DBG_EN 0x00000001
  610. #define PROC_BOOT_CFG_FLAG_R5_DBG_NIDEN 0x00000002
  611. #define PROC_BOOT_CFG_FLAG_R5_LOCKSTEP 0x00000100
  612. #define PROC_BOOT_CFG_FLAG_R5_TEINIT 0x00000200
  613. #define PROC_BOOT_CFG_FLAG_R5_NMFI_EN 0x00000400
  614. #define PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE 0x00000800
  615. #define PROC_BOOT_CFG_FLAG_R5_BTCM_EN 0x00001000
  616. #define PROC_BOOT_CFG_FLAG_R5_ATCM_EN 0x00002000
  617. /**
  618. * struct ti_sci_msg_req_set_proc_boot_config - Set Processor boot configuration
  619. * @hdr: Generic Header
  620. * @processor_id: ID of processor
  621. * @bootvector_low: Lower 32bit (Little Endian) of boot vector
  622. * @bootvector_high: Higher 32bit (Little Endian) of boot vector
  623. * @config_flags_set: Optional Processor specific Config Flags to set.
  624. * Setting a bit here implies required bit sets to 1.
  625. * @config_flags_clear: Optional Processor specific Config Flags to clear.
  626. * Setting a bit here implies required bit gets cleared.
  627. *
  628. * Request type is TISCI_MSG_SET_PROC_BOOT_CONFIG, response is a generic
  629. * ACK/NACK message.
  630. */
  631. struct ti_sci_msg_req_set_proc_boot_config {
  632. struct ti_sci_msg_hdr hdr;
  633. u8 processor_id;
  634. u32 bootvector_low;
  635. u32 bootvector_high;
  636. u32 config_flags_set;
  637. u32 config_flags_clear;
  638. } __packed;
  639. /* R5 Control Flags */
  640. #define PROC_BOOT_CTRL_FLAG_R5_CORE_HALT 0x00000001
  641. /**
  642. * struct ti_sci_msg_req_set_proc_boot_ctrl - Set Processor boot control flags
  643. * @hdr: Generic Header
  644. * @processor_id: ID of processor
  645. * @control_flags_set: Optional Processor specific Control Flags to set.
  646. * Setting a bit here implies required bit sets to 1.
  647. * @control_flags_clear:Optional Processor specific Control Flags to clear.
  648. * Setting a bit here implies required bit gets cleared.
  649. *
  650. * Request type is TISCI_MSG_SET_PROC_BOOT_CTRL, response is a generic ACK/NACK
  651. * message.
  652. */
  653. struct ti_sci_msg_req_set_proc_boot_ctrl {
  654. struct ti_sci_msg_hdr hdr;
  655. u8 processor_id;
  656. u32 control_flags_set;
  657. u32 control_flags_clear;
  658. } __packed;
  659. /**
  660. * struct ti_sci_msg_req_proc_auth_start_image - Authenticate and start image
  661. * @hdr: Generic Header
  662. * @cert_addr_low: Lower 32bit (Little Endian) of certificate
  663. * @cert_addr_high: Higher 32bit (Little Endian) of certificate
  664. *
  665. * Request type is TISCI_MSG_PROC_AUTH_BOOT_IMAGE, response is a generic
  666. * ACK/NACK message.
  667. */
  668. struct ti_sci_msg_req_proc_auth_boot_image {
  669. struct ti_sci_msg_hdr hdr;
  670. u32 cert_addr_low;
  671. u32 cert_addr_high;
  672. } __packed;
  673. struct ti_sci_msg_resp_proc_auth_boot_image {
  674. struct ti_sci_msg_hdr hdr;
  675. u32 image_addr_low;
  676. u32 image_addr_high;
  677. u32 image_size;
  678. } __packed;
  679. /**
  680. * struct ti_sci_msg_req_get_proc_boot_status - Get processor boot status
  681. * @hdr: Generic Header
  682. * @processor_id: ID of processor
  683. *
  684. * Request type is TISCI_MSG_GET_PROC_BOOT_STATUS, response is appropriate
  685. * message, or NACK in case of inability to satisfy request.
  686. */
  687. struct ti_sci_msg_req_get_proc_boot_status {
  688. struct ti_sci_msg_hdr hdr;
  689. u8 processor_id;
  690. } __packed;
  691. /* ARMv8 Status Flags */
  692. #define PROC_BOOT_STATUS_FLAG_ARMV8_WFE 0x00000001
  693. #define PROC_BOOT_STATUS_FLAG_ARMV8_WFI 0x00000002
  694. /* R5 Status Flags */
  695. #define PROC_BOOT_STATUS_FLAG_R5_WFE 0x00000001
  696. #define PROC_BOOT_STATUS_FLAG_R5_WFI 0x00000002
  697. #define PROC_BOOT_STATUS_FLAG_R5_CLK_GATED 0x00000004
  698. #define PROC_BOOT_STATUS_FLAG_R5_LOCKSTEP_PERMITTED 0x00000100
  699. /**
  700. * struct ti_sci_msg_resp_get_proc_boot_status - Processor boot status response
  701. * @hdr: Generic Header
  702. * @processor_id: ID of processor
  703. * @bootvector_low: Lower 32bit (Little Endian) of boot vector
  704. * @bootvector_high: Higher 32bit (Little Endian) of boot vector
  705. * @config_flags: Optional Processor specific Config Flags set.
  706. * @control_flags: Optional Processor specific Control Flags.
  707. * @status_flags: Optional Processor specific Status Flags set.
  708. *
  709. * Response to TISCI_MSG_GET_PROC_BOOT_STATUS.
  710. */
  711. struct ti_sci_msg_resp_get_proc_boot_status {
  712. struct ti_sci_msg_hdr hdr;
  713. u8 processor_id;
  714. u32 bootvector_low;
  715. u32 bootvector_high;
  716. u32 config_flags;
  717. u32 control_flags;
  718. u32 status_flags;
  719. } __packed;
  720. /**
  721. * struct ti_sci_msg_req_wait_proc_boot_status - Wait for a processor
  722. * boot status
  723. * @hdr: Generic Header
  724. * @processor_id: ID of processor
  725. * @num_wait_iterations: Total number of iterations we will check before
  726. * we will timeout and give up
  727. * @num_match_iterations: How many iterations should we have continued
  728. * status to account for status bits glitching.
  729. * This is to make sure that match occurs for
  730. * consecutive checks. This implies that the
  731. * worst case should consider that the stable
  732. * time should at the worst be num_wait_iterations
  733. * num_match_iterations to prevent timeout.
  734. * @delay_per_iteration_us: Specifies how long to wait (in micro seconds)
  735. * between each status checks. This is the minimum
  736. * duration, and overhead of register reads and
  737. * checks are on top of this and can vary based on
  738. * varied conditions.
  739. * @delay_before_iterations_us: Specifies how long to wait (in micro seconds)
  740. * before the very first check in the first
  741. * iteration of status check loop. This is the
  742. * minimum duration, and overhead of register
  743. * reads and checks are.
  744. * @status_flags_1_set_all_wait:If non-zero, Specifies that all bits of the
  745. * status matching this field requested MUST be 1.
  746. * @status_flags_1_set_any_wait:If non-zero, Specifies that at least one of the
  747. * bits matching this field requested MUST be 1.
  748. * @status_flags_1_clr_all_wait:If non-zero, Specifies that all bits of the
  749. * status matching this field requested MUST be 0.
  750. * @status_flags_1_clr_any_wait:If non-zero, Specifies that at least one of the
  751. * bits matching this field requested MUST be 0.
  752. *
  753. * Request type is TISCI_MSG_WAIT_PROC_BOOT_STATUS, response is appropriate
  754. * message, or NACK in case of inability to satisfy request.
  755. */
  756. struct ti_sci_msg_req_wait_proc_boot_status {
  757. struct ti_sci_msg_hdr hdr;
  758. u8 processor_id;
  759. u8 num_wait_iterations;
  760. u8 num_match_iterations;
  761. u8 delay_per_iteration_us;
  762. u8 delay_before_iterations_us;
  763. u32 status_flags_1_set_all_wait;
  764. u32 status_flags_1_set_any_wait;
  765. u32 status_flags_1_clr_all_wait;
  766. u32 status_flags_1_clr_any_wait;
  767. } __packed;
  768. /**
  769. * struct ti_sci_msg_rm_ring_cfg_req - Configure a Navigator Subsystem ring
  770. *
  771. * Configures the non-real-time registers of a Navigator Subsystem ring.
  772. * @hdr: Generic Header
  773. * @valid_params: Bitfield defining validity of ring configuration parameters.
  774. * The ring configuration fields are not valid, and will not be used for
  775. * ring configuration, if their corresponding valid bit is zero.
  776. * Valid bit usage:
  777. * 0 - Valid bit for @tisci_msg_rm_ring_cfg_req addr_lo
  778. * 1 - Valid bit for @tisci_msg_rm_ring_cfg_req addr_hi
  779. * 2 - Valid bit for @tisci_msg_rm_ring_cfg_req count
  780. * 3 - Valid bit for @tisci_msg_rm_ring_cfg_req mode
  781. * 4 - Valid bit for @tisci_msg_rm_ring_cfg_req size
  782. * 5 - Valid bit for @tisci_msg_rm_ring_cfg_req order_id
  783. * @nav_id: Device ID of Navigator Subsystem from which the ring is allocated
  784. * @index: ring index to be configured.
  785. * @addr_lo: 32 LSBs of ring base address to be programmed into the ring's
  786. * RING_BA_LO register
  787. * @addr_hi: 16 MSBs of ring base address to be programmed into the ring's
  788. * RING_BA_HI register.
  789. * @count: Number of ring elements. Must be even if mode is CREDENTIALS or QM
  790. * modes.
  791. * @mode: Specifies the mode the ring is to be configured.
  792. * @size: Specifies encoded ring element size. To calculate the encoded size use
  793. * the formula (log2(size_bytes) - 2), where size_bytes cannot be
  794. * greater than 256.
  795. * @order_id: Specifies the ring's bus order ID.
  796. */
  797. struct ti_sci_msg_rm_ring_cfg_req {
  798. struct ti_sci_msg_hdr hdr;
  799. u32 valid_params;
  800. u16 nav_id;
  801. u16 index;
  802. u32 addr_lo;
  803. u32 addr_hi;
  804. u32 count;
  805. u8 mode;
  806. u8 size;
  807. u8 order_id;
  808. } __packed;
  809. /**
  810. * struct ti_sci_msg_rm_ring_cfg_resp - Response to configuring a ring.
  811. *
  812. * @hdr: Generic Header
  813. */
  814. struct ti_sci_msg_rm_ring_cfg_resp {
  815. struct ti_sci_msg_hdr hdr;
  816. } __packed;
  817. /**
  818. * struct ti_sci_msg_rm_ring_get_cfg_req - Get RA ring's configuration
  819. *
  820. * Gets the configuration of the non-real-time register fields of a ring. The
  821. * host, or a supervisor of the host, who owns the ring must be the requesting
  822. * host. The values of the non-real-time registers are returned in
  823. * @ti_sci_msg_rm_ring_get_cfg_resp.
  824. *
  825. * @hdr: Generic Header
  826. * @nav_id: Device ID of Navigator Subsystem from which the ring is allocated
  827. * @index: ring index.
  828. */
  829. struct ti_sci_msg_rm_ring_get_cfg_req {
  830. struct ti_sci_msg_hdr hdr;
  831. u16 nav_id;
  832. u16 index;
  833. } __packed;
  834. /**
  835. * struct ti_sci_msg_rm_ring_get_cfg_resp - Ring get configuration response
  836. *
  837. * Response received by host processor after RM has handled
  838. * @ti_sci_msg_rm_ring_get_cfg_req. The response contains the ring's
  839. * non-real-time register values.
  840. *
  841. * @hdr: Generic Header
  842. * @addr_lo: Ring 32 LSBs of base address
  843. * @addr_hi: Ring 16 MSBs of base address.
  844. * @count: Ring number of elements.
  845. * @mode: Ring mode.
  846. * @size: encoded Ring element size
  847. * @order_id: ing order ID.
  848. */
  849. struct ti_sci_msg_rm_ring_get_cfg_resp {
  850. struct ti_sci_msg_hdr hdr;
  851. u32 addr_lo;
  852. u32 addr_hi;
  853. u32 count;
  854. u8 mode;
  855. u8 size;
  856. u8 order_id;
  857. } __packed;
  858. /**
  859. * struct ti_sci_msg_psil_pair - Pairs a PSI-L source thread to a destination
  860. * thread
  861. * @hdr: Generic Header
  862. * @nav_id: SoC Navigator Subsystem device ID whose PSI-L config proxy is
  863. * used to pair the source and destination threads.
  864. * @src_thread: PSI-L source thread ID within the PSI-L System thread map.
  865. *
  866. * UDMAP transmit channels mapped to source threads will have their
  867. * TCHAN_THRD_ID register programmed with the destination thread if the pairing
  868. * is successful.
  869. * @dst_thread: PSI-L destination thread ID within the PSI-L System thread map.
  870. * PSI-L destination threads start at index 0x8000. The request is NACK'd if
  871. * the destination thread is not greater than or equal to 0x8000.
  872. *
  873. * UDMAP receive channels mapped to destination threads will have their
  874. * RCHAN_THRD_ID register programmed with the source thread if the pairing
  875. * is successful.
  876. *
  877. * Request type is TI_SCI_MSG_RM_PSIL_PAIR, response is a generic ACK or NACK
  878. * message.
  879. */
  880. struct ti_sci_msg_psil_pair {
  881. struct ti_sci_msg_hdr hdr;
  882. u32 nav_id;
  883. u32 src_thread;
  884. u32 dst_thread;
  885. } __packed;
  886. /**
  887. * struct ti_sci_msg_psil_unpair - Unpairs a PSI-L source thread from a
  888. * destination thread
  889. * @hdr: Generic Header
  890. * @nav_id: SoC Navigator Subsystem device ID whose PSI-L config proxy is
  891. * used to unpair the source and destination threads.
  892. * @src_thread: PSI-L source thread ID within the PSI-L System thread map.
  893. *
  894. * UDMAP transmit channels mapped to source threads will have their
  895. * TCHAN_THRD_ID register cleared if the unpairing is successful.
  896. *
  897. * @dst_thread: PSI-L destination thread ID within the PSI-L System thread map.
  898. * PSI-L destination threads start at index 0x8000. The request is NACK'd if
  899. * the destination thread is not greater than or equal to 0x8000.
  900. *
  901. * UDMAP receive channels mapped to destination threads will have their
  902. * RCHAN_THRD_ID register cleared if the unpairing is successful.
  903. *
  904. * Request type is TI_SCI_MSG_RM_PSIL_UNPAIR, response is a generic ACK or NACK
  905. * message.
  906. */
  907. struct ti_sci_msg_psil_unpair {
  908. struct ti_sci_msg_hdr hdr;
  909. u32 nav_id;
  910. u32 src_thread;
  911. u32 dst_thread;
  912. } __packed;
  913. /**
  914. * Configures a Navigator Subsystem UDMAP transmit channel
  915. *
  916. * Configures the non-real-time registers of a Navigator Subsystem UDMAP
  917. * transmit channel. The channel index must be assigned to the host defined
  918. * in the TISCI header via the RM board configuration resource assignment
  919. * range list.
  920. *
  921. * @hdr: Generic Header
  922. *
  923. * @valid_params: Bitfield defining validity of tx channel configuration
  924. * parameters. The tx channel configuration fields are not valid, and will not
  925. * be used for ch configuration, if their corresponding valid bit is zero.
  926. * Valid bit usage:
  927. * 0 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_pause_on_err
  928. * 1 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_atype
  929. * 2 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_chan_type
  930. * 3 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_fetch_size
  931. * 4 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::txcq_qnum
  932. * 5 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_priority
  933. * 6 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_qos
  934. * 7 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_orderid
  935. * 8 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_sched_priority
  936. * 9 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_filt_einfo
  937. * 10 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_filt_pswords
  938. * 11 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_supr_tdpkt
  939. * 12 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_credit_count
  940. * 13 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::fdepth
  941. * 14 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_burst_size
  942. * 15 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_tdtype
  943. * 16 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::extended_ch_type
  944. *
  945. * @nav_id: SoC device ID of Navigator Subsystem where tx channel is located
  946. *
  947. * @index: UDMAP transmit channel index.
  948. *
  949. * @tx_pause_on_err: UDMAP transmit channel pause on error configuration to
  950. * be programmed into the tx_pause_on_err field of the channel's TCHAN_TCFG
  951. * register.
  952. *
  953. * @tx_filt_einfo: UDMAP transmit channel extended packet information passing
  954. * configuration to be programmed into the tx_filt_einfo field of the
  955. * channel's TCHAN_TCFG register.
  956. *
  957. * @tx_filt_pswords: UDMAP transmit channel protocol specific word passing
  958. * configuration to be programmed into the tx_filt_pswords field of the
  959. * channel's TCHAN_TCFG register.
  960. *
  961. * @tx_atype: UDMAP transmit channel non Ring Accelerator access pointer
  962. * interpretation configuration to be programmed into the tx_atype field of
  963. * the channel's TCHAN_TCFG register.
  964. *
  965. * @tx_chan_type: UDMAP transmit channel functional channel type and work
  966. * passing mechanism configuration to be programmed into the tx_chan_type
  967. * field of the channel's TCHAN_TCFG register.
  968. *
  969. * @tx_supr_tdpkt: UDMAP transmit channel teardown packet generation suppression
  970. * configuration to be programmed into the tx_supr_tdpkt field of the channel's
  971. * TCHAN_TCFG register.
  972. *
  973. * @tx_fetch_size: UDMAP transmit channel number of 32-bit descriptor words to
  974. * fetch configuration to be programmed into the tx_fetch_size field of the
  975. * channel's TCHAN_TCFG register. The user must make sure to set the maximum
  976. * word count that can pass through the channel for any allowed descriptor type.
  977. *
  978. * @tx_credit_count: UDMAP transmit channel transfer request credit count
  979. * configuration to be programmed into the count field of the TCHAN_TCREDIT
  980. * register. Specifies how many credits for complete TRs are available.
  981. *
  982. * @txcq_qnum: UDMAP transmit channel completion queue configuration to be
  983. * programmed into the txcq_qnum field of the TCHAN_TCQ register. The specified
  984. * completion queue must be assigned to the host, or a subordinate of the host,
  985. * requesting configuration of the transmit channel.
  986. *
  987. * @tx_priority: UDMAP transmit channel transmit priority value to be programmed
  988. * into the priority field of the channel's TCHAN_TPRI_CTRL register.
  989. *
  990. * @tx_qos: UDMAP transmit channel transmit qos value to be programmed into the
  991. * qos field of the channel's TCHAN_TPRI_CTRL register.
  992. *
  993. * @tx_orderid: UDMAP transmit channel bus order id value to be programmed into
  994. * the orderid field of the channel's TCHAN_TPRI_CTRL register.
  995. *
  996. * @fdepth: UDMAP transmit channel FIFO depth configuration to be programmed
  997. * into the fdepth field of the TCHAN_TFIFO_DEPTH register. Sets the number of
  998. * Tx FIFO bytes which are allowed to be stored for the channel. Check the UDMAP
  999. * section of the TRM for restrictions regarding this parameter.
  1000. *
  1001. * @tx_sched_priority: UDMAP transmit channel tx scheduling priority
  1002. * configuration to be programmed into the priority field of the channel's
  1003. * TCHAN_TST_SCHED register.
  1004. *
  1005. * @tx_burst_size: UDMAP transmit channel burst size configuration to be
  1006. * programmed into the tx_burst_size field of the TCHAN_TCFG register.
  1007. *
  1008. * @tx_tdtype: UDMAP transmit channel teardown type configuration to be
  1009. * programmed into the tdtype field of the TCHAN_TCFG register:
  1010. * 0 - Return immediately
  1011. * 1 - Wait for completion message from remote peer
  1012. *
  1013. * @extended_ch_type: Valid for BCDMA.
  1014. * 0 - the channel is split tx channel (tchan)
  1015. * 1 - the channel is block copy channel (bchan)
  1016. */
  1017. struct ti_sci_msg_rm_udmap_tx_ch_cfg_req {
  1018. struct ti_sci_msg_hdr hdr;
  1019. u32 valid_params;
  1020. u16 nav_id;
  1021. u16 index;
  1022. u8 tx_pause_on_err;
  1023. u8 tx_filt_einfo;
  1024. u8 tx_filt_pswords;
  1025. u8 tx_atype;
  1026. u8 tx_chan_type;
  1027. u8 tx_supr_tdpkt;
  1028. u16 tx_fetch_size;
  1029. u8 tx_credit_count;
  1030. u16 txcq_qnum;
  1031. u8 tx_priority;
  1032. u8 tx_qos;
  1033. u8 tx_orderid;
  1034. u16 fdepth;
  1035. u8 tx_sched_priority;
  1036. u8 tx_burst_size;
  1037. u8 tx_tdtype;
  1038. u8 extended_ch_type;
  1039. } __packed;
  1040. /**
  1041. * Response to configuring a UDMAP transmit channel.
  1042. *
  1043. * @hdr: Standard TISCI header
  1044. */
  1045. struct ti_sci_msg_rm_udmap_tx_ch_cfg_resp {
  1046. struct ti_sci_msg_hdr hdr;
  1047. } __packed;
  1048. /**
  1049. * Configures a Navigator Subsystem UDMAP receive channel
  1050. *
  1051. * Configures the non-real-time registers of a Navigator Subsystem UDMAP
  1052. * receive channel. The channel index must be assigned to the host defined
  1053. * in the TISCI header via the RM board configuration resource assignment
  1054. * range list.
  1055. *
  1056. * @hdr: Generic Header
  1057. *
  1058. * @valid_params: Bitfield defining validity of rx channel configuration
  1059. * parameters.
  1060. * The rx channel configuration fields are not valid, and will not be used for
  1061. * ch configuration, if their corresponding valid bit is zero.
  1062. * Valid bit usage:
  1063. * 0 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_pause_on_err
  1064. * 1 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_atype
  1065. * 2 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_chan_type
  1066. * 3 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_fetch_size
  1067. * 4 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rxcq_qnum
  1068. * 5 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_priority
  1069. * 6 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_qos
  1070. * 7 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_orderid
  1071. * 8 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_sched_priority
  1072. * 9 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::flowid_start
  1073. * 10 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::flowid_cnt
  1074. * 11 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_ignore_short
  1075. * 12 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_ignore_long
  1076. *
  1077. * @nav_id: SoC device ID of Navigator Subsystem where rx channel is located
  1078. *
  1079. * @index: UDMAP receive channel index.
  1080. *
  1081. * @rx_fetch_size: UDMAP receive channel number of 32-bit descriptor words to
  1082. * fetch configuration to be programmed into the rx_fetch_size field of the
  1083. * channel's RCHAN_RCFG register.
  1084. *
  1085. * @rxcq_qnum: UDMAP receive channel completion queue configuration to be
  1086. * programmed into the rxcq_qnum field of the RCHAN_RCQ register.
  1087. * The specified completion queue must be assigned to the host, or a subordinate
  1088. * of the host, requesting configuration of the receive channel.
  1089. *
  1090. * @rx_priority: UDMAP receive channel receive priority value to be programmed
  1091. * into the priority field of the channel's RCHAN_RPRI_CTRL register.
  1092. *
  1093. * @rx_qos: UDMAP receive channel receive qos value to be programmed into the
  1094. * qos field of the channel's RCHAN_RPRI_CTRL register.
  1095. *
  1096. * @rx_orderid: UDMAP receive channel bus order id value to be programmed into
  1097. * the orderid field of the channel's RCHAN_RPRI_CTRL register.
  1098. *
  1099. * @rx_sched_priority: UDMAP receive channel rx scheduling priority
  1100. * configuration to be programmed into the priority field of the channel's
  1101. * RCHAN_RST_SCHED register.
  1102. *
  1103. * @flowid_start: UDMAP receive channel additional flows starting index
  1104. * configuration to program into the flow_start field of the RCHAN_RFLOW_RNG
  1105. * register. Specifies the starting index for flow IDs the receive channel is to
  1106. * make use of beyond the default flow. flowid_start and @ref flowid_cnt must be
  1107. * set as valid and configured together. The starting flow ID set by
  1108. * @ref flowid_cnt must be a flow index within the Navigator Subsystem's subset
  1109. * of flows beyond the default flows statically mapped to receive channels.
  1110. * The additional flows must be assigned to the host, or a subordinate of the
  1111. * host, requesting configuration of the receive channel.
  1112. *
  1113. * @flowid_cnt: UDMAP receive channel additional flows count configuration to
  1114. * program into the flowid_cnt field of the RCHAN_RFLOW_RNG register.
  1115. * This field specifies how many flow IDs are in the additional contiguous range
  1116. * of legal flow IDs for the channel. @ref flowid_start and flowid_cnt must be
  1117. * set as valid and configured together. Disabling the valid_params field bit
  1118. * for flowid_cnt indicates no flow IDs other than the default are to be
  1119. * allocated and used by the receive channel. @ref flowid_start plus flowid_cnt
  1120. * cannot be greater than the number of receive flows in the receive channel's
  1121. * Navigator Subsystem. The additional flows must be assigned to the host, or a
  1122. * subordinate of the host, requesting configuration of the receive channel.
  1123. *
  1124. * @rx_pause_on_err: UDMAP receive channel pause on error configuration to be
  1125. * programmed into the rx_pause_on_err field of the channel's RCHAN_RCFG
  1126. * register.
  1127. *
  1128. * @rx_atype: UDMAP receive channel non Ring Accelerator access pointer
  1129. * interpretation configuration to be programmed into the rx_atype field of the
  1130. * channel's RCHAN_RCFG register.
  1131. *
  1132. * @rx_chan_type: UDMAP receive channel functional channel type and work passing
  1133. * mechanism configuration to be programmed into the rx_chan_type field of the
  1134. * channel's RCHAN_RCFG register.
  1135. *
  1136. * @rx_ignore_short: UDMAP receive channel short packet treatment configuration
  1137. * to be programmed into the rx_ignore_short field of the RCHAN_RCFG register.
  1138. *
  1139. * @rx_ignore_long: UDMAP receive channel long packet treatment configuration to
  1140. * be programmed into the rx_ignore_long field of the RCHAN_RCFG register.
  1141. */
  1142. struct ti_sci_msg_rm_udmap_rx_ch_cfg_req {
  1143. struct ti_sci_msg_hdr hdr;
  1144. u32 valid_params;
  1145. u16 nav_id;
  1146. u16 index;
  1147. u16 rx_fetch_size;
  1148. u16 rxcq_qnum;
  1149. u8 rx_priority;
  1150. u8 rx_qos;
  1151. u8 rx_orderid;
  1152. u8 rx_sched_priority;
  1153. u16 flowid_start;
  1154. u16 flowid_cnt;
  1155. u8 rx_pause_on_err;
  1156. u8 rx_atype;
  1157. u8 rx_chan_type;
  1158. u8 rx_ignore_short;
  1159. u8 rx_ignore_long;
  1160. } __packed;
  1161. /**
  1162. * Response to configuring a UDMAP receive channel.
  1163. *
  1164. * @hdr: Standard TISCI header
  1165. */
  1166. struct ti_sci_msg_rm_udmap_rx_ch_cfg_resp {
  1167. struct ti_sci_msg_hdr hdr;
  1168. } __packed;
  1169. /**
  1170. * Configures a Navigator Subsystem UDMAP receive flow
  1171. *
  1172. * Configures a Navigator Subsystem UDMAP receive flow's registers.
  1173. * Configuration does not include the flow registers which handle size-based
  1174. * free descriptor queue routing.
  1175. *
  1176. * The flow index must be assigned to the host defined in the TISCI header via
  1177. * the RM board configuration resource assignment range list.
  1178. *
  1179. * @hdr: Standard TISCI header
  1180. *
  1181. * @valid_params
  1182. * Bitfield defining validity of rx flow configuration parameters. The
  1183. * rx flow configuration fields are not valid, and will not be used for flow
  1184. * configuration, if their corresponding valid bit is zero. Valid bit usage:
  1185. * 0 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_einfo_present
  1186. * 1 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_psinfo_present
  1187. * 2 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_error_handling
  1188. * 3 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_desc_type
  1189. * 4 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_sop_offset
  1190. * 5 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_qnum
  1191. * 6 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_hi
  1192. * 7 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_lo
  1193. * 8 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_hi
  1194. * 9 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_lo
  1195. * 10 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_hi_sel
  1196. * 11 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_lo_sel
  1197. * 12 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_hi_sel
  1198. * 13 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_lo_sel
  1199. * 14 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq0_sz0_qnum
  1200. * 15 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq1_sz0_qnum
  1201. * 16 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq2_sz0_qnum
  1202. * 17 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq3_sz0_qnum
  1203. * 18 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_ps_location
  1204. *
  1205. * @nav_id: SoC device ID of Navigator Subsystem from which the receive flow is
  1206. * allocated
  1207. *
  1208. * @flow_index: UDMAP receive flow index for non-optional configuration.
  1209. *
  1210. * @rx_einfo_present:
  1211. * UDMAP receive flow extended packet info present configuration to be
  1212. * programmed into the rx_einfo_present field of the flow's RFLOW_RFA register.
  1213. *
  1214. * @rx_psinfo_present:
  1215. * UDMAP receive flow PS words present configuration to be programmed into the
  1216. * rx_psinfo_present field of the flow's RFLOW_RFA register.
  1217. *
  1218. * @rx_error_handling:
  1219. * UDMAP receive flow error handling configuration to be programmed into the
  1220. * rx_error_handling field of the flow's RFLOW_RFA register.
  1221. *
  1222. * @rx_desc_type:
  1223. * UDMAP receive flow descriptor type configuration to be programmed into the
  1224. * rx_desc_type field field of the flow's RFLOW_RFA register.
  1225. *
  1226. * @rx_sop_offset:
  1227. * UDMAP receive flow start of packet offset configuration to be programmed
  1228. * into the rx_sop_offset field of the RFLOW_RFA register. See the UDMAP
  1229. * section of the TRM for more information on this setting. Valid values for
  1230. * this field are 0-255 bytes.
  1231. *
  1232. * @rx_dest_qnum:
  1233. * UDMAP receive flow destination queue configuration to be programmed into the
  1234. * rx_dest_qnum field of the flow's RFLOW_RFA register. The specified
  1235. * destination queue must be valid within the Navigator Subsystem and must be
  1236. * owned by the host, or a subordinate of the host, requesting allocation and
  1237. * configuration of the receive flow.
  1238. *
  1239. * @rx_src_tag_hi:
  1240. * UDMAP receive flow source tag high byte constant configuration to be
  1241. * programmed into the rx_src_tag_hi field of the flow's RFLOW_RFB register.
  1242. * See the UDMAP section of the TRM for more information on this setting.
  1243. *
  1244. * @rx_src_tag_lo:
  1245. * UDMAP receive flow source tag low byte constant configuration to be
  1246. * programmed into the rx_src_tag_lo field of the flow's RFLOW_RFB register.
  1247. * See the UDMAP section of the TRM for more information on this setting.
  1248. *
  1249. * @rx_dest_tag_hi:
  1250. * UDMAP receive flow destination tag high byte constant configuration to be
  1251. * programmed into the rx_dest_tag_hi field of the flow's RFLOW_RFB register.
  1252. * See the UDMAP section of the TRM for more information on this setting.
  1253. *
  1254. * @rx_dest_tag_lo:
  1255. * UDMAP receive flow destination tag low byte constant configuration to be
  1256. * programmed into the rx_dest_tag_lo field of the flow's RFLOW_RFB register.
  1257. * See the UDMAP section of the TRM for more information on this setting.
  1258. *
  1259. * @rx_src_tag_hi_sel:
  1260. * UDMAP receive flow source tag high byte selector configuration to be
  1261. * programmed into the rx_src_tag_hi_sel field of the RFLOW_RFC register. See
  1262. * the UDMAP section of the TRM for more information on this setting.
  1263. *
  1264. * @rx_src_tag_lo_sel:
  1265. * UDMAP receive flow source tag low byte selector configuration to be
  1266. * programmed into the rx_src_tag_lo_sel field of the RFLOW_RFC register. See
  1267. * the UDMAP section of the TRM for more information on this setting.
  1268. *
  1269. * @rx_dest_tag_hi_sel:
  1270. * UDMAP receive flow destination tag high byte selector configuration to be
  1271. * programmed into the rx_dest_tag_hi_sel field of the RFLOW_RFC register. See
  1272. * the UDMAP section of the TRM for more information on this setting.
  1273. *
  1274. * @rx_dest_tag_lo_sel:
  1275. * UDMAP receive flow destination tag low byte selector configuration to be
  1276. * programmed into the rx_dest_tag_lo_sel field of the RFLOW_RFC register. See
  1277. * the UDMAP section of the TRM for more information on this setting.
  1278. *
  1279. * @rx_fdq0_sz0_qnum:
  1280. * UDMAP receive flow free descriptor queue 0 configuration to be programmed
  1281. * into the rx_fdq0_sz0_qnum field of the flow's RFLOW_RFD register. See the
  1282. * UDMAP section of the TRM for more information on this setting. The specified
  1283. * free queue must be valid within the Navigator Subsystem and must be owned
  1284. * by the host, or a subordinate of the host, requesting allocation and
  1285. * configuration of the receive flow.
  1286. *
  1287. * @rx_fdq1_qnum:
  1288. * UDMAP receive flow free descriptor queue 1 configuration to be programmed
  1289. * into the rx_fdq1_qnum field of the flow's RFLOW_RFD register. See the
  1290. * UDMAP section of the TRM for more information on this setting. The specified
  1291. * free queue must be valid within the Navigator Subsystem and must be owned
  1292. * by the host, or a subordinate of the host, requesting allocation and
  1293. * configuration of the receive flow.
  1294. *
  1295. * @rx_fdq2_qnum:
  1296. * UDMAP receive flow free descriptor queue 2 configuration to be programmed
  1297. * into the rx_fdq2_qnum field of the flow's RFLOW_RFE register. See the
  1298. * UDMAP section of the TRM for more information on this setting. The specified
  1299. * free queue must be valid within the Navigator Subsystem and must be owned
  1300. * by the host, or a subordinate of the host, requesting allocation and
  1301. * configuration of the receive flow.
  1302. *
  1303. * @rx_fdq3_qnum:
  1304. * UDMAP receive flow free descriptor queue 3 configuration to be programmed
  1305. * into the rx_fdq3_qnum field of the flow's RFLOW_RFE register. See the
  1306. * UDMAP section of the TRM for more information on this setting. The specified
  1307. * free queue must be valid within the Navigator Subsystem and must be owned
  1308. * by the host, or a subordinate of the host, requesting allocation and
  1309. * configuration of the receive flow.
  1310. *
  1311. * @rx_ps_location:
  1312. * UDMAP receive flow PS words location configuration to be programmed into the
  1313. * rx_ps_location field of the flow's RFLOW_RFA register.
  1314. */
  1315. struct ti_sci_msg_rm_udmap_flow_cfg_req {
  1316. struct ti_sci_msg_hdr hdr;
  1317. u32 valid_params;
  1318. u16 nav_id;
  1319. u16 flow_index;
  1320. u8 rx_einfo_present;
  1321. u8 rx_psinfo_present;
  1322. u8 rx_error_handling;
  1323. u8 rx_desc_type;
  1324. u16 rx_sop_offset;
  1325. u16 rx_dest_qnum;
  1326. u8 rx_src_tag_hi;
  1327. u8 rx_src_tag_lo;
  1328. u8 rx_dest_tag_hi;
  1329. u8 rx_dest_tag_lo;
  1330. u8 rx_src_tag_hi_sel;
  1331. u8 rx_src_tag_lo_sel;
  1332. u8 rx_dest_tag_hi_sel;
  1333. u8 rx_dest_tag_lo_sel;
  1334. u16 rx_fdq0_sz0_qnum;
  1335. u16 rx_fdq1_qnum;
  1336. u16 rx_fdq2_qnum;
  1337. u16 rx_fdq3_qnum;
  1338. u8 rx_ps_location;
  1339. } __packed;
  1340. /**
  1341. * Response to configuring a Navigator Subsystem UDMAP receive flow
  1342. *
  1343. * @hdr: Standard TISCI header
  1344. */
  1345. struct ti_sci_msg_rm_udmap_flow_cfg_resp {
  1346. struct ti_sci_msg_hdr hdr;
  1347. } __packed;
  1348. #define FWL_MAX_PRIVID_SLOTS 3U
  1349. /**
  1350. * struct ti_sci_msg_fwl_set_firewall_region_req - Request for configuring the firewall permissions.
  1351. *
  1352. * @hdr: Generic Header
  1353. *
  1354. * @fwl_id: Firewall ID in question
  1355. * @region: Region or channel number to set config info
  1356. * This field is unused in case of a simple firewall and must be initialized
  1357. * to zero. In case of a region based firewall, this field indicates the
  1358. * region in question. (index starting from 0) In case of a channel based
  1359. * firewall, this field indicates the channel in question (index starting
  1360. * from 0)
  1361. * @n_permission_regs: Number of permission registers to set
  1362. * @control: Contents of the firewall CONTROL register to set
  1363. * @permissions: Contents of the firewall PERMISSION register to set
  1364. * @start_address: Contents of the firewall START_ADDRESS register to set
  1365. * @end_address: Contents of the firewall END_ADDRESS register to set
  1366. */
  1367. struct ti_sci_msg_fwl_set_firewall_region_req {
  1368. struct ti_sci_msg_hdr hdr;
  1369. u16 fwl_id;
  1370. u16 region;
  1371. u32 n_permission_regs;
  1372. u32 control;
  1373. u32 permissions[FWL_MAX_PRIVID_SLOTS];
  1374. u64 start_address;
  1375. u64 end_address;
  1376. } __packed;
  1377. /**
  1378. * struct ti_sci_msg_fwl_get_firewall_region_req - Request for retrieving the firewall permissions
  1379. *
  1380. * @hdr: Generic Header
  1381. *
  1382. * @fwl_id: Firewall ID in question
  1383. * @region: Region or channel number to get config info
  1384. * This field is unused in case of a simple firewall and must be initialized
  1385. * to zero. In case of a region based firewall, this field indicates the
  1386. * region in question (index starting from 0). In case of a channel based
  1387. * firewall, this field indicates the channel in question (index starting
  1388. * from 0).
  1389. * @n_permission_regs: Number of permission registers to retrieve
  1390. */
  1391. struct ti_sci_msg_fwl_get_firewall_region_req {
  1392. struct ti_sci_msg_hdr hdr;
  1393. u16 fwl_id;
  1394. u16 region;
  1395. u32 n_permission_regs;
  1396. } __packed;
  1397. /**
  1398. * struct ti_sci_msg_fwl_get_firewall_region_resp - Response for retrieving the firewall permissions
  1399. *
  1400. * @hdr: Generic Header
  1401. *
  1402. * @fwl_id: Firewall ID in question
  1403. * @region: Region or channel number to set config info This field is
  1404. * unused in case of a simple firewall and must be initialized to zero. In
  1405. * case of a region based firewall, this field indicates the region in
  1406. * question. (index starting from 0) In case of a channel based firewall, this
  1407. * field indicates the channel in question (index starting from 0)
  1408. * @n_permission_regs: Number of permission registers retrieved
  1409. * @control: Contents of the firewall CONTROL register
  1410. * @permissions: Contents of the firewall PERMISSION registers
  1411. * @start_address: Contents of the firewall START_ADDRESS register This is not applicable for channelized firewalls.
  1412. * @end_address: Contents of the firewall END_ADDRESS register This is not applicable for channelized firewalls.
  1413. */
  1414. struct ti_sci_msg_fwl_get_firewall_region_resp {
  1415. struct ti_sci_msg_hdr hdr;
  1416. u16 fwl_id;
  1417. u16 region;
  1418. u32 n_permission_regs;
  1419. u32 control;
  1420. u32 permissions[FWL_MAX_PRIVID_SLOTS];
  1421. u64 start_address;
  1422. u64 end_address;
  1423. } __packed;
  1424. /**
  1425. * struct ti_sci_msg_fwl_change_owner_info_req - Request for a firewall owner change
  1426. *
  1427. * @hdr: Generic Header
  1428. *
  1429. * @fwl_id: Firewall ID in question
  1430. * @region: Region or channel number if applicable
  1431. * @owner_index: New owner index to transfer ownership to
  1432. */
  1433. struct ti_sci_msg_fwl_change_owner_info_req {
  1434. struct ti_sci_msg_hdr hdr;
  1435. u16 fwl_id;
  1436. u16 region;
  1437. u8 owner_index;
  1438. } __packed;
  1439. /**
  1440. * struct ti_sci_msg_fwl_change_owner_info_resp - Response for a firewall owner change
  1441. *
  1442. * @hdr: Generic Header
  1443. *
  1444. * @fwl_id: Firewall ID specified in request
  1445. * @region: Region or channel number specified in request
  1446. * @owner_index: Owner index specified in request
  1447. * @owner_privid: New owner priv-ID returned by DMSC.
  1448. * @owner_permission_bits: New owner permission bits returned by DMSC.
  1449. */
  1450. struct ti_sci_msg_fwl_change_owner_info_resp {
  1451. struct ti_sci_msg_hdr hdr;
  1452. u16 fwl_id;
  1453. u16 region;
  1454. u8 owner_index;
  1455. u8 owner_privid;
  1456. u16 owner_permission_bits;
  1457. } __packed;
  1458. #endif /* __TI_SCI_H */