k3-udma.c 70 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com
  4. * Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
  5. */
  6. #define pr_fmt(fmt) "udma: " fmt
  7. #include <common.h>
  8. #include <cpu_func.h>
  9. #include <log.h>
  10. #include <asm/cache.h>
  11. #include <asm/io.h>
  12. #include <asm/bitops.h>
  13. #include <malloc.h>
  14. #include <linux/bitops.h>
  15. #include <linux/dma-mapping.h>
  16. #include <dm.h>
  17. #include <dm/device_compat.h>
  18. #include <dm/devres.h>
  19. #include <dm/read.h>
  20. #include <dm/of_access.h>
  21. #include <dma.h>
  22. #include <dma-uclass.h>
  23. #include <linux/delay.h>
  24. #include <linux/bitmap.h>
  25. #include <linux/err.h>
  26. #include <linux/soc/ti/k3-navss-ringacc.h>
  27. #include <linux/soc/ti/cppi5.h>
  28. #include <linux/soc/ti/ti-udma.h>
  29. #include <linux/soc/ti/ti_sci_protocol.h>
  30. #include <linux/soc/ti/cppi5.h>
  31. #include "k3-udma-hwdef.h"
  32. #include "k3-psil-priv.h"
  33. #define K3_UDMA_MAX_RFLOWS 1024
  34. struct udma_chan;
  35. enum k3_dma_type {
  36. DMA_TYPE_UDMA = 0,
  37. DMA_TYPE_BCDMA,
  38. DMA_TYPE_PKTDMA,
  39. };
  40. enum udma_mmr {
  41. MMR_GCFG = 0,
  42. MMR_BCHANRT,
  43. MMR_RCHANRT,
  44. MMR_TCHANRT,
  45. MMR_RCHAN,
  46. MMR_TCHAN,
  47. MMR_RFLOW,
  48. MMR_LAST,
  49. };
  50. static const char * const mmr_names[] = {
  51. [MMR_GCFG] = "gcfg",
  52. [MMR_BCHANRT] = "bchanrt",
  53. [MMR_RCHANRT] = "rchanrt",
  54. [MMR_TCHANRT] = "tchanrt",
  55. [MMR_RCHAN] = "rchan",
  56. [MMR_TCHAN] = "tchan",
  57. [MMR_RFLOW] = "rflow",
  58. };
  59. struct udma_tchan {
  60. void __iomem *reg_chan;
  61. void __iomem *reg_rt;
  62. int id;
  63. struct k3_nav_ring *t_ring; /* Transmit ring */
  64. struct k3_nav_ring *tc_ring; /* Transmit Completion ring */
  65. int tflow_id; /* applicable only for PKTDMA */
  66. };
  67. #define udma_bchan udma_tchan
  68. struct udma_rflow {
  69. void __iomem *reg_rflow;
  70. int id;
  71. struct k3_nav_ring *fd_ring; /* Free Descriptor ring */
  72. struct k3_nav_ring *r_ring; /* Receive ring */
  73. };
  74. struct udma_rchan {
  75. void __iomem *reg_chan;
  76. void __iomem *reg_rt;
  77. int id;
  78. };
  79. struct udma_oes_offsets {
  80. /* K3 UDMA Output Event Offset */
  81. u32 udma_rchan;
  82. /* BCDMA Output Event Offsets */
  83. u32 bcdma_bchan_data;
  84. u32 bcdma_bchan_ring;
  85. u32 bcdma_tchan_data;
  86. u32 bcdma_tchan_ring;
  87. u32 bcdma_rchan_data;
  88. u32 bcdma_rchan_ring;
  89. /* PKTDMA Output Event Offsets */
  90. u32 pktdma_tchan_flow;
  91. u32 pktdma_rchan_flow;
  92. };
  93. #define UDMA_FLAG_PDMA_ACC32 BIT(0)
  94. #define UDMA_FLAG_PDMA_BURST BIT(1)
  95. #define UDMA_FLAG_TDTYPE BIT(2)
  96. struct udma_match_data {
  97. enum k3_dma_type type;
  98. u32 psil_base;
  99. bool enable_memcpy_support;
  100. u32 flags;
  101. u32 statictr_z_mask;
  102. struct udma_oes_offsets oes;
  103. u8 tpl_levels;
  104. u32 level_start_idx[];
  105. };
  106. enum udma_rm_range {
  107. RM_RANGE_BCHAN = 0,
  108. RM_RANGE_TCHAN,
  109. RM_RANGE_RCHAN,
  110. RM_RANGE_RFLOW,
  111. RM_RANGE_TFLOW,
  112. RM_RANGE_LAST,
  113. };
  114. struct udma_tisci_rm {
  115. const struct ti_sci_handle *tisci;
  116. const struct ti_sci_rm_udmap_ops *tisci_udmap_ops;
  117. u32 tisci_dev_id;
  118. /* tisci information for PSI-L thread pairing/unpairing */
  119. const struct ti_sci_rm_psil_ops *tisci_psil_ops;
  120. u32 tisci_navss_dev_id;
  121. struct ti_sci_resource *rm_ranges[RM_RANGE_LAST];
  122. };
  123. struct udma_dev {
  124. struct udevice *dev;
  125. void __iomem *mmrs[MMR_LAST];
  126. struct udma_tisci_rm tisci_rm;
  127. struct k3_nav_ringacc *ringacc;
  128. u32 features;
  129. int bchan_cnt;
  130. int tchan_cnt;
  131. int echan_cnt;
  132. int rchan_cnt;
  133. int rflow_cnt;
  134. int tflow_cnt;
  135. unsigned long *bchan_map;
  136. unsigned long *tchan_map;
  137. unsigned long *rchan_map;
  138. unsigned long *rflow_map;
  139. unsigned long *rflow_map_reserved;
  140. unsigned long *rflow_in_use;
  141. unsigned long *tflow_map;
  142. struct udma_bchan *bchans;
  143. struct udma_tchan *tchans;
  144. struct udma_rchan *rchans;
  145. struct udma_rflow *rflows;
  146. struct udma_match_data *match_data;
  147. struct udma_chan *channels;
  148. u32 psil_base;
  149. u32 ch_count;
  150. };
  151. struct udma_chan_config {
  152. u32 psd_size; /* size of Protocol Specific Data */
  153. u32 metadata_size; /* (needs_epib ? 16:0) + psd_size */
  154. u32 hdesc_size; /* Size of a packet descriptor in packet mode */
  155. int remote_thread_id;
  156. u32 atype;
  157. u32 src_thread;
  158. u32 dst_thread;
  159. enum psil_endpoint_type ep_type;
  160. enum udma_tp_level channel_tpl; /* Channel Throughput Level */
  161. /* PKTDMA mapped channel */
  162. int mapped_channel_id;
  163. /* PKTDMA default tflow or rflow for mapped channel */
  164. int default_flow_id;
  165. enum dma_direction dir;
  166. unsigned int pkt_mode:1; /* TR or packet */
  167. unsigned int needs_epib:1; /* EPIB is needed for the communication or not */
  168. unsigned int enable_acc32:1;
  169. unsigned int enable_burst:1;
  170. unsigned int notdpkt:1; /* Suppress sending TDC packet */
  171. };
  172. struct udma_chan {
  173. struct udma_dev *ud;
  174. char name[20];
  175. struct udma_bchan *bchan;
  176. struct udma_tchan *tchan;
  177. struct udma_rchan *rchan;
  178. struct udma_rflow *rflow;
  179. struct ti_udma_drv_chan_cfg_data cfg_data;
  180. u32 bcnt; /* number of bytes completed since the start of the channel */
  181. struct udma_chan_config config;
  182. u32 id;
  183. struct cppi5_host_desc_t *desc_tx;
  184. bool in_use;
  185. void *desc_rx;
  186. u32 num_rx_bufs;
  187. u32 desc_rx_cur;
  188. };
  189. #define UDMA_CH_1000(ch) (ch * 0x1000)
  190. #define UDMA_CH_100(ch) (ch * 0x100)
  191. #define UDMA_CH_40(ch) (ch * 0x40)
  192. #ifdef PKTBUFSRX
  193. #define UDMA_RX_DESC_NUM PKTBUFSRX
  194. #else
  195. #define UDMA_RX_DESC_NUM 4
  196. #endif
  197. /* Generic register access functions */
  198. static inline u32 udma_read(void __iomem *base, int reg)
  199. {
  200. u32 v;
  201. v = __raw_readl(base + reg);
  202. pr_debug("READL(32): v(%08X)<--reg(%p)\n", v, base + reg);
  203. return v;
  204. }
  205. static inline void udma_write(void __iomem *base, int reg, u32 val)
  206. {
  207. pr_debug("WRITEL(32): v(%08X)-->reg(%p)\n", val, base + reg);
  208. __raw_writel(val, base + reg);
  209. }
  210. static inline void udma_update_bits(void __iomem *base, int reg,
  211. u32 mask, u32 val)
  212. {
  213. u32 tmp, orig;
  214. orig = udma_read(base, reg);
  215. tmp = orig & ~mask;
  216. tmp |= (val & mask);
  217. if (tmp != orig)
  218. udma_write(base, reg, tmp);
  219. }
  220. /* TCHANRT */
  221. static inline u32 udma_tchanrt_read(struct udma_tchan *tchan, int reg)
  222. {
  223. if (!tchan)
  224. return 0;
  225. return udma_read(tchan->reg_rt, reg);
  226. }
  227. static inline void udma_tchanrt_write(struct udma_tchan *tchan,
  228. int reg, u32 val)
  229. {
  230. if (!tchan)
  231. return;
  232. udma_write(tchan->reg_rt, reg, val);
  233. }
  234. /* RCHANRT */
  235. static inline u32 udma_rchanrt_read(struct udma_rchan *rchan, int reg)
  236. {
  237. if (!rchan)
  238. return 0;
  239. return udma_read(rchan->reg_rt, reg);
  240. }
  241. static inline void udma_rchanrt_write(struct udma_rchan *rchan,
  242. int reg, u32 val)
  243. {
  244. if (!rchan)
  245. return;
  246. udma_write(rchan->reg_rt, reg, val);
  247. }
  248. static inline int udma_navss_psil_pair(struct udma_dev *ud, u32 src_thread,
  249. u32 dst_thread)
  250. {
  251. struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
  252. dst_thread |= UDMA_PSIL_DST_THREAD_ID_OFFSET;
  253. return tisci_rm->tisci_psil_ops->pair(tisci_rm->tisci,
  254. tisci_rm->tisci_navss_dev_id,
  255. src_thread, dst_thread);
  256. }
  257. static inline int udma_navss_psil_unpair(struct udma_dev *ud, u32 src_thread,
  258. u32 dst_thread)
  259. {
  260. struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
  261. dst_thread |= UDMA_PSIL_DST_THREAD_ID_OFFSET;
  262. return tisci_rm->tisci_psil_ops->unpair(tisci_rm->tisci,
  263. tisci_rm->tisci_navss_dev_id,
  264. src_thread, dst_thread);
  265. }
  266. static inline char *udma_get_dir_text(enum dma_direction dir)
  267. {
  268. switch (dir) {
  269. case DMA_DEV_TO_MEM:
  270. return "DEV_TO_MEM";
  271. case DMA_MEM_TO_DEV:
  272. return "MEM_TO_DEV";
  273. case DMA_MEM_TO_MEM:
  274. return "MEM_TO_MEM";
  275. case DMA_DEV_TO_DEV:
  276. return "DEV_TO_DEV";
  277. default:
  278. break;
  279. }
  280. return "invalid";
  281. }
  282. #include "k3-udma-u-boot.c"
  283. static void udma_reset_uchan(struct udma_chan *uc)
  284. {
  285. memset(&uc->config, 0, sizeof(uc->config));
  286. uc->config.remote_thread_id = -1;
  287. uc->config.mapped_channel_id = -1;
  288. uc->config.default_flow_id = -1;
  289. }
  290. static inline bool udma_is_chan_running(struct udma_chan *uc)
  291. {
  292. u32 trt_ctl = 0;
  293. u32 rrt_ctl = 0;
  294. switch (uc->config.dir) {
  295. case DMA_DEV_TO_MEM:
  296. rrt_ctl = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_CTL_REG);
  297. pr_debug("%s: rrt_ctl: 0x%08x (peer: 0x%08x)\n",
  298. __func__, rrt_ctl,
  299. udma_rchanrt_read(uc->rchan,
  300. UDMA_RCHAN_RT_PEER_RT_EN_REG));
  301. break;
  302. case DMA_MEM_TO_DEV:
  303. trt_ctl = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_CTL_REG);
  304. pr_debug("%s: trt_ctl: 0x%08x (peer: 0x%08x)\n",
  305. __func__, trt_ctl,
  306. udma_tchanrt_read(uc->tchan,
  307. UDMA_TCHAN_RT_PEER_RT_EN_REG));
  308. break;
  309. case DMA_MEM_TO_MEM:
  310. trt_ctl = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_CTL_REG);
  311. rrt_ctl = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_CTL_REG);
  312. break;
  313. default:
  314. break;
  315. }
  316. if (trt_ctl & UDMA_CHAN_RT_CTL_EN || rrt_ctl & UDMA_CHAN_RT_CTL_EN)
  317. return true;
  318. return false;
  319. }
  320. static int udma_pop_from_ring(struct udma_chan *uc, dma_addr_t *addr)
  321. {
  322. struct k3_nav_ring *ring = NULL;
  323. int ret = -ENOENT;
  324. switch (uc->config.dir) {
  325. case DMA_DEV_TO_MEM:
  326. ring = uc->rflow->r_ring;
  327. break;
  328. case DMA_MEM_TO_DEV:
  329. ring = uc->tchan->tc_ring;
  330. break;
  331. case DMA_MEM_TO_MEM:
  332. ring = uc->tchan->tc_ring;
  333. break;
  334. default:
  335. break;
  336. }
  337. if (ring && k3_nav_ringacc_ring_get_occ(ring))
  338. ret = k3_nav_ringacc_ring_pop(ring, addr);
  339. return ret;
  340. }
  341. static void udma_reset_rings(struct udma_chan *uc)
  342. {
  343. struct k3_nav_ring *ring1 = NULL;
  344. struct k3_nav_ring *ring2 = NULL;
  345. switch (uc->config.dir) {
  346. case DMA_DEV_TO_MEM:
  347. ring1 = uc->rflow->fd_ring;
  348. ring2 = uc->rflow->r_ring;
  349. break;
  350. case DMA_MEM_TO_DEV:
  351. ring1 = uc->tchan->t_ring;
  352. ring2 = uc->tchan->tc_ring;
  353. break;
  354. case DMA_MEM_TO_MEM:
  355. ring1 = uc->tchan->t_ring;
  356. ring2 = uc->tchan->tc_ring;
  357. break;
  358. default:
  359. break;
  360. }
  361. if (ring1)
  362. k3_nav_ringacc_ring_reset_dma(ring1, k3_nav_ringacc_ring_get_occ(ring1));
  363. if (ring2)
  364. k3_nav_ringacc_ring_reset(ring2);
  365. }
  366. static void udma_reset_counters(struct udma_chan *uc)
  367. {
  368. u32 val;
  369. if (uc->tchan) {
  370. val = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_BCNT_REG);
  371. udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_BCNT_REG, val);
  372. val = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_SBCNT_REG);
  373. udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_SBCNT_REG, val);
  374. val = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_PCNT_REG);
  375. udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_PCNT_REG, val);
  376. if (!uc->bchan) {
  377. val = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_PEER_BCNT_REG);
  378. udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_PEER_BCNT_REG, val);
  379. }
  380. }
  381. if (uc->rchan) {
  382. val = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_BCNT_REG);
  383. udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_BCNT_REG, val);
  384. val = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_SBCNT_REG);
  385. udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_SBCNT_REG, val);
  386. val = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_PCNT_REG);
  387. udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_PCNT_REG, val);
  388. val = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_PEER_BCNT_REG);
  389. udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_PEER_BCNT_REG, val);
  390. }
  391. uc->bcnt = 0;
  392. }
  393. static inline int udma_stop_hard(struct udma_chan *uc)
  394. {
  395. pr_debug("%s: ENTER (chan%d)\n", __func__, uc->id);
  396. switch (uc->config.dir) {
  397. case DMA_DEV_TO_MEM:
  398. udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_PEER_RT_EN_REG, 0);
  399. udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_CTL_REG, 0);
  400. break;
  401. case DMA_MEM_TO_DEV:
  402. udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_CTL_REG, 0);
  403. udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_PEER_RT_EN_REG, 0);
  404. break;
  405. case DMA_MEM_TO_MEM:
  406. udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_CTL_REG, 0);
  407. udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_CTL_REG, 0);
  408. break;
  409. default:
  410. return -EINVAL;
  411. }
  412. return 0;
  413. }
  414. static int udma_start(struct udma_chan *uc)
  415. {
  416. /* Channel is already running, no need to proceed further */
  417. if (udma_is_chan_running(uc))
  418. goto out;
  419. pr_debug("%s: chan:%d dir:%s\n",
  420. __func__, uc->id, udma_get_dir_text(uc->config.dir));
  421. /* Make sure that we clear the teardown bit, if it is set */
  422. udma_stop_hard(uc);
  423. /* Reset all counters */
  424. udma_reset_counters(uc);
  425. switch (uc->config.dir) {
  426. case DMA_DEV_TO_MEM:
  427. udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_CTL_REG,
  428. UDMA_CHAN_RT_CTL_EN);
  429. /* Enable remote */
  430. udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_PEER_RT_EN_REG,
  431. UDMA_PEER_RT_EN_ENABLE);
  432. pr_debug("%s(rx): RT_CTL:0x%08x PEER RT_ENABLE:0x%08x\n",
  433. __func__,
  434. udma_rchanrt_read(uc->rchan,
  435. UDMA_RCHAN_RT_CTL_REG),
  436. udma_rchanrt_read(uc->rchan,
  437. UDMA_RCHAN_RT_PEER_RT_EN_REG));
  438. break;
  439. case DMA_MEM_TO_DEV:
  440. /* Enable remote */
  441. udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_PEER_RT_EN_REG,
  442. UDMA_PEER_RT_EN_ENABLE);
  443. udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_CTL_REG,
  444. UDMA_CHAN_RT_CTL_EN);
  445. pr_debug("%s(tx): RT_CTL:0x%08x PEER RT_ENABLE:0x%08x\n",
  446. __func__,
  447. udma_tchanrt_read(uc->tchan,
  448. UDMA_TCHAN_RT_CTL_REG),
  449. udma_tchanrt_read(uc->tchan,
  450. UDMA_TCHAN_RT_PEER_RT_EN_REG));
  451. break;
  452. case DMA_MEM_TO_MEM:
  453. udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_CTL_REG,
  454. UDMA_CHAN_RT_CTL_EN);
  455. udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_CTL_REG,
  456. UDMA_CHAN_RT_CTL_EN);
  457. break;
  458. default:
  459. return -EINVAL;
  460. }
  461. pr_debug("%s: DONE chan:%d\n", __func__, uc->id);
  462. out:
  463. return 0;
  464. }
  465. static inline void udma_stop_mem2dev(struct udma_chan *uc, bool sync)
  466. {
  467. int i = 0;
  468. u32 val;
  469. udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_CTL_REG,
  470. UDMA_CHAN_RT_CTL_EN |
  471. UDMA_CHAN_RT_CTL_TDOWN);
  472. val = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_CTL_REG);
  473. while (sync && (val & UDMA_CHAN_RT_CTL_EN)) {
  474. val = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_CTL_REG);
  475. udelay(1);
  476. if (i > 1000) {
  477. printf(" %s TIMEOUT !\n", __func__);
  478. break;
  479. }
  480. i++;
  481. }
  482. val = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_PEER_RT_EN_REG);
  483. if (val & UDMA_PEER_RT_EN_ENABLE)
  484. printf("%s: peer not stopped TIMEOUT !\n", __func__);
  485. }
  486. static inline void udma_stop_dev2mem(struct udma_chan *uc, bool sync)
  487. {
  488. int i = 0;
  489. u32 val;
  490. udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_PEER_RT_EN_REG,
  491. UDMA_PEER_RT_EN_ENABLE |
  492. UDMA_PEER_RT_EN_TEARDOWN);
  493. val = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_CTL_REG);
  494. while (sync && (val & UDMA_CHAN_RT_CTL_EN)) {
  495. val = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_CTL_REG);
  496. udelay(1);
  497. if (i > 1000) {
  498. printf("%s TIMEOUT !\n", __func__);
  499. break;
  500. }
  501. i++;
  502. }
  503. val = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_PEER_RT_EN_REG);
  504. if (val & UDMA_PEER_RT_EN_ENABLE)
  505. printf("%s: peer not stopped TIMEOUT !\n", __func__);
  506. }
  507. static inline int udma_stop(struct udma_chan *uc)
  508. {
  509. pr_debug("%s: chan:%d dir:%s\n",
  510. __func__, uc->id, udma_get_dir_text(uc->config.dir));
  511. udma_reset_counters(uc);
  512. switch (uc->config.dir) {
  513. case DMA_DEV_TO_MEM:
  514. udma_stop_dev2mem(uc, true);
  515. break;
  516. case DMA_MEM_TO_DEV:
  517. udma_stop_mem2dev(uc, true);
  518. break;
  519. case DMA_MEM_TO_MEM:
  520. udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_CTL_REG, 0);
  521. udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_CTL_REG, 0);
  522. break;
  523. default:
  524. return -EINVAL;
  525. }
  526. return 0;
  527. }
  528. static void udma_poll_completion(struct udma_chan *uc, dma_addr_t *paddr)
  529. {
  530. int i = 1;
  531. while (udma_pop_from_ring(uc, paddr)) {
  532. udelay(1);
  533. if (!(i % 1000000))
  534. printf(".");
  535. i++;
  536. }
  537. }
  538. static struct udma_rflow *__udma_reserve_rflow(struct udma_dev *ud, int id)
  539. {
  540. DECLARE_BITMAP(tmp, K3_UDMA_MAX_RFLOWS);
  541. if (id >= 0) {
  542. if (test_bit(id, ud->rflow_map)) {
  543. dev_err(ud->dev, "rflow%d is in use\n", id);
  544. return ERR_PTR(-ENOENT);
  545. }
  546. } else {
  547. bitmap_or(tmp, ud->rflow_map, ud->rflow_map_reserved,
  548. ud->rflow_cnt);
  549. id = find_next_zero_bit(tmp, ud->rflow_cnt, ud->rchan_cnt);
  550. if (id >= ud->rflow_cnt)
  551. return ERR_PTR(-ENOENT);
  552. }
  553. __set_bit(id, ud->rflow_map);
  554. return &ud->rflows[id];
  555. }
  556. #define UDMA_RESERVE_RESOURCE(res) \
  557. static struct udma_##res *__udma_reserve_##res(struct udma_dev *ud, \
  558. int id) \
  559. { \
  560. if (id >= 0) { \
  561. if (test_bit(id, ud->res##_map)) { \
  562. dev_err(ud->dev, "res##%d is in use\n", id); \
  563. return ERR_PTR(-ENOENT); \
  564. } \
  565. } else { \
  566. id = find_first_zero_bit(ud->res##_map, ud->res##_cnt); \
  567. if (id == ud->res##_cnt) { \
  568. return ERR_PTR(-ENOENT); \
  569. } \
  570. } \
  571. \
  572. __set_bit(id, ud->res##_map); \
  573. return &ud->res##s[id]; \
  574. }
  575. UDMA_RESERVE_RESOURCE(tchan);
  576. UDMA_RESERVE_RESOURCE(rchan);
  577. static int udma_get_tchan(struct udma_chan *uc)
  578. {
  579. struct udma_dev *ud = uc->ud;
  580. if (uc->tchan) {
  581. dev_dbg(ud->dev, "chan%d: already have tchan%d allocated\n",
  582. uc->id, uc->tchan->id);
  583. return 0;
  584. }
  585. uc->tchan = __udma_reserve_tchan(ud, uc->config.mapped_channel_id);
  586. if (IS_ERR(uc->tchan))
  587. return PTR_ERR(uc->tchan);
  588. if (ud->tflow_cnt) {
  589. int tflow_id;
  590. /* Only PKTDMA have support for tx flows */
  591. if (uc->config.default_flow_id >= 0)
  592. tflow_id = uc->config.default_flow_id;
  593. else
  594. tflow_id = uc->tchan->id;
  595. if (test_bit(tflow_id, ud->tflow_map)) {
  596. dev_err(ud->dev, "tflow%d is in use\n", tflow_id);
  597. __clear_bit(uc->tchan->id, ud->tchan_map);
  598. uc->tchan = NULL;
  599. return -ENOENT;
  600. }
  601. uc->tchan->tflow_id = tflow_id;
  602. __set_bit(tflow_id, ud->tflow_map);
  603. } else {
  604. uc->tchan->tflow_id = -1;
  605. }
  606. pr_debug("chan%d: got tchan%d\n", uc->id, uc->tchan->id);
  607. return 0;
  608. }
  609. static int udma_get_rchan(struct udma_chan *uc)
  610. {
  611. struct udma_dev *ud = uc->ud;
  612. if (uc->rchan) {
  613. dev_dbg(ud->dev, "chan%d: already have rchan%d allocated\n",
  614. uc->id, uc->rchan->id);
  615. return 0;
  616. }
  617. uc->rchan = __udma_reserve_rchan(ud, uc->config.mapped_channel_id);
  618. if (IS_ERR(uc->rchan))
  619. return PTR_ERR(uc->rchan);
  620. pr_debug("chan%d: got rchan%d\n", uc->id, uc->rchan->id);
  621. return 0;
  622. }
  623. static int udma_get_chan_pair(struct udma_chan *uc)
  624. {
  625. struct udma_dev *ud = uc->ud;
  626. int chan_id, end;
  627. if ((uc->tchan && uc->rchan) && uc->tchan->id == uc->rchan->id) {
  628. dev_info(ud->dev, "chan%d: already have %d pair allocated\n",
  629. uc->id, uc->tchan->id);
  630. return 0;
  631. }
  632. if (uc->tchan) {
  633. dev_err(ud->dev, "chan%d: already have tchan%d allocated\n",
  634. uc->id, uc->tchan->id);
  635. return -EBUSY;
  636. } else if (uc->rchan) {
  637. dev_err(ud->dev, "chan%d: already have rchan%d allocated\n",
  638. uc->id, uc->rchan->id);
  639. return -EBUSY;
  640. }
  641. /* Can be optimized, but let's have it like this for now */
  642. end = min(ud->tchan_cnt, ud->rchan_cnt);
  643. for (chan_id = 0; chan_id < end; chan_id++) {
  644. if (!test_bit(chan_id, ud->tchan_map) &&
  645. !test_bit(chan_id, ud->rchan_map))
  646. break;
  647. }
  648. if (chan_id == end)
  649. return -ENOENT;
  650. __set_bit(chan_id, ud->tchan_map);
  651. __set_bit(chan_id, ud->rchan_map);
  652. uc->tchan = &ud->tchans[chan_id];
  653. uc->rchan = &ud->rchans[chan_id];
  654. pr_debug("chan%d: got t/rchan%d pair\n", uc->id, chan_id);
  655. return 0;
  656. }
  657. static int udma_get_rflow(struct udma_chan *uc, int flow_id)
  658. {
  659. struct udma_dev *ud = uc->ud;
  660. if (uc->rflow) {
  661. dev_dbg(ud->dev, "chan%d: already have rflow%d allocated\n",
  662. uc->id, uc->rflow->id);
  663. return 0;
  664. }
  665. if (!uc->rchan)
  666. dev_warn(ud->dev, "chan%d: does not have rchan??\n", uc->id);
  667. uc->rflow = __udma_reserve_rflow(ud, flow_id);
  668. if (IS_ERR(uc->rflow))
  669. return PTR_ERR(uc->rflow);
  670. pr_debug("chan%d: got rflow%d\n", uc->id, uc->rflow->id);
  671. return 0;
  672. }
  673. static void udma_put_rchan(struct udma_chan *uc)
  674. {
  675. struct udma_dev *ud = uc->ud;
  676. if (uc->rchan) {
  677. dev_dbg(ud->dev, "chan%d: put rchan%d\n", uc->id,
  678. uc->rchan->id);
  679. __clear_bit(uc->rchan->id, ud->rchan_map);
  680. uc->rchan = NULL;
  681. }
  682. }
  683. static void udma_put_tchan(struct udma_chan *uc)
  684. {
  685. struct udma_dev *ud = uc->ud;
  686. if (uc->tchan) {
  687. dev_dbg(ud->dev, "chan%d: put tchan%d\n", uc->id,
  688. uc->tchan->id);
  689. __clear_bit(uc->tchan->id, ud->tchan_map);
  690. if (uc->tchan->tflow_id >= 0)
  691. __clear_bit(uc->tchan->tflow_id, ud->tflow_map);
  692. uc->tchan = NULL;
  693. }
  694. }
  695. static void udma_put_rflow(struct udma_chan *uc)
  696. {
  697. struct udma_dev *ud = uc->ud;
  698. if (uc->rflow) {
  699. dev_dbg(ud->dev, "chan%d: put rflow%d\n", uc->id,
  700. uc->rflow->id);
  701. __clear_bit(uc->rflow->id, ud->rflow_map);
  702. uc->rflow = NULL;
  703. }
  704. }
  705. static void udma_free_tx_resources(struct udma_chan *uc)
  706. {
  707. if (!uc->tchan)
  708. return;
  709. k3_nav_ringacc_ring_free(uc->tchan->t_ring);
  710. k3_nav_ringacc_ring_free(uc->tchan->tc_ring);
  711. uc->tchan->t_ring = NULL;
  712. uc->tchan->tc_ring = NULL;
  713. udma_put_tchan(uc);
  714. }
  715. static int udma_alloc_tx_resources(struct udma_chan *uc)
  716. {
  717. struct k3_nav_ring_cfg ring_cfg;
  718. struct udma_dev *ud = uc->ud;
  719. int ret;
  720. ret = udma_get_tchan(uc);
  721. if (ret)
  722. return ret;
  723. ret = k3_nav_ringacc_request_rings_pair(ud->ringacc, uc->tchan->id, -1,
  724. &uc->tchan->t_ring,
  725. &uc->tchan->tc_ring);
  726. if (ret) {
  727. ret = -EBUSY;
  728. goto err_tx_ring;
  729. }
  730. memset(&ring_cfg, 0, sizeof(ring_cfg));
  731. ring_cfg.size = 16;
  732. ring_cfg.elm_size = K3_NAV_RINGACC_RING_ELSIZE_8;
  733. ring_cfg.mode = K3_NAV_RINGACC_RING_MODE_RING;
  734. ret = k3_nav_ringacc_ring_cfg(uc->tchan->t_ring, &ring_cfg);
  735. ret |= k3_nav_ringacc_ring_cfg(uc->tchan->tc_ring, &ring_cfg);
  736. if (ret)
  737. goto err_ringcfg;
  738. return 0;
  739. err_ringcfg:
  740. k3_nav_ringacc_ring_free(uc->tchan->tc_ring);
  741. uc->tchan->tc_ring = NULL;
  742. k3_nav_ringacc_ring_free(uc->tchan->t_ring);
  743. uc->tchan->t_ring = NULL;
  744. err_tx_ring:
  745. udma_put_tchan(uc);
  746. return ret;
  747. }
  748. static void udma_free_rx_resources(struct udma_chan *uc)
  749. {
  750. if (!uc->rchan)
  751. return;
  752. if (uc->rflow) {
  753. k3_nav_ringacc_ring_free(uc->rflow->fd_ring);
  754. k3_nav_ringacc_ring_free(uc->rflow->r_ring);
  755. uc->rflow->fd_ring = NULL;
  756. uc->rflow->r_ring = NULL;
  757. udma_put_rflow(uc);
  758. }
  759. udma_put_rchan(uc);
  760. }
  761. static int udma_alloc_rx_resources(struct udma_chan *uc)
  762. {
  763. struct k3_nav_ring_cfg ring_cfg;
  764. struct udma_dev *ud = uc->ud;
  765. struct udma_rflow *rflow;
  766. int fd_ring_id;
  767. int ret;
  768. ret = udma_get_rchan(uc);
  769. if (ret)
  770. return ret;
  771. /* For MEM_TO_MEM we don't need rflow or rings */
  772. if (uc->config.dir == DMA_MEM_TO_MEM)
  773. return 0;
  774. if (uc->config.default_flow_id >= 0)
  775. ret = udma_get_rflow(uc, uc->config.default_flow_id);
  776. else
  777. ret = udma_get_rflow(uc, uc->rchan->id);
  778. if (ret) {
  779. ret = -EBUSY;
  780. goto err_rflow;
  781. }
  782. rflow = uc->rflow;
  783. if (ud->tflow_cnt) {
  784. fd_ring_id = ud->tflow_cnt + rflow->id;
  785. } else {
  786. fd_ring_id = ud->bchan_cnt + ud->tchan_cnt + ud->echan_cnt +
  787. uc->rchan->id;
  788. }
  789. ret = k3_nav_ringacc_request_rings_pair(ud->ringacc, fd_ring_id, -1,
  790. &rflow->fd_ring, &rflow->r_ring);
  791. if (ret) {
  792. ret = -EBUSY;
  793. goto err_rx_ring;
  794. }
  795. memset(&ring_cfg, 0, sizeof(ring_cfg));
  796. ring_cfg.size = 16;
  797. ring_cfg.elm_size = K3_NAV_RINGACC_RING_ELSIZE_8;
  798. ring_cfg.mode = K3_NAV_RINGACC_RING_MODE_RING;
  799. ret = k3_nav_ringacc_ring_cfg(rflow->fd_ring, &ring_cfg);
  800. ret |= k3_nav_ringacc_ring_cfg(rflow->r_ring, &ring_cfg);
  801. if (ret)
  802. goto err_ringcfg;
  803. return 0;
  804. err_ringcfg:
  805. k3_nav_ringacc_ring_free(rflow->r_ring);
  806. rflow->r_ring = NULL;
  807. k3_nav_ringacc_ring_free(rflow->fd_ring);
  808. rflow->fd_ring = NULL;
  809. err_rx_ring:
  810. udma_put_rflow(uc);
  811. err_rflow:
  812. udma_put_rchan(uc);
  813. return ret;
  814. }
  815. static int udma_alloc_tchan_sci_req(struct udma_chan *uc)
  816. {
  817. struct udma_dev *ud = uc->ud;
  818. int tc_ring = k3_nav_ringacc_get_ring_id(uc->tchan->tc_ring);
  819. struct ti_sci_msg_rm_udmap_tx_ch_cfg req;
  820. struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
  821. u32 mode;
  822. int ret;
  823. if (uc->config.pkt_mode)
  824. mode = TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR;
  825. else
  826. mode = TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_BCOPY_PBRR;
  827. req.valid_params = TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID |
  828. TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID |
  829. TI_SCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID;
  830. req.nav_id = tisci_rm->tisci_dev_id;
  831. req.index = uc->tchan->id;
  832. req.tx_chan_type = mode;
  833. if (uc->config.dir == DMA_MEM_TO_MEM)
  834. req.tx_fetch_size = sizeof(struct cppi5_desc_hdr_t) >> 2;
  835. else
  836. req.tx_fetch_size = cppi5_hdesc_calc_size(uc->config.needs_epib,
  837. uc->config.psd_size,
  838. 0) >> 2;
  839. req.txcq_qnum = tc_ring;
  840. ret = tisci_rm->tisci_udmap_ops->tx_ch_cfg(tisci_rm->tisci, &req);
  841. if (ret) {
  842. dev_err(ud->dev, "tisci tx alloc failed %d\n", ret);
  843. return ret;
  844. }
  845. /*
  846. * Above TI SCI call handles firewall configuration, cfg
  847. * register configuration still has to be done locally in
  848. * absence of RM services.
  849. */
  850. if (IS_ENABLED(CONFIG_K3_DM_FW))
  851. udma_alloc_tchan_raw(uc);
  852. return 0;
  853. }
  854. static int udma_alloc_rchan_sci_req(struct udma_chan *uc)
  855. {
  856. struct udma_dev *ud = uc->ud;
  857. int fd_ring = k3_nav_ringacc_get_ring_id(uc->rflow->fd_ring);
  858. int rx_ring = k3_nav_ringacc_get_ring_id(uc->rflow->r_ring);
  859. int tc_ring = k3_nav_ringacc_get_ring_id(uc->tchan->tc_ring);
  860. struct ti_sci_msg_rm_udmap_rx_ch_cfg req = { 0 };
  861. struct ti_sci_msg_rm_udmap_flow_cfg flow_req = { 0 };
  862. struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
  863. u32 mode;
  864. int ret;
  865. if (uc->config.pkt_mode)
  866. mode = TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR;
  867. else
  868. mode = TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_BCOPY_PBRR;
  869. req.valid_params = TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID |
  870. TI_SCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID |
  871. TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID;
  872. req.nav_id = tisci_rm->tisci_dev_id;
  873. req.index = uc->rchan->id;
  874. req.rx_chan_type = mode;
  875. if (uc->config.dir == DMA_MEM_TO_MEM) {
  876. req.rx_fetch_size = sizeof(struct cppi5_desc_hdr_t) >> 2;
  877. req.rxcq_qnum = tc_ring;
  878. } else {
  879. req.rx_fetch_size = cppi5_hdesc_calc_size(uc->config.needs_epib,
  880. uc->config.psd_size,
  881. 0) >> 2;
  882. req.rxcq_qnum = rx_ring;
  883. }
  884. if (ud->match_data->type == DMA_TYPE_UDMA &&
  885. uc->rflow->id != uc->rchan->id &&
  886. uc->config.dir != DMA_MEM_TO_MEM) {
  887. req.flowid_start = uc->rflow->id;
  888. req.flowid_cnt = 1;
  889. req.valid_params |= TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_START_VALID |
  890. TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_CNT_VALID;
  891. }
  892. ret = tisci_rm->tisci_udmap_ops->rx_ch_cfg(tisci_rm->tisci, &req);
  893. if (ret) {
  894. dev_err(ud->dev, "tisci rx %u cfg failed %d\n",
  895. uc->rchan->id, ret);
  896. return ret;
  897. }
  898. if (uc->config.dir == DMA_MEM_TO_MEM)
  899. return ret;
  900. flow_req.valid_params =
  901. TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_EINFO_PRESENT_VALID |
  902. TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PSINFO_PRESENT_VALID |
  903. TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_ERROR_HANDLING_VALID |
  904. TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DESC_TYPE_VALID |
  905. TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_QNUM_VALID |
  906. TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_HI_SEL_VALID |
  907. TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_LO_SEL_VALID |
  908. TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_HI_SEL_VALID |
  909. TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_LO_SEL_VALID |
  910. TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ0_SZ0_QNUM_VALID |
  911. TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ1_QNUM_VALID |
  912. TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ2_QNUM_VALID |
  913. TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ3_QNUM_VALID |
  914. TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PS_LOCATION_VALID;
  915. flow_req.nav_id = tisci_rm->tisci_dev_id;
  916. flow_req.flow_index = uc->rflow->id;
  917. if (uc->config.needs_epib)
  918. flow_req.rx_einfo_present = 1;
  919. else
  920. flow_req.rx_einfo_present = 0;
  921. if (uc->config.psd_size)
  922. flow_req.rx_psinfo_present = 1;
  923. else
  924. flow_req.rx_psinfo_present = 0;
  925. flow_req.rx_error_handling = 0;
  926. flow_req.rx_desc_type = 0;
  927. flow_req.rx_dest_qnum = rx_ring;
  928. flow_req.rx_src_tag_hi_sel = 2;
  929. flow_req.rx_src_tag_lo_sel = 4;
  930. flow_req.rx_dest_tag_hi_sel = 5;
  931. flow_req.rx_dest_tag_lo_sel = 4;
  932. flow_req.rx_fdq0_sz0_qnum = fd_ring;
  933. flow_req.rx_fdq1_qnum = fd_ring;
  934. flow_req.rx_fdq2_qnum = fd_ring;
  935. flow_req.rx_fdq3_qnum = fd_ring;
  936. flow_req.rx_ps_location = 0;
  937. ret = tisci_rm->tisci_udmap_ops->rx_flow_cfg(tisci_rm->tisci,
  938. &flow_req);
  939. if (ret) {
  940. dev_err(ud->dev, "tisci rx %u flow %u cfg failed %d\n",
  941. uc->rchan->id, uc->rflow->id, ret);
  942. return ret;
  943. }
  944. /*
  945. * Above TI SCI call handles firewall configuration, cfg
  946. * register configuration still has to be done locally in
  947. * absence of RM services.
  948. */
  949. if (IS_ENABLED(CONFIG_K3_DM_FW))
  950. udma_alloc_rchan_raw(uc);
  951. return 0;
  952. }
  953. static int udma_alloc_chan_resources(struct udma_chan *uc)
  954. {
  955. struct udma_dev *ud = uc->ud;
  956. int ret;
  957. pr_debug("%s: chan:%d as %s\n",
  958. __func__, uc->id, udma_get_dir_text(uc->config.dir));
  959. switch (uc->config.dir) {
  960. case DMA_MEM_TO_MEM:
  961. /* Non synchronized - mem to mem type of transfer */
  962. uc->config.pkt_mode = false;
  963. ret = udma_get_chan_pair(uc);
  964. if (ret)
  965. return ret;
  966. ret = udma_alloc_tx_resources(uc);
  967. if (ret)
  968. goto err_free_res;
  969. ret = udma_alloc_rx_resources(uc);
  970. if (ret)
  971. goto err_free_res;
  972. uc->config.src_thread = ud->psil_base + uc->tchan->id;
  973. uc->config.dst_thread = (ud->psil_base + uc->rchan->id) | 0x8000;
  974. break;
  975. case DMA_MEM_TO_DEV:
  976. /* Slave transfer synchronized - mem to dev (TX) trasnfer */
  977. ret = udma_alloc_tx_resources(uc);
  978. if (ret)
  979. goto err_free_res;
  980. uc->config.src_thread = ud->psil_base + uc->tchan->id;
  981. uc->config.dst_thread = uc->config.remote_thread_id;
  982. uc->config.dst_thread |= 0x8000;
  983. break;
  984. case DMA_DEV_TO_MEM:
  985. /* Slave transfer synchronized - dev to mem (RX) trasnfer */
  986. ret = udma_alloc_rx_resources(uc);
  987. if (ret)
  988. goto err_free_res;
  989. uc->config.src_thread = uc->config.remote_thread_id;
  990. uc->config.dst_thread = (ud->psil_base + uc->rchan->id) | 0x8000;
  991. break;
  992. default:
  993. /* Can not happen */
  994. pr_debug("%s: chan:%d invalid direction (%u)\n",
  995. __func__, uc->id, uc->config.dir);
  996. return -EINVAL;
  997. }
  998. /* We have channel indexes and rings */
  999. if (uc->config.dir == DMA_MEM_TO_MEM) {
  1000. ret = udma_alloc_tchan_sci_req(uc);
  1001. if (ret)
  1002. goto err_free_res;
  1003. ret = udma_alloc_rchan_sci_req(uc);
  1004. if (ret)
  1005. goto err_free_res;
  1006. } else {
  1007. /* Slave transfer */
  1008. if (uc->config.dir == DMA_MEM_TO_DEV) {
  1009. ret = udma_alloc_tchan_sci_req(uc);
  1010. if (ret)
  1011. goto err_free_res;
  1012. } else {
  1013. ret = udma_alloc_rchan_sci_req(uc);
  1014. if (ret)
  1015. goto err_free_res;
  1016. }
  1017. }
  1018. if (udma_is_chan_running(uc)) {
  1019. dev_warn(ud->dev, "chan%d: is running!\n", uc->id);
  1020. udma_stop(uc);
  1021. if (udma_is_chan_running(uc)) {
  1022. dev_err(ud->dev, "chan%d: won't stop!\n", uc->id);
  1023. goto err_free_res;
  1024. }
  1025. }
  1026. /* PSI-L pairing */
  1027. ret = udma_navss_psil_pair(ud, uc->config.src_thread, uc->config.dst_thread);
  1028. if (ret) {
  1029. dev_err(ud->dev, "k3_nav_psil_request_link fail\n");
  1030. goto err_free_res;
  1031. }
  1032. return 0;
  1033. err_free_res:
  1034. udma_free_tx_resources(uc);
  1035. udma_free_rx_resources(uc);
  1036. uc->config.remote_thread_id = -1;
  1037. return ret;
  1038. }
  1039. static void udma_free_chan_resources(struct udma_chan *uc)
  1040. {
  1041. /* Hard reset UDMA channel */
  1042. udma_stop_hard(uc);
  1043. udma_reset_counters(uc);
  1044. /* Release PSI-L pairing */
  1045. udma_navss_psil_unpair(uc->ud, uc->config.src_thread, uc->config.dst_thread);
  1046. /* Reset the rings for a new start */
  1047. udma_reset_rings(uc);
  1048. udma_free_tx_resources(uc);
  1049. udma_free_rx_resources(uc);
  1050. uc->config.remote_thread_id = -1;
  1051. uc->config.dir = DMA_MEM_TO_MEM;
  1052. }
  1053. static const char * const range_names[] = {
  1054. [RM_RANGE_BCHAN] = "ti,sci-rm-range-bchan",
  1055. [RM_RANGE_TCHAN] = "ti,sci-rm-range-tchan",
  1056. [RM_RANGE_RCHAN] = "ti,sci-rm-range-rchan",
  1057. [RM_RANGE_RFLOW] = "ti,sci-rm-range-rflow",
  1058. [RM_RANGE_TFLOW] = "ti,sci-rm-range-tflow",
  1059. };
  1060. static int udma_get_mmrs(struct udevice *dev)
  1061. {
  1062. struct udma_dev *ud = dev_get_priv(dev);
  1063. u32 cap2, cap3, cap4;
  1064. int i;
  1065. ud->mmrs[MMR_GCFG] = (uint32_t *)devfdt_get_addr_name(dev, mmr_names[MMR_GCFG]);
  1066. if (!ud->mmrs[MMR_GCFG])
  1067. return -EINVAL;
  1068. cap2 = udma_read(ud->mmrs[MMR_GCFG], 0x28);
  1069. cap3 = udma_read(ud->mmrs[MMR_GCFG], 0x2c);
  1070. switch (ud->match_data->type) {
  1071. case DMA_TYPE_UDMA:
  1072. ud->rflow_cnt = cap3 & 0x3fff;
  1073. ud->tchan_cnt = cap2 & 0x1ff;
  1074. ud->echan_cnt = (cap2 >> 9) & 0x1ff;
  1075. ud->rchan_cnt = (cap2 >> 18) & 0x1ff;
  1076. break;
  1077. case DMA_TYPE_BCDMA:
  1078. ud->bchan_cnt = cap2 & 0x1ff;
  1079. ud->tchan_cnt = (cap2 >> 9) & 0x1ff;
  1080. ud->rchan_cnt = (cap2 >> 18) & 0x1ff;
  1081. break;
  1082. case DMA_TYPE_PKTDMA:
  1083. cap4 = udma_read(ud->mmrs[MMR_GCFG], 0x30);
  1084. ud->tchan_cnt = cap2 & 0x1ff;
  1085. ud->rchan_cnt = (cap2 >> 18) & 0x1ff;
  1086. ud->rflow_cnt = cap3 & 0x3fff;
  1087. ud->tflow_cnt = cap4 & 0x3fff;
  1088. break;
  1089. default:
  1090. return -EINVAL;
  1091. }
  1092. for (i = 1; i < MMR_LAST; i++) {
  1093. if (i == MMR_BCHANRT && ud->bchan_cnt == 0)
  1094. continue;
  1095. if (i == MMR_TCHANRT && ud->tchan_cnt == 0)
  1096. continue;
  1097. if (i == MMR_RCHANRT && ud->rchan_cnt == 0)
  1098. continue;
  1099. ud->mmrs[i] = (uint32_t *)devfdt_get_addr_name(dev,
  1100. mmr_names[i]);
  1101. if (!ud->mmrs[i])
  1102. return -EINVAL;
  1103. }
  1104. return 0;
  1105. }
  1106. static int udma_setup_resources(struct udma_dev *ud)
  1107. {
  1108. struct udevice *dev = ud->dev;
  1109. int i;
  1110. struct ti_sci_resource_desc *rm_desc;
  1111. struct ti_sci_resource *rm_res;
  1112. struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
  1113. ud->tchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tchan_cnt),
  1114. sizeof(unsigned long), GFP_KERNEL);
  1115. ud->tchans = devm_kcalloc(dev, ud->tchan_cnt, sizeof(*ud->tchans),
  1116. GFP_KERNEL);
  1117. ud->rchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->rchan_cnt),
  1118. sizeof(unsigned long), GFP_KERNEL);
  1119. ud->rchans = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rchans),
  1120. GFP_KERNEL);
  1121. ud->rflow_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->rflow_cnt),
  1122. sizeof(unsigned long), GFP_KERNEL);
  1123. ud->rflow_map_reserved = devm_kcalloc(dev, BITS_TO_LONGS(ud->rflow_cnt),
  1124. sizeof(unsigned long),
  1125. GFP_KERNEL);
  1126. ud->rflows = devm_kcalloc(dev, ud->rflow_cnt, sizeof(*ud->rflows),
  1127. GFP_KERNEL);
  1128. if (!ud->tchan_map || !ud->rchan_map || !ud->rflow_map ||
  1129. !ud->rflow_map_reserved || !ud->tchans || !ud->rchans ||
  1130. !ud->rflows)
  1131. return -ENOMEM;
  1132. /*
  1133. * RX flows with the same Ids as RX channels are reserved to be used
  1134. * as default flows if remote HW can't generate flow_ids. Those
  1135. * RX flows can be requested only explicitly by id.
  1136. */
  1137. bitmap_set(ud->rflow_map_reserved, 0, ud->rchan_cnt);
  1138. /* Get resource ranges from tisci */
  1139. for (i = 0; i < RM_RANGE_LAST; i++) {
  1140. if (i == RM_RANGE_BCHAN || i == RM_RANGE_TFLOW)
  1141. continue;
  1142. tisci_rm->rm_ranges[i] =
  1143. devm_ti_sci_get_of_resource(tisci_rm->tisci, dev,
  1144. tisci_rm->tisci_dev_id,
  1145. (char *)range_names[i]);
  1146. }
  1147. /* tchan ranges */
  1148. rm_res = tisci_rm->rm_ranges[RM_RANGE_TCHAN];
  1149. if (IS_ERR(rm_res)) {
  1150. bitmap_zero(ud->tchan_map, ud->tchan_cnt);
  1151. } else {
  1152. bitmap_fill(ud->tchan_map, ud->tchan_cnt);
  1153. for (i = 0; i < rm_res->sets; i++) {
  1154. rm_desc = &rm_res->desc[i];
  1155. bitmap_clear(ud->tchan_map, rm_desc->start,
  1156. rm_desc->num);
  1157. }
  1158. }
  1159. /* rchan and matching default flow ranges */
  1160. rm_res = tisci_rm->rm_ranges[RM_RANGE_RCHAN];
  1161. if (IS_ERR(rm_res)) {
  1162. bitmap_zero(ud->rchan_map, ud->rchan_cnt);
  1163. bitmap_zero(ud->rflow_map, ud->rchan_cnt);
  1164. } else {
  1165. bitmap_fill(ud->rchan_map, ud->rchan_cnt);
  1166. bitmap_fill(ud->rflow_map, ud->rchan_cnt);
  1167. for (i = 0; i < rm_res->sets; i++) {
  1168. rm_desc = &rm_res->desc[i];
  1169. bitmap_clear(ud->rchan_map, rm_desc->start,
  1170. rm_desc->num);
  1171. bitmap_clear(ud->rflow_map, rm_desc->start,
  1172. rm_desc->num);
  1173. }
  1174. }
  1175. /* GP rflow ranges */
  1176. rm_res = tisci_rm->rm_ranges[RM_RANGE_RFLOW];
  1177. if (IS_ERR(rm_res)) {
  1178. bitmap_clear(ud->rflow_map, ud->rchan_cnt,
  1179. ud->rflow_cnt - ud->rchan_cnt);
  1180. } else {
  1181. bitmap_set(ud->rflow_map, ud->rchan_cnt,
  1182. ud->rflow_cnt - ud->rchan_cnt);
  1183. for (i = 0; i < rm_res->sets; i++) {
  1184. rm_desc = &rm_res->desc[i];
  1185. bitmap_clear(ud->rflow_map, rm_desc->start,
  1186. rm_desc->num);
  1187. }
  1188. }
  1189. return 0;
  1190. }
  1191. static int bcdma_setup_resources(struct udma_dev *ud)
  1192. {
  1193. int i;
  1194. struct udevice *dev = ud->dev;
  1195. struct ti_sci_resource_desc *rm_desc;
  1196. struct ti_sci_resource *rm_res;
  1197. struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
  1198. ud->bchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->bchan_cnt),
  1199. sizeof(unsigned long), GFP_KERNEL);
  1200. ud->bchans = devm_kcalloc(dev, ud->bchan_cnt, sizeof(*ud->bchans),
  1201. GFP_KERNEL);
  1202. ud->tchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tchan_cnt),
  1203. sizeof(unsigned long), GFP_KERNEL);
  1204. ud->tchans = devm_kcalloc(dev, ud->tchan_cnt, sizeof(*ud->tchans),
  1205. GFP_KERNEL);
  1206. ud->rchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->rchan_cnt),
  1207. sizeof(unsigned long), GFP_KERNEL);
  1208. ud->rchans = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rchans),
  1209. GFP_KERNEL);
  1210. /* BCDMA do not really have flows, but the driver expect it */
  1211. ud->rflow_in_use = devm_kcalloc(dev, BITS_TO_LONGS(ud->rchan_cnt),
  1212. sizeof(unsigned long),
  1213. GFP_KERNEL);
  1214. ud->rflows = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rflows),
  1215. GFP_KERNEL);
  1216. if (!ud->bchan_map || !ud->tchan_map || !ud->rchan_map ||
  1217. !ud->rflow_in_use || !ud->bchans || !ud->tchans || !ud->rchans ||
  1218. !ud->rflows)
  1219. return -ENOMEM;
  1220. /* Get resource ranges from tisci */
  1221. for (i = 0; i < RM_RANGE_LAST; i++) {
  1222. if (i == RM_RANGE_RFLOW || i == RM_RANGE_TFLOW)
  1223. continue;
  1224. tisci_rm->rm_ranges[i] =
  1225. devm_ti_sci_get_of_resource(tisci_rm->tisci, dev,
  1226. tisci_rm->tisci_dev_id,
  1227. (char *)range_names[i]);
  1228. }
  1229. /* bchan ranges */
  1230. rm_res = tisci_rm->rm_ranges[RM_RANGE_BCHAN];
  1231. if (IS_ERR(rm_res)) {
  1232. bitmap_zero(ud->bchan_map, ud->bchan_cnt);
  1233. } else {
  1234. bitmap_fill(ud->bchan_map, ud->bchan_cnt);
  1235. for (i = 0; i < rm_res->sets; i++) {
  1236. rm_desc = &rm_res->desc[i];
  1237. bitmap_clear(ud->bchan_map, rm_desc->start,
  1238. rm_desc->num);
  1239. dev_dbg(dev, "ti-sci-res: bchan: %d:%d\n",
  1240. rm_desc->start, rm_desc->num);
  1241. }
  1242. }
  1243. /* tchan ranges */
  1244. rm_res = tisci_rm->rm_ranges[RM_RANGE_TCHAN];
  1245. if (IS_ERR(rm_res)) {
  1246. bitmap_zero(ud->tchan_map, ud->tchan_cnt);
  1247. } else {
  1248. bitmap_fill(ud->tchan_map, ud->tchan_cnt);
  1249. for (i = 0; i < rm_res->sets; i++) {
  1250. rm_desc = &rm_res->desc[i];
  1251. bitmap_clear(ud->tchan_map, rm_desc->start,
  1252. rm_desc->num);
  1253. dev_dbg(dev, "ti-sci-res: tchan: %d:%d\n",
  1254. rm_desc->start, rm_desc->num);
  1255. }
  1256. }
  1257. /* rchan ranges */
  1258. rm_res = tisci_rm->rm_ranges[RM_RANGE_RCHAN];
  1259. if (IS_ERR(rm_res)) {
  1260. bitmap_zero(ud->rchan_map, ud->rchan_cnt);
  1261. } else {
  1262. bitmap_fill(ud->rchan_map, ud->rchan_cnt);
  1263. for (i = 0; i < rm_res->sets; i++) {
  1264. rm_desc = &rm_res->desc[i];
  1265. bitmap_clear(ud->rchan_map, rm_desc->start,
  1266. rm_desc->num);
  1267. dev_dbg(dev, "ti-sci-res: rchan: %d:%d\n",
  1268. rm_desc->start, rm_desc->num);
  1269. }
  1270. }
  1271. return 0;
  1272. }
  1273. static int pktdma_setup_resources(struct udma_dev *ud)
  1274. {
  1275. int i;
  1276. struct udevice *dev = ud->dev;
  1277. struct ti_sci_resource *rm_res;
  1278. struct ti_sci_resource_desc *rm_desc;
  1279. struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
  1280. ud->tchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tchan_cnt),
  1281. sizeof(unsigned long), GFP_KERNEL);
  1282. ud->tchans = devm_kcalloc(dev, ud->tchan_cnt, sizeof(*ud->tchans),
  1283. GFP_KERNEL);
  1284. ud->rchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->rchan_cnt),
  1285. sizeof(unsigned long), GFP_KERNEL);
  1286. ud->rchans = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rchans),
  1287. GFP_KERNEL);
  1288. ud->rflow_in_use = devm_kcalloc(dev, BITS_TO_LONGS(ud->rflow_cnt),
  1289. sizeof(unsigned long),
  1290. GFP_KERNEL);
  1291. ud->rflows = devm_kcalloc(dev, ud->rflow_cnt, sizeof(*ud->rflows),
  1292. GFP_KERNEL);
  1293. ud->tflow_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tflow_cnt),
  1294. sizeof(unsigned long), GFP_KERNEL);
  1295. if (!ud->tchan_map || !ud->rchan_map || !ud->tflow_map || !ud->tchans ||
  1296. !ud->rchans || !ud->rflows || !ud->rflow_in_use)
  1297. return -ENOMEM;
  1298. /* Get resource ranges from tisci */
  1299. for (i = 0; i < RM_RANGE_LAST; i++) {
  1300. if (i == RM_RANGE_BCHAN)
  1301. continue;
  1302. tisci_rm->rm_ranges[i] =
  1303. devm_ti_sci_get_of_resource(tisci_rm->tisci, dev,
  1304. tisci_rm->tisci_dev_id,
  1305. (char *)range_names[i]);
  1306. }
  1307. /* tchan ranges */
  1308. rm_res = tisci_rm->rm_ranges[RM_RANGE_TCHAN];
  1309. if (IS_ERR(rm_res)) {
  1310. bitmap_zero(ud->tchan_map, ud->tchan_cnt);
  1311. } else {
  1312. bitmap_fill(ud->tchan_map, ud->tchan_cnt);
  1313. for (i = 0; i < rm_res->sets; i++) {
  1314. rm_desc = &rm_res->desc[i];
  1315. bitmap_clear(ud->tchan_map, rm_desc->start,
  1316. rm_desc->num);
  1317. dev_dbg(dev, "ti-sci-res: tchan: %d:%d\n",
  1318. rm_desc->start, rm_desc->num);
  1319. }
  1320. }
  1321. /* rchan ranges */
  1322. rm_res = tisci_rm->rm_ranges[RM_RANGE_RCHAN];
  1323. if (IS_ERR(rm_res)) {
  1324. bitmap_zero(ud->rchan_map, ud->rchan_cnt);
  1325. } else {
  1326. bitmap_fill(ud->rchan_map, ud->rchan_cnt);
  1327. for (i = 0; i < rm_res->sets; i++) {
  1328. rm_desc = &rm_res->desc[i];
  1329. bitmap_clear(ud->rchan_map, rm_desc->start,
  1330. rm_desc->num);
  1331. dev_dbg(dev, "ti-sci-res: rchan: %d:%d\n",
  1332. rm_desc->start, rm_desc->num);
  1333. }
  1334. }
  1335. /* rflow ranges */
  1336. rm_res = tisci_rm->rm_ranges[RM_RANGE_RFLOW];
  1337. if (IS_ERR(rm_res)) {
  1338. /* all rflows are assigned exclusively to Linux */
  1339. bitmap_zero(ud->rflow_in_use, ud->rflow_cnt);
  1340. } else {
  1341. bitmap_fill(ud->rflow_in_use, ud->rflow_cnt);
  1342. for (i = 0; i < rm_res->sets; i++) {
  1343. rm_desc = &rm_res->desc[i];
  1344. bitmap_clear(ud->rflow_in_use, rm_desc->start,
  1345. rm_desc->num);
  1346. dev_dbg(dev, "ti-sci-res: rflow: %d:%d\n",
  1347. rm_desc->start, rm_desc->num);
  1348. }
  1349. }
  1350. /* tflow ranges */
  1351. rm_res = tisci_rm->rm_ranges[RM_RANGE_TFLOW];
  1352. if (IS_ERR(rm_res)) {
  1353. /* all tflows are assigned exclusively to Linux */
  1354. bitmap_zero(ud->tflow_map, ud->tflow_cnt);
  1355. } else {
  1356. bitmap_fill(ud->tflow_map, ud->tflow_cnt);
  1357. for (i = 0; i < rm_res->sets; i++) {
  1358. rm_desc = &rm_res->desc[i];
  1359. bitmap_clear(ud->tflow_map, rm_desc->start,
  1360. rm_desc->num);
  1361. dev_dbg(dev, "ti-sci-res: tflow: %d:%d\n",
  1362. rm_desc->start, rm_desc->num);
  1363. }
  1364. }
  1365. return 0;
  1366. }
  1367. static int setup_resources(struct udma_dev *ud)
  1368. {
  1369. struct udevice *dev = ud->dev;
  1370. int ch_count, ret;
  1371. switch (ud->match_data->type) {
  1372. case DMA_TYPE_UDMA:
  1373. ret = udma_setup_resources(ud);
  1374. break;
  1375. case DMA_TYPE_BCDMA:
  1376. ret = bcdma_setup_resources(ud);
  1377. break;
  1378. case DMA_TYPE_PKTDMA:
  1379. ret = pktdma_setup_resources(ud);
  1380. break;
  1381. default:
  1382. return -EINVAL;
  1383. }
  1384. if (ret)
  1385. return ret;
  1386. ch_count = ud->bchan_cnt + ud->tchan_cnt + ud->rchan_cnt;
  1387. if (ud->bchan_cnt)
  1388. ch_count -= bitmap_weight(ud->bchan_map, ud->bchan_cnt);
  1389. ch_count -= bitmap_weight(ud->tchan_map, ud->tchan_cnt);
  1390. ch_count -= bitmap_weight(ud->rchan_map, ud->rchan_cnt);
  1391. if (!ch_count)
  1392. return -ENODEV;
  1393. ud->channels = devm_kcalloc(dev, ch_count, sizeof(*ud->channels),
  1394. GFP_KERNEL);
  1395. if (!ud->channels)
  1396. return -ENOMEM;
  1397. switch (ud->match_data->type) {
  1398. case DMA_TYPE_UDMA:
  1399. dev_dbg(dev,
  1400. "Channels: %d (tchan: %u, rchan: %u, gp-rflow: %u)\n",
  1401. ch_count,
  1402. ud->tchan_cnt - bitmap_weight(ud->tchan_map,
  1403. ud->tchan_cnt),
  1404. ud->rchan_cnt - bitmap_weight(ud->rchan_map,
  1405. ud->rchan_cnt),
  1406. ud->rflow_cnt - bitmap_weight(ud->rflow_map,
  1407. ud->rflow_cnt));
  1408. break;
  1409. case DMA_TYPE_BCDMA:
  1410. dev_dbg(dev,
  1411. "Channels: %d (bchan: %u, tchan: %u, rchan: %u)\n",
  1412. ch_count,
  1413. ud->bchan_cnt - bitmap_weight(ud->bchan_map,
  1414. ud->bchan_cnt),
  1415. ud->tchan_cnt - bitmap_weight(ud->tchan_map,
  1416. ud->tchan_cnt),
  1417. ud->rchan_cnt - bitmap_weight(ud->rchan_map,
  1418. ud->rchan_cnt));
  1419. break;
  1420. case DMA_TYPE_PKTDMA:
  1421. dev_dbg(dev,
  1422. "Channels: %d (tchan: %u, rchan: %u)\n",
  1423. ch_count,
  1424. ud->tchan_cnt - bitmap_weight(ud->tchan_map,
  1425. ud->tchan_cnt),
  1426. ud->rchan_cnt - bitmap_weight(ud->rchan_map,
  1427. ud->rchan_cnt));
  1428. break;
  1429. default:
  1430. break;
  1431. }
  1432. return ch_count;
  1433. }
  1434. static int udma_probe(struct udevice *dev)
  1435. {
  1436. struct dma_dev_priv *uc_priv = dev_get_uclass_priv(dev);
  1437. struct udma_dev *ud = dev_get_priv(dev);
  1438. int i, ret;
  1439. struct udevice *tmp;
  1440. struct udevice *tisci_dev = NULL;
  1441. struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
  1442. ofnode navss_ofnode = ofnode_get_parent(dev_ofnode(dev));
  1443. ud->match_data = (void *)dev_get_driver_data(dev);
  1444. ret = udma_get_mmrs(dev);
  1445. if (ret)
  1446. return ret;
  1447. ud->psil_base = ud->match_data->psil_base;
  1448. ret = uclass_get_device_by_phandle(UCLASS_FIRMWARE, dev,
  1449. "ti,sci", &tisci_dev);
  1450. if (ret) {
  1451. debug("Failed to get TISCI phandle (%d)\n", ret);
  1452. tisci_rm->tisci = NULL;
  1453. return -EINVAL;
  1454. }
  1455. tisci_rm->tisci = (struct ti_sci_handle *)
  1456. (ti_sci_get_handle_from_sysfw(tisci_dev));
  1457. tisci_rm->tisci_dev_id = -1;
  1458. ret = dev_read_u32(dev, "ti,sci-dev-id", &tisci_rm->tisci_dev_id);
  1459. if (ret) {
  1460. dev_err(dev, "ti,sci-dev-id read failure %d\n", ret);
  1461. return ret;
  1462. }
  1463. tisci_rm->tisci_navss_dev_id = -1;
  1464. ret = ofnode_read_u32(navss_ofnode, "ti,sci-dev-id",
  1465. &tisci_rm->tisci_navss_dev_id);
  1466. if (ret) {
  1467. dev_err(dev, "navss sci-dev-id read failure %d\n", ret);
  1468. return ret;
  1469. }
  1470. tisci_rm->tisci_udmap_ops = &tisci_rm->tisci->ops.rm_udmap_ops;
  1471. tisci_rm->tisci_psil_ops = &tisci_rm->tisci->ops.rm_psil_ops;
  1472. if (ud->match_data->type == DMA_TYPE_UDMA) {
  1473. ret = uclass_get_device_by_phandle(UCLASS_MISC, dev,
  1474. "ti,ringacc", &tmp);
  1475. ud->ringacc = dev_get_priv(tmp);
  1476. } else {
  1477. struct k3_ringacc_init_data ring_init_data;
  1478. ring_init_data.tisci = ud->tisci_rm.tisci;
  1479. ring_init_data.tisci_dev_id = ud->tisci_rm.tisci_dev_id;
  1480. if (ud->match_data->type == DMA_TYPE_BCDMA) {
  1481. ring_init_data.num_rings = ud->bchan_cnt +
  1482. ud->tchan_cnt +
  1483. ud->rchan_cnt;
  1484. } else {
  1485. ring_init_data.num_rings = ud->rflow_cnt +
  1486. ud->tflow_cnt;
  1487. }
  1488. ud->ringacc = k3_ringacc_dmarings_init(dev, &ring_init_data);
  1489. }
  1490. if (IS_ERR(ud->ringacc))
  1491. return PTR_ERR(ud->ringacc);
  1492. ud->dev = dev;
  1493. ud->ch_count = setup_resources(ud);
  1494. if (ud->ch_count <= 0)
  1495. return ud->ch_count;
  1496. for (i = 0; i < ud->bchan_cnt; i++) {
  1497. struct udma_bchan *bchan = &ud->bchans[i];
  1498. bchan->id = i;
  1499. bchan->reg_rt = ud->mmrs[MMR_BCHANRT] + i * 0x1000;
  1500. }
  1501. for (i = 0; i < ud->tchan_cnt; i++) {
  1502. struct udma_tchan *tchan = &ud->tchans[i];
  1503. tchan->id = i;
  1504. tchan->reg_chan = ud->mmrs[MMR_TCHAN] + UDMA_CH_100(i);
  1505. tchan->reg_rt = ud->mmrs[MMR_TCHANRT] + UDMA_CH_1000(i);
  1506. }
  1507. for (i = 0; i < ud->rchan_cnt; i++) {
  1508. struct udma_rchan *rchan = &ud->rchans[i];
  1509. rchan->id = i;
  1510. rchan->reg_chan = ud->mmrs[MMR_RCHAN] + UDMA_CH_100(i);
  1511. rchan->reg_rt = ud->mmrs[MMR_RCHANRT] + UDMA_CH_1000(i);
  1512. }
  1513. for (i = 0; i < ud->rflow_cnt; i++) {
  1514. struct udma_rflow *rflow = &ud->rflows[i];
  1515. rflow->id = i;
  1516. rflow->reg_rflow = ud->mmrs[MMR_RFLOW] + UDMA_CH_40(i);
  1517. }
  1518. for (i = 0; i < ud->ch_count; i++) {
  1519. struct udma_chan *uc = &ud->channels[i];
  1520. uc->ud = ud;
  1521. uc->id = i;
  1522. uc->config.remote_thread_id = -1;
  1523. uc->bchan = NULL;
  1524. uc->tchan = NULL;
  1525. uc->rchan = NULL;
  1526. uc->config.mapped_channel_id = -1;
  1527. uc->config.default_flow_id = -1;
  1528. uc->config.dir = DMA_MEM_TO_MEM;
  1529. sprintf(uc->name, "UDMA chan%d\n", i);
  1530. if (!i)
  1531. uc->in_use = true;
  1532. }
  1533. pr_debug("%s(rev: 0x%08x) CAP0-3: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
  1534. dev->name,
  1535. udma_read(ud->mmrs[MMR_GCFG], 0),
  1536. udma_read(ud->mmrs[MMR_GCFG], 0x20),
  1537. udma_read(ud->mmrs[MMR_GCFG], 0x24),
  1538. udma_read(ud->mmrs[MMR_GCFG], 0x28),
  1539. udma_read(ud->mmrs[MMR_GCFG], 0x2c));
  1540. uc_priv->supported = DMA_SUPPORTS_MEM_TO_MEM | DMA_SUPPORTS_MEM_TO_DEV;
  1541. return ret;
  1542. }
  1543. static int udma_push_to_ring(struct k3_nav_ring *ring, void *elem)
  1544. {
  1545. u64 addr = 0;
  1546. memcpy(&addr, &elem, sizeof(elem));
  1547. return k3_nav_ringacc_ring_push(ring, &addr);
  1548. }
  1549. static int *udma_prep_dma_memcpy(struct udma_chan *uc, dma_addr_t dest,
  1550. dma_addr_t src, size_t len)
  1551. {
  1552. u32 tc_ring_id = k3_nav_ringacc_get_ring_id(uc->tchan->tc_ring);
  1553. struct cppi5_tr_type15_t *tr_req;
  1554. int num_tr;
  1555. size_t tr_size = sizeof(struct cppi5_tr_type15_t);
  1556. u16 tr0_cnt0, tr0_cnt1, tr1_cnt0;
  1557. unsigned long dummy;
  1558. void *tr_desc;
  1559. size_t desc_size;
  1560. if (len < SZ_64K) {
  1561. num_tr = 1;
  1562. tr0_cnt0 = len;
  1563. tr0_cnt1 = 1;
  1564. } else {
  1565. unsigned long align_to = __ffs(src | dest);
  1566. if (align_to > 3)
  1567. align_to = 3;
  1568. /*
  1569. * Keep simple: tr0: SZ_64K-alignment blocks,
  1570. * tr1: the remaining
  1571. */
  1572. num_tr = 2;
  1573. tr0_cnt0 = (SZ_64K - BIT(align_to));
  1574. if (len / tr0_cnt0 >= SZ_64K) {
  1575. dev_err(uc->ud->dev, "size %zu is not supported\n",
  1576. len);
  1577. return NULL;
  1578. }
  1579. tr0_cnt1 = len / tr0_cnt0;
  1580. tr1_cnt0 = len % tr0_cnt0;
  1581. }
  1582. desc_size = cppi5_trdesc_calc_size(num_tr, tr_size);
  1583. tr_desc = dma_alloc_coherent(desc_size, &dummy);
  1584. if (!tr_desc)
  1585. return NULL;
  1586. memset(tr_desc, 0, desc_size);
  1587. cppi5_trdesc_init(tr_desc, num_tr, tr_size, 0, 0);
  1588. cppi5_desc_set_pktids(tr_desc, uc->id, 0x3fff);
  1589. cppi5_desc_set_retpolicy(tr_desc, 0, tc_ring_id);
  1590. tr_req = tr_desc + tr_size;
  1591. cppi5_tr_init(&tr_req[0].flags, CPPI5_TR_TYPE15, false, true,
  1592. CPPI5_TR_EVENT_SIZE_COMPLETION, 1);
  1593. cppi5_tr_csf_set(&tr_req[0].flags, CPPI5_TR_CSF_SUPR_EVT);
  1594. tr_req[0].addr = src;
  1595. tr_req[0].icnt0 = tr0_cnt0;
  1596. tr_req[0].icnt1 = tr0_cnt1;
  1597. tr_req[0].icnt2 = 1;
  1598. tr_req[0].icnt3 = 1;
  1599. tr_req[0].dim1 = tr0_cnt0;
  1600. tr_req[0].daddr = dest;
  1601. tr_req[0].dicnt0 = tr0_cnt0;
  1602. tr_req[0].dicnt1 = tr0_cnt1;
  1603. tr_req[0].dicnt2 = 1;
  1604. tr_req[0].dicnt3 = 1;
  1605. tr_req[0].ddim1 = tr0_cnt0;
  1606. if (num_tr == 2) {
  1607. cppi5_tr_init(&tr_req[1].flags, CPPI5_TR_TYPE15, false, true,
  1608. CPPI5_TR_EVENT_SIZE_COMPLETION, 0);
  1609. cppi5_tr_csf_set(&tr_req[1].flags, CPPI5_TR_CSF_SUPR_EVT);
  1610. tr_req[1].addr = src + tr0_cnt1 * tr0_cnt0;
  1611. tr_req[1].icnt0 = tr1_cnt0;
  1612. tr_req[1].icnt1 = 1;
  1613. tr_req[1].icnt2 = 1;
  1614. tr_req[1].icnt3 = 1;
  1615. tr_req[1].daddr = dest + tr0_cnt1 * tr0_cnt0;
  1616. tr_req[1].dicnt0 = tr1_cnt0;
  1617. tr_req[1].dicnt1 = 1;
  1618. tr_req[1].dicnt2 = 1;
  1619. tr_req[1].dicnt3 = 1;
  1620. }
  1621. cppi5_tr_csf_set(&tr_req[num_tr - 1].flags, CPPI5_TR_CSF_EOP);
  1622. flush_dcache_range((unsigned long)tr_desc,
  1623. ALIGN((unsigned long)tr_desc + desc_size,
  1624. ARCH_DMA_MINALIGN));
  1625. udma_push_to_ring(uc->tchan->t_ring, tr_desc);
  1626. return 0;
  1627. }
  1628. #define TISCI_BCDMA_BCHAN_VALID_PARAMS ( \
  1629. TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID | \
  1630. TI_SCI_MSG_VALUE_RM_UDMAP_CH_EXTENDED_CH_TYPE_VALID)
  1631. #define TISCI_BCDMA_TCHAN_VALID_PARAMS ( \
  1632. TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID | \
  1633. TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_SUPR_TDPKT_VALID)
  1634. #define TISCI_BCDMA_RCHAN_VALID_PARAMS ( \
  1635. TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID)
  1636. #define TISCI_UDMA_TCHAN_VALID_PARAMS ( \
  1637. TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID | \
  1638. TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_EINFO_VALID | \
  1639. TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_PSWORDS_VALID | \
  1640. TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID | \
  1641. TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_SUPR_TDPKT_VALID | \
  1642. TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID | \
  1643. TI_SCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID | \
  1644. TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID)
  1645. #define TISCI_UDMA_RCHAN_VALID_PARAMS ( \
  1646. TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID | \
  1647. TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID | \
  1648. TI_SCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID | \
  1649. TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID | \
  1650. TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_SHORT_VALID | \
  1651. TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_LONG_VALID | \
  1652. TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_START_VALID | \
  1653. TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_CNT_VALID | \
  1654. TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID)
  1655. static int bcdma_tisci_m2m_channel_config(struct udma_chan *uc)
  1656. {
  1657. struct udma_dev *ud = uc->ud;
  1658. struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
  1659. const struct ti_sci_rm_udmap_ops *tisci_ops = tisci_rm->tisci_udmap_ops;
  1660. struct ti_sci_msg_rm_udmap_tx_ch_cfg req_tx = { 0 };
  1661. struct udma_bchan *bchan = uc->bchan;
  1662. int ret = 0;
  1663. req_tx.valid_params = TISCI_BCDMA_BCHAN_VALID_PARAMS;
  1664. req_tx.nav_id = tisci_rm->tisci_dev_id;
  1665. req_tx.extended_ch_type = TI_SCI_RM_BCDMA_EXTENDED_CH_TYPE_BCHAN;
  1666. req_tx.index = bchan->id;
  1667. ret = tisci_ops->tx_ch_cfg(tisci_rm->tisci, &req_tx);
  1668. if (ret)
  1669. dev_err(ud->dev, "bchan%d cfg failed %d\n", bchan->id, ret);
  1670. return ret;
  1671. }
  1672. static struct udma_bchan *__bcdma_reserve_bchan(struct udma_dev *ud, int id)
  1673. {
  1674. if (id >= 0) {
  1675. if (test_bit(id, ud->bchan_map)) {
  1676. dev_err(ud->dev, "bchan%d is in use\n", id);
  1677. return ERR_PTR(-ENOENT);
  1678. }
  1679. } else {
  1680. id = find_next_zero_bit(ud->bchan_map, ud->bchan_cnt, 0);
  1681. if (id == ud->bchan_cnt)
  1682. return ERR_PTR(-ENOENT);
  1683. }
  1684. __set_bit(id, ud->bchan_map);
  1685. return &ud->bchans[id];
  1686. }
  1687. static int bcdma_get_bchan(struct udma_chan *uc)
  1688. {
  1689. struct udma_dev *ud = uc->ud;
  1690. if (uc->bchan) {
  1691. dev_err(ud->dev, "chan%d: already have bchan%d allocated\n",
  1692. uc->id, uc->bchan->id);
  1693. return 0;
  1694. }
  1695. uc->bchan = __bcdma_reserve_bchan(ud, -1);
  1696. if (IS_ERR(uc->bchan))
  1697. return PTR_ERR(uc->bchan);
  1698. uc->tchan = uc->bchan;
  1699. return 0;
  1700. }
  1701. static void bcdma_put_bchan(struct udma_chan *uc)
  1702. {
  1703. struct udma_dev *ud = uc->ud;
  1704. if (uc->bchan) {
  1705. dev_dbg(ud->dev, "chan%d: put bchan%d\n", uc->id,
  1706. uc->bchan->id);
  1707. __clear_bit(uc->bchan->id, ud->bchan_map);
  1708. uc->bchan = NULL;
  1709. uc->tchan = NULL;
  1710. }
  1711. }
  1712. static void bcdma_free_bchan_resources(struct udma_chan *uc)
  1713. {
  1714. if (!uc->bchan)
  1715. return;
  1716. k3_nav_ringacc_ring_free(uc->bchan->tc_ring);
  1717. k3_nav_ringacc_ring_free(uc->bchan->t_ring);
  1718. uc->bchan->tc_ring = NULL;
  1719. uc->bchan->t_ring = NULL;
  1720. bcdma_put_bchan(uc);
  1721. }
  1722. static int bcdma_alloc_bchan_resources(struct udma_chan *uc)
  1723. {
  1724. struct k3_nav_ring_cfg ring_cfg;
  1725. struct udma_dev *ud = uc->ud;
  1726. int ret;
  1727. ret = bcdma_get_bchan(uc);
  1728. if (ret)
  1729. return ret;
  1730. ret = k3_nav_ringacc_request_rings_pair(ud->ringacc, uc->bchan->id, -1,
  1731. &uc->bchan->t_ring,
  1732. &uc->bchan->tc_ring);
  1733. if (ret) {
  1734. ret = -EBUSY;
  1735. goto err_ring;
  1736. }
  1737. memset(&ring_cfg, 0, sizeof(ring_cfg));
  1738. ring_cfg.size = 16;
  1739. ring_cfg.elm_size = K3_NAV_RINGACC_RING_ELSIZE_8;
  1740. ring_cfg.mode = K3_NAV_RINGACC_RING_MODE_RING;
  1741. ret = k3_nav_ringacc_ring_cfg(uc->bchan->t_ring, &ring_cfg);
  1742. if (ret)
  1743. goto err_ringcfg;
  1744. return 0;
  1745. err_ringcfg:
  1746. k3_nav_ringacc_ring_free(uc->bchan->tc_ring);
  1747. uc->bchan->tc_ring = NULL;
  1748. k3_nav_ringacc_ring_free(uc->bchan->t_ring);
  1749. uc->bchan->t_ring = NULL;
  1750. err_ring:
  1751. bcdma_put_bchan(uc);
  1752. return ret;
  1753. }
  1754. static int bcdma_tisci_tx_channel_config(struct udma_chan *uc)
  1755. {
  1756. struct udma_dev *ud = uc->ud;
  1757. struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
  1758. const struct ti_sci_rm_udmap_ops *tisci_ops = tisci_rm->tisci_udmap_ops;
  1759. struct udma_tchan *tchan = uc->tchan;
  1760. struct ti_sci_msg_rm_udmap_tx_ch_cfg req_tx = { 0 };
  1761. int ret = 0;
  1762. req_tx.valid_params = TISCI_BCDMA_TCHAN_VALID_PARAMS;
  1763. req_tx.nav_id = tisci_rm->tisci_dev_id;
  1764. req_tx.index = tchan->id;
  1765. req_tx.tx_supr_tdpkt = uc->config.notdpkt;
  1766. if (uc->config.ep_type == PSIL_EP_PDMA_XY &&
  1767. ud->match_data->flags & UDMA_FLAG_TDTYPE) {
  1768. /* wait for peer to complete the teardown for PDMAs */
  1769. req_tx.valid_params |=
  1770. TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_TDTYPE_VALID;
  1771. req_tx.tx_tdtype = 1;
  1772. }
  1773. ret = tisci_ops->tx_ch_cfg(tisci_rm->tisci, &req_tx);
  1774. if (ret)
  1775. dev_err(ud->dev, "tchan%d cfg failed %d\n", tchan->id, ret);
  1776. return ret;
  1777. }
  1778. #define pktdma_tisci_tx_channel_config bcdma_tisci_tx_channel_config
  1779. static int pktdma_tisci_rx_channel_config(struct udma_chan *uc)
  1780. {
  1781. struct udma_dev *ud = uc->ud;
  1782. struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
  1783. const struct ti_sci_rm_udmap_ops *tisci_ops = tisci_rm->tisci_udmap_ops;
  1784. struct ti_sci_msg_rm_udmap_rx_ch_cfg req_rx = { 0 };
  1785. struct ti_sci_msg_rm_udmap_flow_cfg flow_req = { 0 };
  1786. int ret = 0;
  1787. req_rx.valid_params = TISCI_BCDMA_RCHAN_VALID_PARAMS;
  1788. req_rx.nav_id = tisci_rm->tisci_dev_id;
  1789. req_rx.index = uc->rchan->id;
  1790. ret = tisci_ops->rx_ch_cfg(tisci_rm->tisci, &req_rx);
  1791. if (ret) {
  1792. dev_err(ud->dev, "rchan%d cfg failed %d\n", uc->rchan->id, ret);
  1793. return ret;
  1794. }
  1795. flow_req.valid_params =
  1796. TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_EINFO_PRESENT_VALID |
  1797. TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PSINFO_PRESENT_VALID |
  1798. TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_ERROR_HANDLING_VALID;
  1799. flow_req.nav_id = tisci_rm->tisci_dev_id;
  1800. flow_req.flow_index = uc->rflow->id;
  1801. if (uc->config.needs_epib)
  1802. flow_req.rx_einfo_present = 1;
  1803. else
  1804. flow_req.rx_einfo_present = 0;
  1805. if (uc->config.psd_size)
  1806. flow_req.rx_psinfo_present = 1;
  1807. else
  1808. flow_req.rx_psinfo_present = 0;
  1809. flow_req.rx_error_handling = 1;
  1810. ret = tisci_ops->rx_flow_cfg(tisci_rm->tisci, &flow_req);
  1811. if (ret)
  1812. dev_err(ud->dev, "flow%d config failed: %d\n", uc->rflow->id,
  1813. ret);
  1814. return ret;
  1815. }
  1816. static int bcdma_alloc_chan_resources(struct udma_chan *uc)
  1817. {
  1818. int ret;
  1819. uc->config.pkt_mode = false;
  1820. switch (uc->config.dir) {
  1821. case DMA_MEM_TO_MEM:
  1822. /* Non synchronized - mem to mem type of transfer */
  1823. dev_dbg(uc->ud->dev, "%s: chan%d as MEM-to-MEM\n", __func__,
  1824. uc->id);
  1825. ret = bcdma_alloc_bchan_resources(uc);
  1826. if (ret)
  1827. return ret;
  1828. ret = bcdma_tisci_m2m_channel_config(uc);
  1829. break;
  1830. default:
  1831. /* Can not happen */
  1832. dev_err(uc->ud->dev, "%s: chan%d invalid direction (%u)\n",
  1833. __func__, uc->id, uc->config.dir);
  1834. return -EINVAL;
  1835. }
  1836. /* check if the channel configuration was successful */
  1837. if (ret)
  1838. goto err_res_free;
  1839. if (udma_is_chan_running(uc)) {
  1840. dev_warn(uc->ud->dev, "chan%d: is running!\n", uc->id);
  1841. udma_stop(uc);
  1842. if (udma_is_chan_running(uc)) {
  1843. dev_err(uc->ud->dev, "chan%d: won't stop!\n", uc->id);
  1844. goto err_res_free;
  1845. }
  1846. }
  1847. udma_reset_rings(uc);
  1848. return 0;
  1849. err_res_free:
  1850. bcdma_free_bchan_resources(uc);
  1851. udma_free_tx_resources(uc);
  1852. udma_free_rx_resources(uc);
  1853. udma_reset_uchan(uc);
  1854. return ret;
  1855. }
  1856. static int pktdma_alloc_chan_resources(struct udma_chan *uc)
  1857. {
  1858. struct udma_dev *ud = uc->ud;
  1859. int ret;
  1860. switch (uc->config.dir) {
  1861. case DMA_MEM_TO_DEV:
  1862. /* Slave transfer synchronized - mem to dev (TX) trasnfer */
  1863. dev_dbg(uc->ud->dev, "%s: chan%d as MEM-to-DEV\n", __func__,
  1864. uc->id);
  1865. ret = udma_alloc_tx_resources(uc);
  1866. if (ret) {
  1867. uc->config.remote_thread_id = -1;
  1868. return ret;
  1869. }
  1870. uc->config.src_thread = ud->psil_base + uc->tchan->id;
  1871. uc->config.dst_thread = uc->config.remote_thread_id;
  1872. uc->config.dst_thread |= K3_PSIL_DST_THREAD_ID_OFFSET;
  1873. ret = pktdma_tisci_tx_channel_config(uc);
  1874. break;
  1875. case DMA_DEV_TO_MEM:
  1876. /* Slave transfer synchronized - dev to mem (RX) trasnfer */
  1877. dev_dbg(uc->ud->dev, "%s: chan%d as DEV-to-MEM\n", __func__,
  1878. uc->id);
  1879. ret = udma_alloc_rx_resources(uc);
  1880. if (ret) {
  1881. uc->config.remote_thread_id = -1;
  1882. return ret;
  1883. }
  1884. uc->config.src_thread = uc->config.remote_thread_id;
  1885. uc->config.dst_thread = (ud->psil_base + uc->rchan->id) |
  1886. K3_PSIL_DST_THREAD_ID_OFFSET;
  1887. ret = pktdma_tisci_rx_channel_config(uc);
  1888. break;
  1889. default:
  1890. /* Can not happen */
  1891. dev_err(uc->ud->dev, "%s: chan%d invalid direction (%u)\n",
  1892. __func__, uc->id, uc->config.dir);
  1893. return -EINVAL;
  1894. }
  1895. /* check if the channel configuration was successful */
  1896. if (ret)
  1897. goto err_res_free;
  1898. /* PSI-L pairing */
  1899. ret = udma_navss_psil_pair(ud, uc->config.src_thread, uc->config.dst_thread);
  1900. if (ret) {
  1901. dev_err(ud->dev, "PSI-L pairing failed: 0x%04x -> 0x%04x\n",
  1902. uc->config.src_thread, uc->config.dst_thread);
  1903. goto err_res_free;
  1904. }
  1905. if (udma_is_chan_running(uc)) {
  1906. dev_warn(ud->dev, "chan%d: is running!\n", uc->id);
  1907. udma_stop(uc);
  1908. if (udma_is_chan_running(uc)) {
  1909. dev_err(ud->dev, "chan%d: won't stop!\n", uc->id);
  1910. goto err_res_free;
  1911. }
  1912. }
  1913. udma_reset_rings(uc);
  1914. if (uc->tchan)
  1915. dev_dbg(ud->dev,
  1916. "chan%d: tchan%d, tflow%d, Remote thread: 0x%04x\n",
  1917. uc->id, uc->tchan->id, uc->tchan->tflow_id,
  1918. uc->config.remote_thread_id);
  1919. else if (uc->rchan)
  1920. dev_dbg(ud->dev,
  1921. "chan%d: rchan%d, rflow%d, Remote thread: 0x%04x\n",
  1922. uc->id, uc->rchan->id, uc->rflow->id,
  1923. uc->config.remote_thread_id);
  1924. return 0;
  1925. err_res_free:
  1926. udma_free_tx_resources(uc);
  1927. udma_free_rx_resources(uc);
  1928. udma_reset_uchan(uc);
  1929. return ret;
  1930. }
  1931. static int udma_transfer(struct udevice *dev, int direction,
  1932. void *dst, void *src, size_t len)
  1933. {
  1934. struct udma_dev *ud = dev_get_priv(dev);
  1935. /* Channel0 is reserved for memcpy */
  1936. struct udma_chan *uc = &ud->channels[0];
  1937. dma_addr_t paddr = 0;
  1938. int ret;
  1939. switch (ud->match_data->type) {
  1940. case DMA_TYPE_UDMA:
  1941. ret = udma_alloc_chan_resources(uc);
  1942. break;
  1943. case DMA_TYPE_BCDMA:
  1944. ret = bcdma_alloc_chan_resources(uc);
  1945. break;
  1946. default:
  1947. return -EINVAL;
  1948. };
  1949. if (ret)
  1950. return ret;
  1951. udma_prep_dma_memcpy(uc, (dma_addr_t)dst, (dma_addr_t)src, len);
  1952. udma_start(uc);
  1953. udma_poll_completion(uc, &paddr);
  1954. udma_stop(uc);
  1955. switch (ud->match_data->type) {
  1956. case DMA_TYPE_UDMA:
  1957. udma_free_chan_resources(uc);
  1958. break;
  1959. case DMA_TYPE_BCDMA:
  1960. bcdma_free_bchan_resources(uc);
  1961. break;
  1962. default:
  1963. return -EINVAL;
  1964. };
  1965. return 0;
  1966. }
  1967. static int udma_request(struct dma *dma)
  1968. {
  1969. struct udma_dev *ud = dev_get_priv(dma->dev);
  1970. struct udma_chan_config *ucc;
  1971. struct udma_chan *uc;
  1972. unsigned long dummy;
  1973. int ret;
  1974. if (dma->id >= (ud->rchan_cnt + ud->tchan_cnt)) {
  1975. dev_err(dma->dev, "invalid dma ch_id %lu\n", dma->id);
  1976. return -EINVAL;
  1977. }
  1978. uc = &ud->channels[dma->id];
  1979. ucc = &uc->config;
  1980. switch (ud->match_data->type) {
  1981. case DMA_TYPE_UDMA:
  1982. ret = udma_alloc_chan_resources(uc);
  1983. break;
  1984. case DMA_TYPE_BCDMA:
  1985. ret = bcdma_alloc_chan_resources(uc);
  1986. break;
  1987. case DMA_TYPE_PKTDMA:
  1988. ret = pktdma_alloc_chan_resources(uc);
  1989. break;
  1990. default:
  1991. return -EINVAL;
  1992. }
  1993. if (ret) {
  1994. dev_err(dma->dev, "alloc dma res failed %d\n", ret);
  1995. return -EINVAL;
  1996. }
  1997. if (uc->config.dir == DMA_MEM_TO_DEV) {
  1998. uc->desc_tx = dma_alloc_coherent(ucc->hdesc_size, &dummy);
  1999. memset(uc->desc_tx, 0, ucc->hdesc_size);
  2000. } else {
  2001. uc->desc_rx = dma_alloc_coherent(
  2002. ucc->hdesc_size * UDMA_RX_DESC_NUM, &dummy);
  2003. memset(uc->desc_rx, 0, ucc->hdesc_size * UDMA_RX_DESC_NUM);
  2004. }
  2005. uc->in_use = true;
  2006. uc->desc_rx_cur = 0;
  2007. uc->num_rx_bufs = 0;
  2008. if (uc->config.dir == DMA_DEV_TO_MEM) {
  2009. uc->cfg_data.flow_id_base = uc->rflow->id;
  2010. uc->cfg_data.flow_id_cnt = 1;
  2011. }
  2012. return 0;
  2013. }
  2014. static int udma_rfree(struct dma *dma)
  2015. {
  2016. struct udma_dev *ud = dev_get_priv(dma->dev);
  2017. struct udma_chan *uc;
  2018. if (dma->id >= (ud->rchan_cnt + ud->tchan_cnt)) {
  2019. dev_err(dma->dev, "invalid dma ch_id %lu\n", dma->id);
  2020. return -EINVAL;
  2021. }
  2022. uc = &ud->channels[dma->id];
  2023. if (udma_is_chan_running(uc))
  2024. udma_stop(uc);
  2025. udma_navss_psil_unpair(ud, uc->config.src_thread,
  2026. uc->config.dst_thread);
  2027. bcdma_free_bchan_resources(uc);
  2028. udma_free_tx_resources(uc);
  2029. udma_free_rx_resources(uc);
  2030. udma_reset_uchan(uc);
  2031. uc->in_use = false;
  2032. return 0;
  2033. }
  2034. static int udma_enable(struct dma *dma)
  2035. {
  2036. struct udma_dev *ud = dev_get_priv(dma->dev);
  2037. struct udma_chan *uc;
  2038. int ret;
  2039. if (dma->id >= (ud->rchan_cnt + ud->tchan_cnt)) {
  2040. dev_err(dma->dev, "invalid dma ch_id %lu\n", dma->id);
  2041. return -EINVAL;
  2042. }
  2043. uc = &ud->channels[dma->id];
  2044. ret = udma_start(uc);
  2045. return ret;
  2046. }
  2047. static int udma_disable(struct dma *dma)
  2048. {
  2049. struct udma_dev *ud = dev_get_priv(dma->dev);
  2050. struct udma_chan *uc;
  2051. int ret = 0;
  2052. if (dma->id >= (ud->rchan_cnt + ud->tchan_cnt)) {
  2053. dev_err(dma->dev, "invalid dma ch_id %lu\n", dma->id);
  2054. return -EINVAL;
  2055. }
  2056. uc = &ud->channels[dma->id];
  2057. if (udma_is_chan_running(uc))
  2058. ret = udma_stop(uc);
  2059. else
  2060. dev_err(dma->dev, "%s not running\n", __func__);
  2061. return ret;
  2062. }
  2063. static int udma_send(struct dma *dma, void *src, size_t len, void *metadata)
  2064. {
  2065. struct udma_dev *ud = dev_get_priv(dma->dev);
  2066. struct cppi5_host_desc_t *desc_tx;
  2067. dma_addr_t dma_src = (dma_addr_t)src;
  2068. struct ti_udma_drv_packet_data packet_data = { 0 };
  2069. dma_addr_t paddr;
  2070. struct udma_chan *uc;
  2071. u32 tc_ring_id;
  2072. int ret;
  2073. if (metadata)
  2074. packet_data = *((struct ti_udma_drv_packet_data *)metadata);
  2075. if (dma->id >= (ud->rchan_cnt + ud->tchan_cnt)) {
  2076. dev_err(dma->dev, "invalid dma ch_id %lu\n", dma->id);
  2077. return -EINVAL;
  2078. }
  2079. uc = &ud->channels[dma->id];
  2080. if (uc->config.dir != DMA_MEM_TO_DEV)
  2081. return -EINVAL;
  2082. tc_ring_id = k3_nav_ringacc_get_ring_id(uc->tchan->tc_ring);
  2083. desc_tx = uc->desc_tx;
  2084. cppi5_hdesc_reset_hbdesc(desc_tx);
  2085. cppi5_hdesc_init(desc_tx,
  2086. uc->config.needs_epib ? CPPI5_INFO0_HDESC_EPIB_PRESENT : 0,
  2087. uc->config.psd_size);
  2088. cppi5_hdesc_set_pktlen(desc_tx, len);
  2089. cppi5_hdesc_attach_buf(desc_tx, dma_src, len, dma_src, len);
  2090. cppi5_desc_set_pktids(&desc_tx->hdr, uc->id, 0x3fff);
  2091. cppi5_desc_set_retpolicy(&desc_tx->hdr, 0, tc_ring_id);
  2092. /* pass below information from caller */
  2093. cppi5_hdesc_set_pkttype(desc_tx, packet_data.pkt_type);
  2094. cppi5_desc_set_tags_ids(&desc_tx->hdr, 0, packet_data.dest_tag);
  2095. flush_dcache_range((unsigned long)dma_src,
  2096. ALIGN((unsigned long)dma_src + len,
  2097. ARCH_DMA_MINALIGN));
  2098. flush_dcache_range((unsigned long)desc_tx,
  2099. ALIGN((unsigned long)desc_tx + uc->config.hdesc_size,
  2100. ARCH_DMA_MINALIGN));
  2101. ret = udma_push_to_ring(uc->tchan->t_ring, uc->desc_tx);
  2102. if (ret) {
  2103. dev_err(dma->dev, "TX dma push fail ch_id %lu %d\n",
  2104. dma->id, ret);
  2105. return ret;
  2106. }
  2107. udma_poll_completion(uc, &paddr);
  2108. return 0;
  2109. }
  2110. static int udma_receive(struct dma *dma, void **dst, void *metadata)
  2111. {
  2112. struct udma_dev *ud = dev_get_priv(dma->dev);
  2113. struct udma_chan_config *ucc;
  2114. struct cppi5_host_desc_t *desc_rx;
  2115. dma_addr_t buf_dma;
  2116. struct udma_chan *uc;
  2117. u32 buf_dma_len, pkt_len;
  2118. u32 port_id = 0;
  2119. int ret;
  2120. if (dma->id >= (ud->rchan_cnt + ud->tchan_cnt)) {
  2121. dev_err(dma->dev, "invalid dma ch_id %lu\n", dma->id);
  2122. return -EINVAL;
  2123. }
  2124. uc = &ud->channels[dma->id];
  2125. ucc = &uc->config;
  2126. if (uc->config.dir != DMA_DEV_TO_MEM)
  2127. return -EINVAL;
  2128. if (!uc->num_rx_bufs)
  2129. return -EINVAL;
  2130. ret = k3_nav_ringacc_ring_pop(uc->rflow->r_ring, &desc_rx);
  2131. if (ret && ret != -ENODATA) {
  2132. dev_err(dma->dev, "rx dma fail ch_id:%lu %d\n", dma->id, ret);
  2133. return ret;
  2134. } else if (ret == -ENODATA) {
  2135. return 0;
  2136. }
  2137. /* invalidate cache data */
  2138. invalidate_dcache_range((ulong)desc_rx,
  2139. (ulong)(desc_rx + ucc->hdesc_size));
  2140. cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len);
  2141. pkt_len = cppi5_hdesc_get_pktlen(desc_rx);
  2142. /* invalidate cache data */
  2143. invalidate_dcache_range((ulong)buf_dma,
  2144. (ulong)(buf_dma + buf_dma_len));
  2145. cppi5_desc_get_tags_ids(&desc_rx->hdr, &port_id, NULL);
  2146. *dst = (void *)buf_dma;
  2147. uc->num_rx_bufs--;
  2148. return pkt_len;
  2149. }
  2150. static int udma_of_xlate(struct dma *dma, struct ofnode_phandle_args *args)
  2151. {
  2152. struct udma_chan_config *ucc;
  2153. struct udma_dev *ud = dev_get_priv(dma->dev);
  2154. struct udma_chan *uc = &ud->channels[0];
  2155. struct psil_endpoint_config *ep_config;
  2156. u32 val;
  2157. for (val = 0; val < ud->ch_count; val++) {
  2158. uc = &ud->channels[val];
  2159. if (!uc->in_use)
  2160. break;
  2161. }
  2162. if (val == ud->ch_count)
  2163. return -EBUSY;
  2164. ucc = &uc->config;
  2165. ucc->remote_thread_id = args->args[0];
  2166. if (ucc->remote_thread_id & K3_PSIL_DST_THREAD_ID_OFFSET)
  2167. ucc->dir = DMA_MEM_TO_DEV;
  2168. else
  2169. ucc->dir = DMA_DEV_TO_MEM;
  2170. ep_config = psil_get_ep_config(ucc->remote_thread_id);
  2171. if (IS_ERR(ep_config)) {
  2172. dev_err(ud->dev, "No configuration for psi-l thread 0x%04x\n",
  2173. uc->config.remote_thread_id);
  2174. ucc->dir = DMA_MEM_TO_MEM;
  2175. ucc->remote_thread_id = -1;
  2176. return false;
  2177. }
  2178. ucc->pkt_mode = ep_config->pkt_mode;
  2179. ucc->channel_tpl = ep_config->channel_tpl;
  2180. ucc->notdpkt = ep_config->notdpkt;
  2181. ucc->ep_type = ep_config->ep_type;
  2182. if (ud->match_data->type == DMA_TYPE_PKTDMA &&
  2183. ep_config->mapped_channel_id >= 0) {
  2184. ucc->mapped_channel_id = ep_config->mapped_channel_id;
  2185. ucc->default_flow_id = ep_config->default_flow_id;
  2186. } else {
  2187. ucc->mapped_channel_id = -1;
  2188. ucc->default_flow_id = -1;
  2189. }
  2190. ucc->needs_epib = ep_config->needs_epib;
  2191. ucc->psd_size = ep_config->psd_size;
  2192. ucc->metadata_size = (ucc->needs_epib ? CPPI5_INFO0_HDESC_EPIB_SIZE : 0) + ucc->psd_size;
  2193. ucc->hdesc_size = cppi5_hdesc_calc_size(ucc->needs_epib,
  2194. ucc->psd_size, 0);
  2195. ucc->hdesc_size = ALIGN(ucc->hdesc_size, ARCH_DMA_MINALIGN);
  2196. dma->id = uc->id;
  2197. pr_debug("Allocated dma chn:%lu epib:%d psdata:%u meta:%u thread_id:%x\n",
  2198. dma->id, ucc->needs_epib,
  2199. ucc->psd_size, ucc->metadata_size,
  2200. ucc->remote_thread_id);
  2201. return 0;
  2202. }
  2203. int udma_prepare_rcv_buf(struct dma *dma, void *dst, size_t size)
  2204. {
  2205. struct udma_dev *ud = dev_get_priv(dma->dev);
  2206. struct cppi5_host_desc_t *desc_rx;
  2207. dma_addr_t dma_dst;
  2208. struct udma_chan *uc;
  2209. u32 desc_num;
  2210. if (dma->id >= (ud->rchan_cnt + ud->tchan_cnt)) {
  2211. dev_err(dma->dev, "invalid dma ch_id %lu\n", dma->id);
  2212. return -EINVAL;
  2213. }
  2214. uc = &ud->channels[dma->id];
  2215. if (uc->config.dir != DMA_DEV_TO_MEM)
  2216. return -EINVAL;
  2217. if (uc->num_rx_bufs >= UDMA_RX_DESC_NUM)
  2218. return -EINVAL;
  2219. desc_num = uc->desc_rx_cur % UDMA_RX_DESC_NUM;
  2220. desc_rx = uc->desc_rx + (desc_num * uc->config.hdesc_size);
  2221. dma_dst = (dma_addr_t)dst;
  2222. cppi5_hdesc_reset_hbdesc(desc_rx);
  2223. cppi5_hdesc_init(desc_rx,
  2224. uc->config.needs_epib ? CPPI5_INFO0_HDESC_EPIB_PRESENT : 0,
  2225. uc->config.psd_size);
  2226. cppi5_hdesc_set_pktlen(desc_rx, size);
  2227. cppi5_hdesc_attach_buf(desc_rx, dma_dst, size, dma_dst, size);
  2228. flush_dcache_range((unsigned long)desc_rx,
  2229. ALIGN((unsigned long)desc_rx + uc->config.hdesc_size,
  2230. ARCH_DMA_MINALIGN));
  2231. udma_push_to_ring(uc->rflow->fd_ring, desc_rx);
  2232. uc->num_rx_bufs++;
  2233. uc->desc_rx_cur++;
  2234. return 0;
  2235. }
  2236. static int udma_get_cfg(struct dma *dma, u32 id, void **data)
  2237. {
  2238. struct udma_dev *ud = dev_get_priv(dma->dev);
  2239. struct udma_chan *uc;
  2240. if (dma->id >= (ud->rchan_cnt + ud->tchan_cnt)) {
  2241. dev_err(dma->dev, "invalid dma ch_id %lu\n", dma->id);
  2242. return -EINVAL;
  2243. }
  2244. switch (id) {
  2245. case TI_UDMA_CHAN_PRIV_INFO:
  2246. uc = &ud->channels[dma->id];
  2247. *data = &uc->cfg_data;
  2248. return 0;
  2249. }
  2250. return -EINVAL;
  2251. }
  2252. static const struct dma_ops udma_ops = {
  2253. .transfer = udma_transfer,
  2254. .of_xlate = udma_of_xlate,
  2255. .request = udma_request,
  2256. .rfree = udma_rfree,
  2257. .enable = udma_enable,
  2258. .disable = udma_disable,
  2259. .send = udma_send,
  2260. .receive = udma_receive,
  2261. .prepare_rcv_buf = udma_prepare_rcv_buf,
  2262. .get_cfg = udma_get_cfg,
  2263. };
  2264. static struct udma_match_data am654_main_data = {
  2265. .type = DMA_TYPE_UDMA,
  2266. .psil_base = 0x1000,
  2267. .enable_memcpy_support = true,
  2268. .statictr_z_mask = GENMASK(11, 0),
  2269. .oes = {
  2270. .udma_rchan = 0x200,
  2271. },
  2272. .tpl_levels = 2,
  2273. .level_start_idx = {
  2274. [0] = 8, /* Normal channels */
  2275. [1] = 0, /* High Throughput channels */
  2276. },
  2277. };
  2278. static struct udma_match_data am654_mcu_data = {
  2279. .type = DMA_TYPE_UDMA,
  2280. .psil_base = 0x6000,
  2281. .enable_memcpy_support = true,
  2282. .statictr_z_mask = GENMASK(11, 0),
  2283. .oes = {
  2284. .udma_rchan = 0x200,
  2285. },
  2286. .tpl_levels = 2,
  2287. .level_start_idx = {
  2288. [0] = 2, /* Normal channels */
  2289. [1] = 0, /* High Throughput channels */
  2290. },
  2291. };
  2292. static struct udma_match_data j721e_main_data = {
  2293. .type = DMA_TYPE_UDMA,
  2294. .psil_base = 0x1000,
  2295. .enable_memcpy_support = true,
  2296. .flags = UDMA_FLAG_PDMA_ACC32 | UDMA_FLAG_PDMA_BURST | UDMA_FLAG_TDTYPE,
  2297. .statictr_z_mask = GENMASK(23, 0),
  2298. .oes = {
  2299. .udma_rchan = 0x400,
  2300. },
  2301. .tpl_levels = 3,
  2302. .level_start_idx = {
  2303. [0] = 16, /* Normal channels */
  2304. [1] = 4, /* High Throughput channels */
  2305. [2] = 0, /* Ultra High Throughput channels */
  2306. },
  2307. };
  2308. static struct udma_match_data j721e_mcu_data = {
  2309. .type = DMA_TYPE_UDMA,
  2310. .psil_base = 0x6000,
  2311. .enable_memcpy_support = true,
  2312. .flags = UDMA_FLAG_PDMA_ACC32 | UDMA_FLAG_PDMA_BURST | UDMA_FLAG_TDTYPE,
  2313. .statictr_z_mask = GENMASK(23, 0),
  2314. .oes = {
  2315. .udma_rchan = 0x400,
  2316. },
  2317. .tpl_levels = 2,
  2318. .level_start_idx = {
  2319. [0] = 2, /* Normal channels */
  2320. [1] = 0, /* High Throughput channels */
  2321. },
  2322. };
  2323. static struct udma_match_data am64_bcdma_data = {
  2324. .type = DMA_TYPE_BCDMA,
  2325. .psil_base = 0x2000, /* for tchan and rchan, not applicable to bchan */
  2326. .enable_memcpy_support = true, /* Supported via bchan */
  2327. .flags = UDMA_FLAG_PDMA_ACC32 | UDMA_FLAG_PDMA_BURST | UDMA_FLAG_TDTYPE,
  2328. .statictr_z_mask = GENMASK(23, 0),
  2329. .oes = {
  2330. .bcdma_bchan_data = 0x2200,
  2331. .bcdma_bchan_ring = 0x2400,
  2332. .bcdma_tchan_data = 0x2800,
  2333. .bcdma_tchan_ring = 0x2a00,
  2334. .bcdma_rchan_data = 0x2e00,
  2335. .bcdma_rchan_ring = 0x3000,
  2336. },
  2337. /* No throughput levels */
  2338. };
  2339. static struct udma_match_data am64_pktdma_data = {
  2340. .type = DMA_TYPE_PKTDMA,
  2341. .psil_base = 0x1000,
  2342. .enable_memcpy_support = false,
  2343. .flags = UDMA_FLAG_PDMA_ACC32 | UDMA_FLAG_PDMA_BURST | UDMA_FLAG_TDTYPE,
  2344. .statictr_z_mask = GENMASK(23, 0),
  2345. .oes = {
  2346. .pktdma_tchan_flow = 0x1200,
  2347. .pktdma_rchan_flow = 0x1600,
  2348. },
  2349. /* No throughput levels */
  2350. };
  2351. static const struct udevice_id udma_ids[] = {
  2352. {
  2353. .compatible = "ti,am654-navss-main-udmap",
  2354. .data = (ulong)&am654_main_data,
  2355. },
  2356. {
  2357. .compatible = "ti,am654-navss-mcu-udmap",
  2358. .data = (ulong)&am654_mcu_data,
  2359. }, {
  2360. .compatible = "ti,j721e-navss-main-udmap",
  2361. .data = (ulong)&j721e_main_data,
  2362. }, {
  2363. .compatible = "ti,j721e-navss-mcu-udmap",
  2364. .data = (ulong)&j721e_mcu_data,
  2365. },
  2366. {
  2367. .compatible = "ti,am64-dmss-bcdma",
  2368. .data = (ulong)&am64_bcdma_data,
  2369. },
  2370. {
  2371. .compatible = "ti,am64-dmss-pktdma",
  2372. .data = (ulong)&am64_pktdma_data,
  2373. },
  2374. { /* Sentinel */ },
  2375. };
  2376. U_BOOT_DRIVER(ti_edma3) = {
  2377. .name = "ti-udma",
  2378. .id = UCLASS_DMA,
  2379. .of_match = udma_ids,
  2380. .ops = &udma_ops,
  2381. .probe = udma_probe,
  2382. .priv_auto = sizeof(struct udma_dev),
  2383. };