lpc32xx_dma.c 3.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2008 by NXP Semiconductors
  4. * @Author: Kevin Wells
  5. * @Descr: LPC3250 DMA controller interface support functions
  6. *
  7. * Copyright (c) 2015 Tyco Fire Protection Products.
  8. */
  9. #include <common.h>
  10. #include <errno.h>
  11. #include <init.h>
  12. #include <asm/arch/dma.h>
  13. #include <asm/arch/cpu.h>
  14. #include <asm/arch/clk.h>
  15. #include <asm/arch/sys_proto.h>
  16. #include <asm/io.h>
  17. #include <linux/bitops.h>
  18. #include <linux/delay.h>
  19. /* DMA controller channel register structure */
  20. struct dmac_chan_reg {
  21. u32 src_addr;
  22. u32 dest_addr;
  23. u32 lli;
  24. u32 control;
  25. u32 config_ch;
  26. u32 reserved[3];
  27. };
  28. /* DMA controller register structures */
  29. struct dma_reg {
  30. u32 int_stat;
  31. u32 int_tc_stat;
  32. u32 int_tc_clear;
  33. u32 int_err_stat;
  34. u32 int_err_clear;
  35. u32 raw_tc_stat;
  36. u32 raw_err_stat;
  37. u32 chan_enable;
  38. u32 sw_burst_req;
  39. u32 sw_single_req;
  40. u32 sw_last_burst_req;
  41. u32 sw_last_single_req;
  42. u32 config;
  43. u32 sync;
  44. u32 reserved[50];
  45. struct dmac_chan_reg dma_chan[8];
  46. };
  47. #define DMA_NO_OF_CHANNELS 8
  48. /* config register definitions */
  49. #define DMAC_CTRL_ENABLE (1 << 0) /* For enabling the DMA controller */
  50. static u32 alloc_ch;
  51. static struct dma_reg *dma = (struct dma_reg *)DMA_BASE;
  52. int lpc32xx_dma_get_channel(void)
  53. {
  54. int i;
  55. if (!alloc_ch) { /* First time caller */
  56. /*
  57. * DMA clock are enable by "lpc32xx_dma_init()" and should
  58. * be call by board "board_early_init_f()" function.
  59. */
  60. /*
  61. * Make sure DMA controller and all channels are disabled.
  62. * Controller is in little-endian mode. Disable sync signals.
  63. */
  64. writel(0, &dma->config);
  65. writel(0, &dma->sync);
  66. /* Clear interrupt and error statuses */
  67. writel(0xFF, &dma->int_tc_clear);
  68. writel(0xFF, &dma->raw_tc_stat);
  69. writel(0xFF, &dma->int_err_clear);
  70. writel(0xFF, &dma->raw_err_stat);
  71. /* Enable DMA controller */
  72. writel(DMAC_CTRL_ENABLE, &dma->config);
  73. }
  74. i = ffz(alloc_ch);
  75. /* Check if all the available channels are busy */
  76. if (unlikely(i == DMA_NO_OF_CHANNELS))
  77. return -1;
  78. alloc_ch |= BIT_MASK(i);
  79. return i;
  80. }
  81. int lpc32xx_dma_start_xfer(unsigned int channel,
  82. const struct lpc32xx_dmac_ll *desc, u32 config)
  83. {
  84. if (unlikely(((BIT_MASK(channel) & alloc_ch) == 0) ||
  85. (channel >= DMA_NO_OF_CHANNELS))) {
  86. pr_err("Request for xfer on unallocated channel %d", channel);
  87. return -1;
  88. }
  89. writel(BIT_MASK(channel), &dma->int_tc_clear);
  90. writel(BIT_MASK(channel), &dma->int_err_clear);
  91. writel(desc->dma_src, &dma->dma_chan[channel].src_addr);
  92. writel(desc->dma_dest, &dma->dma_chan[channel].dest_addr);
  93. writel(desc->next_lli, &dma->dma_chan[channel].lli);
  94. writel(desc->next_ctrl, &dma->dma_chan[channel].control);
  95. writel(config, &dma->dma_chan[channel].config_ch);
  96. return 0;
  97. }
  98. int lpc32xx_dma_wait_status(unsigned int channel)
  99. {
  100. unsigned long start;
  101. u32 reg;
  102. /* Check if given channel is valid */
  103. if (unlikely(channel >= DMA_NO_OF_CHANNELS)) {
  104. pr_err("Request for status on unallocated channel %d", channel);
  105. return -1;
  106. }
  107. start = get_timer(0);
  108. while (1) {
  109. reg = readl(&dma->raw_tc_stat);
  110. reg |= readl(dma->raw_err_stat);
  111. if (reg & BIT_MASK(channel))
  112. break;
  113. if (get_timer(start) > CONFIG_SYS_HZ) {
  114. pr_err("DMA status timeout channel %d\n", channel);
  115. return -ETIMEDOUT;
  116. }
  117. udelay(1);
  118. }
  119. if (unlikely(readl(&dma->raw_err_stat) & BIT_MASK(channel))) {
  120. setbits_le32(&dma->int_err_clear, BIT_MASK(channel));
  121. setbits_le32(&dma->raw_err_stat, BIT_MASK(channel));
  122. pr_err("DMA error on channel %d\n", channel);
  123. return -1;
  124. }
  125. setbits_le32(&dma->int_tc_clear, BIT_MASK(channel));
  126. setbits_le32(&dma->raw_tc_stat, BIT_MASK(channel));
  127. return 0;
  128. }