fsl_dma.c 3.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2004,2007,2008 Freescale Semiconductor, Inc.
  4. * (C) Copyright 2002, 2003 Motorola Inc.
  5. * Xianghua Xiao (X.Xiao@motorola.com)
  6. *
  7. * (C) Copyright 2000
  8. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  9. */
  10. #include <config.h>
  11. #include <common.h>
  12. #include <asm/io.h>
  13. #include <asm/fsl_dma.h>
  14. /* Controller can only transfer 2^26 - 1 bytes at a time */
  15. #define FSL_DMA_MAX_SIZE (0x3ffffff)
  16. #if defined(CONFIG_MPC83xx)
  17. #define FSL_DMA_MR_DEFAULT (FSL_DMA_MR_CTM_DIRECT | FSL_DMA_MR_DMSEN)
  18. #else
  19. #define FSL_DMA_MR_DEFAULT (FSL_DMA_MR_BWC_DIS | FSL_DMA_MR_CTM_DIRECT)
  20. #endif
  21. #if defined(CONFIG_MPC83xx)
  22. dma83xx_t *dma_base = (void *)(CONFIG_SYS_MPC83xx_DMA_ADDR);
  23. #elif defined(CONFIG_MPC85xx)
  24. ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
  25. #elif defined(CONFIG_MPC86xx)
  26. ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR);
  27. #else
  28. #error "Freescale DMA engine not supported on your processor"
  29. #endif
  30. static void dma_sync(void)
  31. {
  32. #if defined(CONFIG_MPC85xx)
  33. asm("sync; isync; msync");
  34. #elif defined(CONFIG_MPC86xx)
  35. asm("sync; isync");
  36. #endif
  37. }
  38. static void out_dma32(volatile unsigned *addr, int val)
  39. {
  40. #if defined(CONFIG_MPC83xx)
  41. out_le32(addr, val);
  42. #else
  43. out_be32(addr, val);
  44. #endif
  45. }
  46. static uint in_dma32(volatile unsigned *addr)
  47. {
  48. #if defined(CONFIG_MPC83xx)
  49. return in_le32(addr);
  50. #else
  51. return in_be32(addr);
  52. #endif
  53. }
  54. static uint dma_check(void) {
  55. volatile fsl_dma_t *dma = &dma_base->dma[0];
  56. uint status;
  57. /* While the channel is busy, spin */
  58. do {
  59. status = in_dma32(&dma->sr);
  60. } while (status & FSL_DMA_SR_CB);
  61. /* clear MR[CS] channel start bit */
  62. out_dma32(&dma->mr, in_dma32(&dma->mr) & ~FSL_DMA_MR_CS);
  63. dma_sync();
  64. if (status != 0)
  65. printf ("DMA Error: status = %x\n", status);
  66. return status;
  67. }
  68. #if !defined(CONFIG_MPC83xx)
  69. void dma_init(void) {
  70. volatile fsl_dma_t *dma = &dma_base->dma[0];
  71. out_dma32(&dma->satr, FSL_DMA_SATR_SREAD_SNOOP);
  72. out_dma32(&dma->datr, FSL_DMA_DATR_DWRITE_SNOOP);
  73. out_dma32(&dma->sr, 0xffffffff); /* clear any errors */
  74. dma_sync();
  75. }
  76. #endif
  77. int dmacpy(phys_addr_t dest, phys_addr_t src, phys_size_t count) {
  78. volatile fsl_dma_t *dma = &dma_base->dma[0];
  79. uint xfer_size;
  80. while (count) {
  81. xfer_size = min(FSL_DMA_MAX_SIZE, count);
  82. out_dma32(&dma->dar, (u32) (dest & 0xFFFFFFFF));
  83. out_dma32(&dma->sar, (u32) (src & 0xFFFFFFFF));
  84. #if !defined(CONFIG_MPC83xx)
  85. out_dma32(&dma->satr,
  86. in_dma32(&dma->satr) | (u32)((u64)src >> 32));
  87. out_dma32(&dma->datr,
  88. in_dma32(&dma->datr) | (u32)((u64)dest >> 32));
  89. #endif
  90. out_dma32(&dma->bcr, xfer_size);
  91. dma_sync();
  92. /* Prepare mode register */
  93. out_dma32(&dma->mr, FSL_DMA_MR_DEFAULT);
  94. dma_sync();
  95. /* Start the transfer */
  96. out_dma32(&dma->mr, FSL_DMA_MR_DEFAULT | FSL_DMA_MR_CS);
  97. count -= xfer_size;
  98. src += xfer_size;
  99. dest += xfer_size;
  100. dma_sync();
  101. if (dma_check())
  102. return -1;
  103. }
  104. return 0;
  105. }
  106. /*
  107. * 85xx/86xx use dma to initialize SDRAM when !CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  108. * while 83xx uses dma to initialize SDRAM when CONFIG_DDR_ECC_INIT_VIA_DMA
  109. */
  110. #if ((!defined CONFIG_MPC83xx && defined(CONFIG_DDR_ECC) && \
  111. !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)) || \
  112. (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)))
  113. void dma_meminit(uint val, uint size)
  114. {
  115. uint *p = 0;
  116. uint i = 0;
  117. for (*p = 0; p < (uint *)(8 * 1024); p++) {
  118. if (((uint)p & 0x1f) == 0)
  119. ppcDcbz((ulong)p);
  120. *p = (uint)CONFIG_MEM_INIT_VALUE;
  121. if (((uint)p & 0x1c) == 0x1c)
  122. ppcDcbf((ulong)p);
  123. }
  124. dmacpy(0x002000, 0, 0x002000); /* 8K */
  125. dmacpy(0x004000, 0, 0x004000); /* 16K */
  126. dmacpy(0x008000, 0, 0x008000); /* 32K */
  127. dmacpy(0x010000, 0, 0x010000); /* 64K */
  128. dmacpy(0x020000, 0, 0x020000); /* 128K */
  129. dmacpy(0x040000, 0, 0x040000); /* 256K */
  130. dmacpy(0x080000, 0, 0x080000); /* 512K */
  131. dmacpy(0x100000, 0, 0x100000); /* 1M */
  132. dmacpy(0x200000, 0, 0x200000); /* 2M */
  133. dmacpy(0x400000, 0, 0x400000); /* 4M */
  134. for (i = 1; i < size / 0x800000; i++)
  135. dmacpy((0x800000 * i), 0, 0x800000);
  136. }
  137. #endif