mpc85xx_ddr_gen1.c 2.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright 2008 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <log.h>
  7. #include <asm/io.h>
  8. #include <fsl_ddr_sdram.h>
  9. #include <linux/delay.h>
  10. #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
  11. #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
  12. #endif
  13. void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
  14. unsigned int ctrl_num, int step)
  15. {
  16. unsigned int i;
  17. struct ccsr_ddr __iomem *ddr =
  18. (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
  19. if (ctrl_num != 0) {
  20. printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
  21. return;
  22. }
  23. for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  24. if (i == 0) {
  25. out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
  26. out_be32(&ddr->cs0_config, regs->cs[i].config);
  27. } else if (i == 1) {
  28. out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
  29. out_be32(&ddr->cs1_config, regs->cs[i].config);
  30. } else if (i == 2) {
  31. out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
  32. out_be32(&ddr->cs2_config, regs->cs[i].config);
  33. } else if (i == 3) {
  34. out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
  35. out_be32(&ddr->cs3_config, regs->cs[i].config);
  36. }
  37. }
  38. out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
  39. out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
  40. out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
  41. out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
  42. /*
  43. * 200 painful micro-seconds must elapse between
  44. * the DDR clock setup and the DDR config enable.
  45. */
  46. udelay(200);
  47. asm volatile("sync;isync");
  48. out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
  49. asm("sync;isync;msync");
  50. udelay(500);
  51. }
  52. #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  53. /*
  54. * Initialize all of memory for ECC, then enable errors.
  55. */
  56. void
  57. ddr_enable_ecc(unsigned int dram_size)
  58. {
  59. struct ccsr_ddr __iomem *ddr =
  60. (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
  61. dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size);
  62. /*
  63. * Enable errors for ECC.
  64. */
  65. debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable);
  66. ddr->err_disable = 0x00000000;
  67. asm("sync;isync;msync");
  68. debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable);
  69. }
  70. #endif /* CONFIG_DDR_ECC && ! CONFIG_ECC_INIT_VIA_DDRCONTROLLER */