ddr1_dimm_params.c 8.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright 2008 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <fsl_ddr_sdram.h>
  7. #include <log.h>
  8. #include <asm/bitops.h>
  9. #include <fsl_ddr.h>
  10. /*
  11. * Calculate the Density of each Physical Rank.
  12. * Returned size is in bytes.
  13. *
  14. * Study these table from Byte 31 of JEDEC SPD Spec.
  15. *
  16. * DDR I DDR II
  17. * Bit Size Size
  18. * --- ----- ------
  19. * 7 high 512MB 512MB
  20. * 6 256MB 256MB
  21. * 5 128MB 128MB
  22. * 4 64MB 16GB
  23. * 3 32MB 8GB
  24. * 2 16MB 4GB
  25. * 1 2GB 2GB
  26. * 0 low 1GB 1GB
  27. *
  28. * Reorder Table to be linear by stripping the bottom
  29. * 2 or 5 bits off and shifting them up to the top.
  30. */
  31. static unsigned long long
  32. compute_ranksize(unsigned int mem_type, unsigned char row_dens)
  33. {
  34. unsigned long long bsize;
  35. /* Bottom 2 bits up to the top. */
  36. bsize = ((row_dens >> 2) | ((row_dens & 3) << 6));
  37. bsize <<= 24ULL;
  38. debug("DDR: DDR I rank density = 0x%16llx\n", bsize);
  39. return bsize;
  40. }
  41. /*
  42. * Convert a two-nibble BCD value into a cycle time.
  43. * While the spec calls for nano-seconds, picos are returned.
  44. *
  45. * This implements the tables for bytes 9, 23 and 25 for both
  46. * DDR I and II. No allowance for distinguishing the invalid
  47. * fields absent for DDR I yet present in DDR II is made.
  48. * (That is, cycle times of .25, .33, .66 and .75 ns are
  49. * allowed for both DDR II and I.)
  50. */
  51. static unsigned int
  52. convert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val)
  53. {
  54. /* Table look up the lower nibble, allow DDR I & II. */
  55. unsigned int tenths_ps[16] = {
  56. 0,
  57. 100,
  58. 200,
  59. 300,
  60. 400,
  61. 500,
  62. 600,
  63. 700,
  64. 800,
  65. 900,
  66. 250, /* This and the next 3 entries valid ... */
  67. 330, /* ... only for tCK calculations. */
  68. 660,
  69. 750,
  70. 0, /* undefined */
  71. 0 /* undefined */
  72. };
  73. unsigned int whole_ns = (spd_val & 0xF0) >> 4;
  74. unsigned int tenth_ns = spd_val & 0x0F;
  75. unsigned int ps = whole_ns * 1000 + tenths_ps[tenth_ns];
  76. return ps;
  77. }
  78. static unsigned int
  79. convert_bcd_hundredths_to_cycle_time_ps(unsigned int spd_val)
  80. {
  81. unsigned int tenth_ns = (spd_val & 0xF0) >> 4;
  82. unsigned int hundredth_ns = spd_val & 0x0F;
  83. unsigned int ps = tenth_ns * 100 + hundredth_ns * 10;
  84. return ps;
  85. }
  86. static unsigned int byte40_table_ps[8] = {
  87. 0,
  88. 250,
  89. 330,
  90. 500,
  91. 660,
  92. 750,
  93. 0, /* supposed to be RFC, but not sure what that means */
  94. 0 /* Undefined */
  95. };
  96. static unsigned int
  97. compute_trfc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trfc)
  98. {
  99. return ((trctrfc_ext & 0x1) * 256 + trfc) * 1000
  100. + byte40_table_ps[(trctrfc_ext >> 1) & 0x7];
  101. }
  102. static unsigned int
  103. compute_trc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trc)
  104. {
  105. return trc * 1000 + byte40_table_ps[(trctrfc_ext >> 4) & 0x7];
  106. }
  107. /*
  108. * tCKmax from DDR I SPD Byte 43
  109. *
  110. * Bits 7:2 == whole ns
  111. * Bits 1:0 == quarter ns
  112. * 00 == 0.00 ns
  113. * 01 == 0.25 ns
  114. * 10 == 0.50 ns
  115. * 11 == 0.75 ns
  116. *
  117. * Returns picoseconds.
  118. */
  119. static unsigned int
  120. compute_tckmax_from_spd_ps(unsigned int byte43)
  121. {
  122. return (byte43 >> 2) * 1000 + (byte43 & 0x3) * 250;
  123. }
  124. /*
  125. * Determine Refresh Rate. Ignore self refresh bit on DDR I.
  126. * Table from SPD Spec, Byte 12, converted to picoseconds and
  127. * filled in with "default" normal values.
  128. */
  129. static unsigned int
  130. determine_refresh_rate_ps(const unsigned int spd_refresh)
  131. {
  132. unsigned int refresh_time_ps[8] = {
  133. 15625000, /* 0 Normal 1.00x */
  134. 3900000, /* 1 Reduced .25x */
  135. 7800000, /* 2 Extended .50x */
  136. 31300000, /* 3 Extended 2.00x */
  137. 62500000, /* 4 Extended 4.00x */
  138. 125000000, /* 5 Extended 8.00x */
  139. 15625000, /* 6 Normal 1.00x filler */
  140. 15625000, /* 7 Normal 1.00x filler */
  141. };
  142. return refresh_time_ps[spd_refresh & 0x7];
  143. }
  144. /*
  145. * The purpose of this function is to compute a suitable
  146. * CAS latency given the DRAM clock period. The SPD only
  147. * defines at most 3 CAS latencies. Typically the slower in
  148. * frequency the DIMM runs at, the shorter its CAS latency can be.
  149. * If the DIMM is operating at a sufficiently low frequency,
  150. * it may be able to run at a CAS latency shorter than the
  151. * shortest SPD-defined CAS latency.
  152. *
  153. * If a CAS latency is not found, 0 is returned.
  154. *
  155. * Do this by finding in the standard speed bin table the longest
  156. * tCKmin that doesn't exceed the value of mclk_ps (tCK).
  157. *
  158. * An assumption made is that the SDRAM device allows the
  159. * CL to be programmed for a value that is lower than those
  160. * advertised by the SPD. This is not always the case,
  161. * as those modes not defined in the SPD are optional.
  162. *
  163. * CAS latency de-rating based upon values JEDEC Standard No. 79-E
  164. * Table 11.
  165. *
  166. * ordinal 2, ddr1_speed_bins[1] contains tCK for CL=2
  167. */
  168. /* CL2.0 CL2.5 CL3.0 */
  169. unsigned short ddr1_speed_bins[] = {0, 7500, 6000, 5000 };
  170. unsigned int
  171. compute_derated_DDR1_CAS_latency(unsigned int mclk_ps)
  172. {
  173. const unsigned int num_speed_bins = ARRAY_SIZE(ddr1_speed_bins);
  174. unsigned int lowest_tCKmin_found = 0;
  175. unsigned int lowest_tCKmin_CL = 0;
  176. unsigned int i;
  177. debug("mclk_ps = %u\n", mclk_ps);
  178. for (i = 0; i < num_speed_bins; i++) {
  179. unsigned int x = ddr1_speed_bins[i];
  180. debug("i=%u, x = %u, lowest_tCKmin_found = %u\n",
  181. i, x, lowest_tCKmin_found);
  182. if (x && lowest_tCKmin_found <= x && x <= mclk_ps) {
  183. lowest_tCKmin_found = x;
  184. lowest_tCKmin_CL = i + 1;
  185. }
  186. }
  187. debug("lowest_tCKmin_CL = %u\n", lowest_tCKmin_CL);
  188. return lowest_tCKmin_CL;
  189. }
  190. /*
  191. * ddr_compute_dimm_parameters for DDR1 SPD
  192. *
  193. * Compute DIMM parameters based upon the SPD information in spd.
  194. * Writes the results to the dimm_params_t structure pointed by pdimm.
  195. *
  196. * FIXME: use #define for the retvals
  197. */
  198. unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num,
  199. const ddr1_spd_eeprom_t *spd,
  200. dimm_params_t *pdimm,
  201. unsigned int dimm_number)
  202. {
  203. unsigned int retval;
  204. if (spd->mem_type) {
  205. if (spd->mem_type != SPD_MEMTYPE_DDR) {
  206. printf("DIMM %u: is not a DDR1 SPD.\n", dimm_number);
  207. return 1;
  208. }
  209. } else {
  210. memset(pdimm, 0, sizeof(dimm_params_t));
  211. return 1;
  212. }
  213. retval = ddr1_spd_check(spd);
  214. if (retval) {
  215. printf("DIMM %u: failed checksum\n", dimm_number);
  216. return 2;
  217. }
  218. /*
  219. * The part name in ASCII in the SPD EEPROM is not null terminated.
  220. * Guarantee null termination here by presetting all bytes to 0
  221. * and copying the part name in ASCII from the SPD onto it
  222. */
  223. memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
  224. memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1);
  225. /* DIMM organization parameters */
  226. pdimm->n_ranks = spd->nrows;
  227. pdimm->rank_density = compute_ranksize(spd->mem_type, spd->bank_dens);
  228. pdimm->capacity = pdimm->n_ranks * pdimm->rank_density;
  229. pdimm->data_width = spd->dataw_lsb;
  230. pdimm->primary_sdram_width = spd->primw;
  231. pdimm->ec_sdram_width = spd->ecw;
  232. /*
  233. * FIXME: Need to determine registered_dimm status.
  234. * 1 == register buffered
  235. * 0 == unbuffered
  236. */
  237. pdimm->registered_dimm = 0; /* unbuffered */
  238. /* SDRAM device parameters */
  239. pdimm->n_row_addr = spd->nrow_addr;
  240. pdimm->n_col_addr = spd->ncol_addr;
  241. pdimm->n_banks_per_sdram_device = spd->nbanks;
  242. pdimm->edc_config = spd->config;
  243. pdimm->burst_lengths_bitmask = spd->burstl;
  244. /*
  245. * Calculate the Maximum Data Rate based on the Minimum Cycle time.
  246. * The SPD clk_cycle field (tCKmin) is measured in tenths of
  247. * nanoseconds and represented as BCD.
  248. */
  249. pdimm->tckmin_x_ps
  250. = convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle);
  251. pdimm->tckmin_x_minus_1_ps
  252. = convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle2);
  253. pdimm->tckmin_x_minus_2_ps
  254. = convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle3);
  255. pdimm->tckmax_ps = compute_tckmax_from_spd_ps(spd->tckmax);
  256. /*
  257. * Compute CAS latencies defined by SPD
  258. * The SPD caslat_x should have at least 1 and at most 3 bits set.
  259. *
  260. * If cas_lat after masking is 0, the __ilog2 function returns
  261. * 255 into the variable. This behavior is abused once.
  262. */
  263. pdimm->caslat_x = __ilog2(spd->cas_lat);
  264. pdimm->caslat_x_minus_1 = __ilog2(spd->cas_lat
  265. & ~(1 << pdimm->caslat_x));
  266. pdimm->caslat_x_minus_2 = __ilog2(spd->cas_lat
  267. & ~(1 << pdimm->caslat_x)
  268. & ~(1 << pdimm->caslat_x_minus_1));
  269. /* Compute CAS latencies below that defined by SPD */
  270. pdimm->caslat_lowest_derated = compute_derated_DDR1_CAS_latency(
  271. get_memory_clk_period_ps(ctrl_num));
  272. /* Compute timing parameters */
  273. pdimm->trcd_ps = spd->trcd * 250;
  274. pdimm->trp_ps = spd->trp * 250;
  275. pdimm->tras_ps = spd->tras * 1000;
  276. pdimm->twr_ps = mclk_to_picos(ctrl_num, 3);
  277. pdimm->twtr_ps = mclk_to_picos(ctrl_num, 1);
  278. pdimm->trfc_ps = compute_trfc_ps_from_spd(0, spd->trfc);
  279. pdimm->trrd_ps = spd->trrd * 250;
  280. pdimm->trc_ps = compute_trc_ps_from_spd(0, spd->trc);
  281. pdimm->refresh_rate_ps = determine_refresh_rate_ps(spd->refresh);
  282. pdimm->tis_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_setup);
  283. pdimm->tih_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_hold);
  284. pdimm->tds_ps
  285. = convert_bcd_hundredths_to_cycle_time_ps(spd->data_setup);
  286. pdimm->tdh_ps
  287. = convert_bcd_hundredths_to_cycle_time_ps(spd->data_hold);
  288. pdimm->trtp_ps = mclk_to_picos(ctrl_num, 2); /* By the book. */
  289. pdimm->tdqsq_max_ps = spd->tdqsq * 10;
  290. pdimm->tqhs_ps = spd->tqhs * 10;
  291. return 0;
  292. }