sdram_s10.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
  4. *
  5. */
  6. #include <common.h>
  7. #include <cpu_func.h>
  8. #include <dm.h>
  9. #include <errno.h>
  10. #include <div64.h>
  11. #include <fdtdec.h>
  12. #include <hang.h>
  13. #include <init.h>
  14. #include <log.h>
  15. #include <ram.h>
  16. #include <reset.h>
  17. #include <asm/global_data.h>
  18. #include "sdram_s10.h"
  19. #include <wait_bit.h>
  20. #include <asm/arch/firewall.h>
  21. #include <asm/arch/reset_manager.h>
  22. #include <asm/io.h>
  23. #include <linux/sizes.h>
  24. DECLARE_GLOBAL_DATA_PTR;
  25. #define DDR_CONFIG(A, B, C, R) (((A) << 24) | ((B) << 16) | ((C) << 8) | (R))
  26. /* The followring are the supported configurations */
  27. u32 ddr_config[] = {
  28. /* DDR_CONFIG(Address order,Bank,Column,Row) */
  29. /* List for DDR3 or LPDDR3 (pinout order > chip, row, bank, column) */
  30. DDR_CONFIG(0, 3, 10, 12),
  31. DDR_CONFIG(0, 3, 9, 13),
  32. DDR_CONFIG(0, 3, 10, 13),
  33. DDR_CONFIG(0, 3, 9, 14),
  34. DDR_CONFIG(0, 3, 10, 14),
  35. DDR_CONFIG(0, 3, 10, 15),
  36. DDR_CONFIG(0, 3, 11, 14),
  37. DDR_CONFIG(0, 3, 11, 15),
  38. DDR_CONFIG(0, 3, 10, 16),
  39. DDR_CONFIG(0, 3, 11, 16),
  40. DDR_CONFIG(0, 3, 12, 15), /* 0xa */
  41. /* List for DDR4 only (pinout order > chip, bank, row, column) */
  42. DDR_CONFIG(1, 3, 10, 14),
  43. DDR_CONFIG(1, 4, 10, 14),
  44. DDR_CONFIG(1, 3, 10, 15),
  45. DDR_CONFIG(1, 4, 10, 15),
  46. DDR_CONFIG(1, 3, 10, 16),
  47. DDR_CONFIG(1, 4, 10, 16),
  48. DDR_CONFIG(1, 3, 10, 17),
  49. DDR_CONFIG(1, 4, 10, 17),
  50. };
  51. int match_ddr_conf(u32 ddr_conf)
  52. {
  53. int i;
  54. for (i = 0; i < ARRAY_SIZE(ddr_config); i++) {
  55. if (ddr_conf == ddr_config[i])
  56. return i;
  57. }
  58. return 0;
  59. }
  60. /**
  61. * sdram_mmr_init_full() - Function to initialize SDRAM MMR
  62. *
  63. * Initialize the SDRAM MMR.
  64. */
  65. int sdram_mmr_init_full(struct udevice *dev)
  66. {
  67. struct altera_sdram_plat *plat = dev_get_plat(dev);
  68. struct altera_sdram_priv *priv = dev_get_priv(dev);
  69. u32 update_value, io48_value, ddrioctl;
  70. u32 i;
  71. int ret;
  72. phys_size_t hw_size;
  73. struct bd_info bd = {0};
  74. /* Enable access to DDR from CPU master */
  75. clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_DDRREG),
  76. CCU_ADBASE_DI_MASK);
  77. clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE0),
  78. CCU_ADBASE_DI_MASK);
  79. clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1A),
  80. CCU_ADBASE_DI_MASK);
  81. clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1B),
  82. CCU_ADBASE_DI_MASK);
  83. clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1C),
  84. CCU_ADBASE_DI_MASK);
  85. clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1D),
  86. CCU_ADBASE_DI_MASK);
  87. clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1E),
  88. CCU_ADBASE_DI_MASK);
  89. /* Enable access to DDR from IO master */
  90. clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE0),
  91. CCU_ADBASE_DI_MASK);
  92. clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1A),
  93. CCU_ADBASE_DI_MASK);
  94. clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1B),
  95. CCU_ADBASE_DI_MASK);
  96. clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1C),
  97. CCU_ADBASE_DI_MASK);
  98. clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1D),
  99. CCU_ADBASE_DI_MASK);
  100. clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1E),
  101. CCU_ADBASE_DI_MASK);
  102. /* Enable access to DDR from TCU */
  103. clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE0),
  104. CCU_ADBASE_DI_MASK);
  105. clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1A),
  106. CCU_ADBASE_DI_MASK);
  107. clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1B),
  108. CCU_ADBASE_DI_MASK);
  109. clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1C),
  110. CCU_ADBASE_DI_MASK);
  111. clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1D),
  112. CCU_ADBASE_DI_MASK);
  113. clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1E),
  114. CCU_ADBASE_DI_MASK);
  115. /* this enables nonsecure access to DDR */
  116. /* mpuregion0addr_limit */
  117. FW_MPU_DDR_SCR_WRITEL(0xFFFF0000, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT);
  118. FW_MPU_DDR_SCR_WRITEL(0x1F, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT);
  119. /* nonmpuregion0addr_limit */
  120. FW_MPU_DDR_SCR_WRITEL(0xFFFF0000,
  121. FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT);
  122. FW_MPU_DDR_SCR_WRITEL(0x1F, FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT);
  123. /* Enable mpuregion0enable and nonmpuregion0enable */
  124. FW_MPU_DDR_SCR_WRITEL(MPUREGION0_ENABLE | NONMPUREGION0_ENABLE,
  125. FW_MPU_DDR_SCR_EN_SET);
  126. /* Ensure HMC clock is running */
  127. if (poll_hmc_clock_status()) {
  128. puts("DDR: Error as HMC clock not running\n");
  129. return -1;
  130. }
  131. /* Try 3 times to do a calibration */
  132. for (i = 0; i < 3; i++) {
  133. ret = wait_for_bit_le32((const void *)(plat->hmc +
  134. DDRCALSTAT),
  135. DDR_HMC_DDRCALSTAT_CAL_MSK, true, 1000,
  136. false);
  137. if (!ret)
  138. break;
  139. emif_reset(plat);
  140. }
  141. if (ret) {
  142. puts("DDR: Error as SDRAM calibration failed\n");
  143. return -1;
  144. }
  145. debug("DDR: Calibration success\n");
  146. u32 ctrlcfg0 = hmc_readl(plat, CTRLCFG0);
  147. u32 ctrlcfg1 = hmc_readl(plat, CTRLCFG1);
  148. u32 dramaddrw = hmc_readl(plat, DRAMADDRW);
  149. u32 dramtim0 = hmc_readl(plat, DRAMTIMING0);
  150. u32 caltim0 = hmc_readl(plat, CALTIMING0);
  151. u32 caltim1 = hmc_readl(plat, CALTIMING1);
  152. u32 caltim2 = hmc_readl(plat, CALTIMING2);
  153. u32 caltim3 = hmc_readl(plat, CALTIMING3);
  154. u32 caltim4 = hmc_readl(plat, CALTIMING4);
  155. u32 caltim9 = hmc_readl(plat, CALTIMING9);
  156. /*
  157. * Configure the DDR IO size [0xFFCFB008]
  158. * niosreserve0: Used to indicate DDR width &
  159. * bit[7:0] = Number of data bits (bit[6:5] 0x01=32bit, 0x10=64bit)
  160. * bit[8] = 1 if user-mode OCT is present
  161. * bit[9] = 1 if warm reset compiled into EMIF Cal Code
  162. * bit[10] = 1 if warm reset is on during generation in EMIF Cal
  163. * niosreserve1: IP ADCDS version encoded as 16 bit value
  164. * bit[2:0] = Variant (0=not special,1=FAE beta, 2=Customer beta,
  165. * 3=EAP, 4-6 are reserved)
  166. * bit[5:3] = Service Pack # (e.g. 1)
  167. * bit[9:6] = Minor Release #
  168. * bit[14:10] = Major Release #
  169. */
  170. update_value = hmc_readl(plat, NIOSRESERVED0);
  171. hmc_ecc_writel(plat, ((update_value & 0xFF) >> 5), DDRIOCTRL);
  172. ddrioctl = hmc_ecc_readl(plat, DDRIOCTRL);
  173. /* enable HPS interface to HMC */
  174. hmc_ecc_writel(plat, DDR_HMC_HPSINTFCSEL_ENABLE_MASK, HPSINTFCSEL);
  175. /* Set the DDR Configuration */
  176. io48_value = DDR_CONFIG(CTRLCFG1_CFG_ADDR_ORDER(ctrlcfg1),
  177. (DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) +
  178. DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw)),
  179. DRAMADDRW_CFG_COL_ADDR_WIDTH(dramaddrw),
  180. DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw));
  181. update_value = match_ddr_conf(io48_value);
  182. if (update_value)
  183. ddr_sch_writel(plat, update_value, DDR_SCH_DDRCONF);
  184. /* Configure HMC dramaddrw */
  185. hmc_ecc_writel(plat, hmc_readl(plat, DRAMADDRW), DRAMADDRWIDTH);
  186. /*
  187. * Configure DDR timing
  188. * RDTOMISS = tRTP + tRP + tRCD - BL/2
  189. * WRTOMISS = WL + tWR + tRP + tRCD and
  190. * WL = RL + BL/2 + 2 - rd-to-wr ; tWR = 15ns so...
  191. * First part of equation is in memory clock units so divide by 2
  192. * for HMC clock units. 1066MHz is close to 1ns so use 15 directly.
  193. * WRTOMISS = ((RL + BL/2 + 2 + tWR) >> 1)- rd-to-wr + tRP + tRCD
  194. */
  195. u32 burst_len = CTRLCFG0_CFG_CTRL_BURST_LEN(ctrlcfg0);
  196. update_value = CALTIMING2_CFG_RD_TO_WR_PCH(caltim2) +
  197. CALTIMING4_CFG_PCH_TO_VALID(caltim4) +
  198. CALTIMING0_CFG_ACT_TO_RDWR(caltim0) -
  199. (burst_len >> 2);
  200. io48_value = (((DRAMTIMING0_CFG_TCL(dramtim0) + 2 + DDR_TWR +
  201. (burst_len >> 1)) >> 1) -
  202. /* Up to here was in memory cycles so divide by 2 */
  203. CALTIMING1_CFG_RD_TO_WR(caltim1) +
  204. CALTIMING0_CFG_ACT_TO_RDWR(caltim0) +
  205. CALTIMING4_CFG_PCH_TO_VALID(caltim4));
  206. ddr_sch_writel(plat, ((CALTIMING0_CFG_ACT_TO_ACT(caltim0) <<
  207. DDR_SCH_DDRTIMING_ACTTOACT_OFF) |
  208. (update_value << DDR_SCH_DDRTIMING_RDTOMISS_OFF) |
  209. (io48_value << DDR_SCH_DDRTIMING_WRTOMISS_OFF) |
  210. ((burst_len >> 2) << DDR_SCH_DDRTIMING_BURSTLEN_OFF) |
  211. (CALTIMING1_CFG_RD_TO_WR(caltim1) <<
  212. DDR_SCH_DDRTIMING_RDTOWR_OFF) |
  213. (CALTIMING3_CFG_WR_TO_RD(caltim3) <<
  214. DDR_SCH_DDRTIMING_WRTORD_OFF) |
  215. (((ddrioctl == 1) ? 1 : 0) <<
  216. DDR_SCH_DDRTIMING_BWRATIO_OFF)),
  217. DDR_SCH_DDRTIMING);
  218. /* Configure DDR mode [precharge = 0] */
  219. ddr_sch_writel(plat, ((ddrioctl ? 0 : 1) <<
  220. DDR_SCH_DDRMOD_BWRATIOEXTENDED_OFF),
  221. DDR_SCH_DDRMODE);
  222. /* Configure the read latency */
  223. ddr_sch_writel(plat, (DRAMTIMING0_CFG_TCL(dramtim0) >> 1) +
  224. DDR_READ_LATENCY_DELAY,
  225. DDR_SCH_READ_LATENCY);
  226. /*
  227. * Configuring timing values concerning activate commands
  228. * [FAWBANK alway 1 because always 4 bank DDR]
  229. */
  230. ddr_sch_writel(plat, ((CALTIMING0_CFG_ACT_TO_ACT_DB(caltim0) <<
  231. DDR_SCH_ACTIVATE_RRD_OFF) |
  232. (CALTIMING9_CFG_4_ACT_TO_ACT(caltim9) <<
  233. DDR_SCH_ACTIVATE_FAW_OFF) |
  234. (DDR_ACTIVATE_FAWBANK <<
  235. DDR_SCH_ACTIVATE_FAWBANK_OFF)),
  236. DDR_SCH_ACTIVATE);
  237. /*
  238. * Configuring timing values concerning device to device data bus
  239. * ownership change
  240. */
  241. ddr_sch_writel(plat, ((CALTIMING1_CFG_RD_TO_RD_DC(caltim1) <<
  242. DDR_SCH_DEVTODEV_BUSRDTORD_OFF) |
  243. (CALTIMING1_CFG_RD_TO_WR_DC(caltim1) <<
  244. DDR_SCH_DEVTODEV_BUSRDTOWR_OFF) |
  245. (CALTIMING3_CFG_WR_TO_RD_DC(caltim3) <<
  246. DDR_SCH_DEVTODEV_BUSWRTORD_OFF)),
  247. DDR_SCH_DEVTODEV);
  248. /* assigning the SDRAM size */
  249. unsigned long long size = sdram_calculate_size(plat);
  250. /* If the size is invalid, use default Config size */
  251. if (size <= 0)
  252. hw_size = PHYS_SDRAM_1_SIZE;
  253. else
  254. hw_size = size;
  255. /* Get bank configuration from devicetree */
  256. ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL,
  257. (phys_size_t *)&gd->ram_size, &bd);
  258. if (ret) {
  259. puts("DDR: Failed to decode memory node\n");
  260. return -1;
  261. }
  262. if (gd->ram_size != hw_size)
  263. printf("DDR: Warning: DRAM size from device tree mismatch with hardware.\n");
  264. printf("DDR: %lld MiB\n", gd->ram_size >> 20);
  265. /* Enable or disable the SDRAM ECC */
  266. if (CTRLCFG1_CFG_CTRL_EN_ECC(ctrlcfg1)) {
  267. setbits_le32(plat->hmc + ECCCTRL1,
  268. (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
  269. DDR_HMC_ECCCTL_CNT_RST_SET_MSK |
  270. DDR_HMC_ECCCTL_ECC_EN_SET_MSK));
  271. clrbits_le32(plat->hmc + ECCCTRL1,
  272. (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
  273. DDR_HMC_ECCCTL_CNT_RST_SET_MSK));
  274. setbits_le32(plat->hmc + ECCCTRL2,
  275. (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK |
  276. DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
  277. hmc_ecc_writel(plat, DDR_HMC_ERRINTEN_INTMASK, ERRINTENS);
  278. /* Initialize memory content if not from warm reset */
  279. if (!cpu_has_been_warmreset())
  280. sdram_init_ecc_bits(&bd);
  281. } else {
  282. clrbits_le32(plat->hmc + ECCCTRL1,
  283. (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
  284. DDR_HMC_ECCCTL_CNT_RST_SET_MSK |
  285. DDR_HMC_ECCCTL_ECC_EN_SET_MSK));
  286. clrbits_le32(plat->hmc + ECCCTRL2,
  287. (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK |
  288. DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
  289. }
  290. /* Enable non-secure reads/writes to HMC Adapter for SDRAM ECC */
  291. writel(FW_HMC_ADAPTOR_MPU_MASK, FW_HMC_ADAPTOR_REG_ADDR);
  292. sdram_size_check(&bd);
  293. priv->info.base = bd.bi_dram[0].start;
  294. priv->info.size = gd->ram_size;
  295. debug("DDR: HMC init success\n");
  296. return 0;
  297. }