sdram_agilex.c 4.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2019 Intel Corporation <www.intel.com>
  4. *
  5. */
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <errno.h>
  9. #include <div64.h>
  10. #include <fdtdec.h>
  11. #include <hang.h>
  12. #include <log.h>
  13. #include <ram.h>
  14. #include <reset.h>
  15. #include <asm/global_data.h>
  16. #include "sdram_soc64.h"
  17. #include <wait_bit.h>
  18. #include <asm/arch/firewall.h>
  19. #include <asm/arch/reset_manager.h>
  20. #include <asm/arch/system_manager.h>
  21. #include <asm/io.h>
  22. #include <linux/sizes.h>
  23. DECLARE_GLOBAL_DATA_PTR;
  24. int sdram_mmr_init_full(struct udevice *dev)
  25. {
  26. struct altera_sdram_plat *plat = dev_get_plat(dev);
  27. struct altera_sdram_priv *priv = dev_get_priv(dev);
  28. u32 i;
  29. int ret;
  30. phys_size_t hw_size;
  31. struct bd_info bd = {0};
  32. /* Ensure HMC clock is running */
  33. if (poll_hmc_clock_status()) {
  34. debug("DDR: Error as HMC clock was not running\n");
  35. return -EPERM;
  36. }
  37. /* Trying 3 times to do a calibration */
  38. for (i = 0; i < 3; i++) {
  39. ret = wait_for_bit_le32((const void *)(plat->hmc +
  40. DDRCALSTAT),
  41. DDR_HMC_DDRCALSTAT_CAL_MSK, true, 1000,
  42. false);
  43. if (!ret)
  44. break;
  45. emif_reset(plat);
  46. }
  47. if (ret) {
  48. puts("DDR: Error as SDRAM calibration failed\n");
  49. return -EPERM;
  50. }
  51. debug("DDR: Calibration success\n");
  52. /*
  53. * Configure the DDR IO size
  54. * niosreserve0: Used to indicate DDR width &
  55. * bit[7:0] = Number of data bits (bit[6:5] 0x01=32bit, 0x10=64bit)
  56. * bit[8] = 1 if user-mode OCT is present
  57. * bit[9] = 1 if warm reset compiled into EMIF Cal Code
  58. * bit[10] = 1 if warm reset is on during generation in EMIF Cal
  59. * niosreserve1: IP ADCDS version encoded as 16 bit value
  60. * bit[2:0] = Variant (0=not special,1=FAE beta, 2=Customer beta,
  61. * 3=EAP, 4-6 are reserved)
  62. * bit[5:3] = Service Pack # (e.g. 1)
  63. * bit[9:6] = Minor Release #
  64. * bit[14:10] = Major Release #
  65. */
  66. /* Configure DDR IO size x16, x32 and x64 mode */
  67. u32 update_value;
  68. update_value = hmc_readl(plat, NIOSRESERVED0);
  69. update_value = (update_value & 0xFF) >> 5;
  70. /* Configure DDR data rate 0-HAlf-rate 1-Quarter-rate */
  71. update_value |= (hmc_readl(plat, CTRLCFG3) & 0x4);
  72. hmc_ecc_writel(plat, update_value, DDRIOCTRL);
  73. /* Copy values MMR IOHMC dramaddrw to HMC adp DRAMADDRWIDTH */
  74. hmc_ecc_writel(plat, hmc_readl(plat, DRAMADDRW), DRAMADDRWIDTH);
  75. /* assigning the SDRAM size */
  76. phys_size_t size = sdram_calculate_size(plat);
  77. if (size <= 0)
  78. hw_size = PHYS_SDRAM_1_SIZE;
  79. else
  80. hw_size = size;
  81. /* Get bank configuration from devicetree */
  82. ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL,
  83. (phys_size_t *)&gd->ram_size, &bd);
  84. if (ret) {
  85. puts("DDR: Failed to decode memory node\n");
  86. return -ENXIO;
  87. }
  88. if (gd->ram_size != hw_size) {
  89. printf("DDR: Warning: DRAM size from device tree (%lld MiB)\n",
  90. gd->ram_size >> 20);
  91. printf(" mismatch with hardware (%lld MiB).\n",
  92. hw_size >> 20);
  93. }
  94. if (gd->ram_size > hw_size) {
  95. printf("DDR: Error: DRAM size from device tree is greater\n");
  96. printf(" than hardware size.\n");
  97. hang();
  98. }
  99. printf("DDR: %lld MiB\n", gd->ram_size >> 20);
  100. /* This enables nonsecure access to DDR */
  101. /* mpuregion0addr_limit */
  102. FW_MPU_DDR_SCR_WRITEL(gd->ram_size - 1,
  103. FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT);
  104. FW_MPU_DDR_SCR_WRITEL(0x1F, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT);
  105. /* nonmpuregion0addr_limit */
  106. FW_MPU_DDR_SCR_WRITEL(gd->ram_size - 1,
  107. FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT);
  108. /* Enable mpuregion0enable and nonmpuregion0enable */
  109. FW_MPU_DDR_SCR_WRITEL(MPUREGION0_ENABLE | NONMPUREGION0_ENABLE,
  110. FW_MPU_DDR_SCR_EN_SET);
  111. u32 ctrlcfg1 = hmc_readl(plat, CTRLCFG1);
  112. /* Enable or disable the DDR ECC */
  113. if (CTRLCFG1_CFG_CTRL_EN_ECC(ctrlcfg1)) {
  114. setbits_le32(plat->hmc + ECCCTRL1,
  115. (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
  116. DDR_HMC_ECCCTL_CNT_RST_SET_MSK |
  117. DDR_HMC_ECCCTL_ECC_EN_SET_MSK));
  118. clrbits_le32(plat->hmc + ECCCTRL1,
  119. (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
  120. DDR_HMC_ECCCTL_CNT_RST_SET_MSK));
  121. setbits_le32(plat->hmc + ECCCTRL2,
  122. (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK |
  123. DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
  124. setbits_le32(plat->hmc + ERRINTEN,
  125. DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK);
  126. if (!cpu_has_been_warmreset())
  127. sdram_init_ecc_bits(&bd);
  128. } else {
  129. clrbits_le32(plat->hmc + ECCCTRL1,
  130. (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
  131. DDR_HMC_ECCCTL_CNT_RST_SET_MSK |
  132. DDR_HMC_ECCCTL_ECC_EN_SET_MSK));
  133. clrbits_le32(plat->hmc + ECCCTRL2,
  134. (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK |
  135. DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
  136. }
  137. /* Enable non-secure reads/writes to HMC Adapter for SDRAM ECC */
  138. writel(FW_HMC_ADAPTOR_MPU_MASK, FW_HMC_ADAPTOR_REG_ADDR);
  139. sdram_size_check(&bd);
  140. priv->info.base = bd.bi_dram[0].start;
  141. priv->info.size = gd->ram_size;
  142. debug("DDR: HMC init success\n");
  143. return 0;
  144. }