jr.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2008-2014 Freescale Semiconductor, Inc.
  4. * Copyright 2018 NXP
  5. *
  6. * Based on CAAM driver in drivers/crypto/caam in Linux
  7. */
  8. #include <common.h>
  9. #include <cpu_func.h>
  10. #include <linux/kernel.h>
  11. #include <log.h>
  12. #include <malloc.h>
  13. #include "fsl_sec.h"
  14. #include "jr.h"
  15. #include "jobdesc.h"
  16. #include "desc_constr.h"
  17. #include <time.h>
  18. #include <asm/cache.h>
  19. #ifdef CONFIG_FSL_CORENET
  20. #include <asm/cache.h>
  21. #include <asm/fsl_pamu.h>
  22. #endif
  23. #include <dm/lists.h>
  24. #include <linux/delay.h>
  25. #define CIRC_CNT(head, tail, size) (((head) - (tail)) & (size - 1))
  26. #define CIRC_SPACE(head, tail, size) CIRC_CNT((tail), (head) + 1, (size))
  27. uint32_t sec_offset[CONFIG_SYS_FSL_MAX_NUM_OF_SEC] = {
  28. 0,
  29. #if defined(CONFIG_ARCH_C29X)
  30. CONFIG_SYS_FSL_SEC_IDX_OFFSET,
  31. 2 * CONFIG_SYS_FSL_SEC_IDX_OFFSET
  32. #endif
  33. };
  34. #define SEC_ADDR(idx) \
  35. (ulong)((CONFIG_SYS_FSL_SEC_ADDR + sec_offset[idx]))
  36. #define SEC_JR0_ADDR(idx) \
  37. (ulong)(SEC_ADDR(idx) + \
  38. (CONFIG_SYS_FSL_JR0_OFFSET - CONFIG_SYS_FSL_SEC_OFFSET))
  39. struct jobring jr0[CONFIG_SYS_FSL_MAX_NUM_OF_SEC];
  40. static inline void start_jr0(uint8_t sec_idx)
  41. {
  42. ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
  43. u32 ctpr_ms = sec_in32(&sec->ctpr_ms);
  44. u32 scfgr = sec_in32(&sec->scfgr);
  45. if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_INCL) {
  46. /* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or
  47. * VIRT_EN_INCL = 1 & VIRT_EN_POR = 0 & SEC_SCFGR_VIRT_EN = 1
  48. */
  49. if ((ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR) ||
  50. (scfgr & SEC_SCFGR_VIRT_EN))
  51. sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
  52. } else {
  53. /* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */
  54. if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR)
  55. sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
  56. }
  57. }
  58. static inline void jr_reset_liodn(uint8_t sec_idx)
  59. {
  60. ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
  61. sec_out32(&sec->jrliodnr[0].ls, 0);
  62. }
  63. static inline void jr_disable_irq(uint8_t sec_idx)
  64. {
  65. struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
  66. uint32_t jrcfg = sec_in32(&regs->jrcfg1);
  67. jrcfg = jrcfg | JR_INTMASK;
  68. sec_out32(&regs->jrcfg1, jrcfg);
  69. }
  70. static void jr_initregs(uint8_t sec_idx)
  71. {
  72. struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
  73. struct jobring *jr = &jr0[sec_idx];
  74. caam_dma_addr_t ip_base = virt_to_phys((void *)jr->input_ring);
  75. caam_dma_addr_t op_base = virt_to_phys((void *)jr->output_ring);
  76. #ifdef CONFIG_CAAM_64BIT
  77. sec_out32(&regs->irba_h, ip_base >> 32);
  78. #else
  79. sec_out32(&regs->irba_h, 0x0);
  80. #endif
  81. sec_out32(&regs->irba_l, (uint32_t)ip_base);
  82. #ifdef CONFIG_CAAM_64BIT
  83. sec_out32(&regs->orba_h, op_base >> 32);
  84. #else
  85. sec_out32(&regs->orba_h, 0x0);
  86. #endif
  87. sec_out32(&regs->orba_l, (uint32_t)op_base);
  88. sec_out32(&regs->ors, JR_SIZE);
  89. sec_out32(&regs->irs, JR_SIZE);
  90. if (!jr->irq)
  91. jr_disable_irq(sec_idx);
  92. }
  93. static int jr_init(uint8_t sec_idx)
  94. {
  95. struct jobring *jr = &jr0[sec_idx];
  96. memset(jr, 0, sizeof(struct jobring));
  97. jr->jq_id = DEFAULT_JR_ID;
  98. jr->irq = DEFAULT_IRQ;
  99. #ifdef CONFIG_FSL_CORENET
  100. jr->liodn = DEFAULT_JR_LIODN;
  101. #endif
  102. jr->size = JR_SIZE;
  103. jr->input_ring = (caam_dma_addr_t *)memalign(ARCH_DMA_MINALIGN,
  104. JR_SIZE * sizeof(caam_dma_addr_t));
  105. if (!jr->input_ring)
  106. return -1;
  107. jr->op_size = roundup(JR_SIZE * sizeof(struct op_ring),
  108. ARCH_DMA_MINALIGN);
  109. jr->output_ring =
  110. (struct op_ring *)memalign(ARCH_DMA_MINALIGN, jr->op_size);
  111. if (!jr->output_ring)
  112. return -1;
  113. memset(jr->input_ring, 0, JR_SIZE * sizeof(caam_dma_addr_t));
  114. memset(jr->output_ring, 0, jr->op_size);
  115. start_jr0(sec_idx);
  116. jr_initregs(sec_idx);
  117. return 0;
  118. }
  119. static int jr_sw_cleanup(uint8_t sec_idx)
  120. {
  121. struct jobring *jr = &jr0[sec_idx];
  122. jr->head = 0;
  123. jr->tail = 0;
  124. jr->read_idx = 0;
  125. jr->write_idx = 0;
  126. memset(jr->info, 0, sizeof(jr->info));
  127. memset(jr->input_ring, 0, jr->size * sizeof(caam_dma_addr_t));
  128. memset(jr->output_ring, 0, jr->size * sizeof(struct op_ring));
  129. return 0;
  130. }
  131. static int jr_hw_reset(uint8_t sec_idx)
  132. {
  133. struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
  134. uint32_t timeout = 100000;
  135. uint32_t jrint, jrcr;
  136. sec_out32(&regs->jrcr, JRCR_RESET);
  137. do {
  138. jrint = sec_in32(&regs->jrint);
  139. } while (((jrint & JRINT_ERR_HALT_MASK) ==
  140. JRINT_ERR_HALT_INPROGRESS) && --timeout);
  141. jrint = sec_in32(&regs->jrint);
  142. if (((jrint & JRINT_ERR_HALT_MASK) !=
  143. JRINT_ERR_HALT_INPROGRESS) && timeout == 0)
  144. return -1;
  145. timeout = 100000;
  146. sec_out32(&regs->jrcr, JRCR_RESET);
  147. do {
  148. jrcr = sec_in32(&regs->jrcr);
  149. } while ((jrcr & JRCR_RESET) && --timeout);
  150. if (timeout == 0)
  151. return -1;
  152. return 0;
  153. }
  154. /* -1 --- error, can't enqueue -- no space available */
  155. static int jr_enqueue(uint32_t *desc_addr,
  156. void (*callback)(uint32_t status, void *arg),
  157. void *arg, uint8_t sec_idx)
  158. {
  159. struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
  160. struct jobring *jr = &jr0[sec_idx];
  161. int head = jr->head;
  162. uint32_t desc_word;
  163. int length = desc_len(desc_addr);
  164. int i;
  165. #ifdef CONFIG_CAAM_64BIT
  166. uint32_t *addr_hi, *addr_lo;
  167. #endif
  168. /* The descriptor must be submitted to SEC block as per endianness
  169. * of the SEC Block.
  170. * So, if the endianness of Core and SEC block is different, each word
  171. * of the descriptor will be byte-swapped.
  172. */
  173. for (i = 0; i < length; i++) {
  174. desc_word = desc_addr[i];
  175. sec_out32((uint32_t *)&desc_addr[i], desc_word);
  176. }
  177. caam_dma_addr_t desc_phys_addr = virt_to_phys(desc_addr);
  178. jr->info[head].desc_phys_addr = desc_phys_addr;
  179. jr->info[head].callback = (void *)callback;
  180. jr->info[head].arg = arg;
  181. jr->info[head].op_done = 0;
  182. unsigned long start = (unsigned long)&jr->info[head] &
  183. ~(ARCH_DMA_MINALIGN - 1);
  184. unsigned long end = ALIGN((unsigned long)&jr->info[head] +
  185. sizeof(struct jr_info), ARCH_DMA_MINALIGN);
  186. flush_dcache_range(start, end);
  187. #ifdef CONFIG_CAAM_64BIT
  188. /* Write the 64 bit Descriptor address on Input Ring.
  189. * The 32 bit hign and low part of the address will
  190. * depend on endianness of SEC block.
  191. */
  192. #ifdef CONFIG_SYS_FSL_SEC_LE
  193. addr_lo = (uint32_t *)(&jr->input_ring[head]);
  194. addr_hi = (uint32_t *)(&jr->input_ring[head]) + 1;
  195. #elif defined(CONFIG_SYS_FSL_SEC_BE)
  196. addr_hi = (uint32_t *)(&jr->input_ring[head]);
  197. addr_lo = (uint32_t *)(&jr->input_ring[head]) + 1;
  198. #endif /* ifdef CONFIG_SYS_FSL_SEC_LE */
  199. sec_out32(addr_hi, (uint32_t)(desc_phys_addr >> 32));
  200. sec_out32(addr_lo, (uint32_t)(desc_phys_addr));
  201. #else
  202. /* Write the 32 bit Descriptor address on Input Ring. */
  203. sec_out32(&jr->input_ring[head], desc_phys_addr);
  204. #endif /* ifdef CONFIG_CAAM_64BIT */
  205. start = (unsigned long)&jr->input_ring[head] & ~(ARCH_DMA_MINALIGN - 1);
  206. end = ALIGN((unsigned long)&jr->input_ring[head] +
  207. sizeof(caam_dma_addr_t), ARCH_DMA_MINALIGN);
  208. flush_dcache_range(start, end);
  209. jr->head = (head + 1) & (jr->size - 1);
  210. /* Invalidate output ring */
  211. start = (unsigned long)jr->output_ring &
  212. ~(ARCH_DMA_MINALIGN - 1);
  213. end = ALIGN((unsigned long)jr->output_ring + jr->op_size,
  214. ARCH_DMA_MINALIGN);
  215. invalidate_dcache_range(start, end);
  216. sec_out32(&regs->irja, 1);
  217. return 0;
  218. }
  219. static int jr_dequeue(int sec_idx)
  220. {
  221. struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
  222. struct jobring *jr = &jr0[sec_idx];
  223. int head = jr->head;
  224. int tail = jr->tail;
  225. int idx, i, found;
  226. void (*callback)(uint32_t status, void *arg);
  227. void *arg = NULL;
  228. #ifdef CONFIG_CAAM_64BIT
  229. uint32_t *addr_hi, *addr_lo;
  230. #else
  231. uint32_t *addr;
  232. #endif
  233. while (sec_in32(&regs->orsf) && CIRC_CNT(jr->head, jr->tail,
  234. jr->size)) {
  235. found = 0;
  236. caam_dma_addr_t op_desc;
  237. #ifdef CONFIG_CAAM_64BIT
  238. /* Read the 64 bit Descriptor address from Output Ring.
  239. * The 32 bit hign and low part of the address will
  240. * depend on endianness of SEC block.
  241. */
  242. #ifdef CONFIG_SYS_FSL_SEC_LE
  243. addr_lo = (uint32_t *)(&jr->output_ring[jr->tail].desc);
  244. addr_hi = (uint32_t *)(&jr->output_ring[jr->tail].desc) + 1;
  245. #elif defined(CONFIG_SYS_FSL_SEC_BE)
  246. addr_hi = (uint32_t *)(&jr->output_ring[jr->tail].desc);
  247. addr_lo = (uint32_t *)(&jr->output_ring[jr->tail].desc) + 1;
  248. #endif /* ifdef CONFIG_SYS_FSL_SEC_LE */
  249. op_desc = ((u64)sec_in32(addr_hi) << 32) |
  250. ((u64)sec_in32(addr_lo));
  251. #else
  252. /* Read the 32 bit Descriptor address from Output Ring. */
  253. addr = (uint32_t *)&jr->output_ring[jr->tail].desc;
  254. op_desc = sec_in32(addr);
  255. #endif /* ifdef CONFIG_CAAM_64BIT */
  256. uint32_t status = sec_in32(&jr->output_ring[jr->tail].status);
  257. for (i = 0; CIRC_CNT(head, tail + i, jr->size) >= 1; i++) {
  258. idx = (tail + i) & (jr->size - 1);
  259. if (op_desc == jr->info[idx].desc_phys_addr) {
  260. found = 1;
  261. break;
  262. }
  263. }
  264. /* Error condition if match not found */
  265. if (!found)
  266. return -1;
  267. jr->info[idx].op_done = 1;
  268. callback = (void *)jr->info[idx].callback;
  269. arg = jr->info[idx].arg;
  270. /* When the job on tail idx gets done, increment
  271. * tail till the point where job completed out of oredr has
  272. * been taken into account
  273. */
  274. if (idx == tail)
  275. do {
  276. tail = (tail + 1) & (jr->size - 1);
  277. } while (jr->info[tail].op_done);
  278. jr->tail = tail;
  279. jr->read_idx = (jr->read_idx + 1) & (jr->size - 1);
  280. sec_out32(&regs->orjr, 1);
  281. jr->info[idx].op_done = 0;
  282. callback(status, arg);
  283. }
  284. return 0;
  285. }
  286. static void desc_done(uint32_t status, void *arg)
  287. {
  288. struct result *x = arg;
  289. x->status = status;
  290. #ifndef CONFIG_SPL_BUILD
  291. caam_jr_strstatus(status);
  292. #endif
  293. x->done = 1;
  294. }
  295. static inline int run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx)
  296. {
  297. unsigned long long timeval = 0;
  298. unsigned long long timeout = CONFIG_USEC_DEQ_TIMEOUT;
  299. struct result op;
  300. int ret = 0;
  301. memset(&op, 0, sizeof(op));
  302. ret = jr_enqueue(desc, desc_done, &op, sec_idx);
  303. if (ret) {
  304. debug("Error in SEC enq\n");
  305. ret = JQ_ENQ_ERR;
  306. goto out;
  307. }
  308. while (op.done != 1) {
  309. udelay(1);
  310. timeval += 1;
  311. ret = jr_dequeue(sec_idx);
  312. if (ret) {
  313. debug("Error in SEC deq\n");
  314. ret = JQ_DEQ_ERR;
  315. goto out;
  316. }
  317. if (timeval > timeout) {
  318. debug("SEC Dequeue timed out\n");
  319. ret = JQ_DEQ_TO_ERR;
  320. goto out;
  321. }
  322. }
  323. if (op.status) {
  324. debug("Error %x\n", op.status);
  325. ret = op.status;
  326. }
  327. out:
  328. return ret;
  329. }
  330. int run_descriptor_jr(uint32_t *desc)
  331. {
  332. return run_descriptor_jr_idx(desc, 0);
  333. }
  334. static inline int jr_reset_sec(uint8_t sec_idx)
  335. {
  336. if (jr_hw_reset(sec_idx) < 0)
  337. return -1;
  338. /* Clean up the jobring structure maintained by software */
  339. jr_sw_cleanup(sec_idx);
  340. return 0;
  341. }
  342. int jr_reset(void)
  343. {
  344. return jr_reset_sec(0);
  345. }
  346. static inline int sec_reset_idx(uint8_t sec_idx)
  347. {
  348. ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
  349. uint32_t mcfgr = sec_in32(&sec->mcfgr);
  350. uint32_t timeout = 100000;
  351. mcfgr |= MCFGR_SWRST;
  352. sec_out32(&sec->mcfgr, mcfgr);
  353. mcfgr |= MCFGR_DMA_RST;
  354. sec_out32(&sec->mcfgr, mcfgr);
  355. do {
  356. mcfgr = sec_in32(&sec->mcfgr);
  357. } while ((mcfgr & MCFGR_DMA_RST) == MCFGR_DMA_RST && --timeout);
  358. if (timeout == 0)
  359. return -1;
  360. timeout = 100000;
  361. do {
  362. mcfgr = sec_in32(&sec->mcfgr);
  363. } while ((mcfgr & MCFGR_SWRST) == MCFGR_SWRST && --timeout);
  364. if (timeout == 0)
  365. return -1;
  366. return 0;
  367. }
  368. int sec_reset(void)
  369. {
  370. return sec_reset_idx(0);
  371. }
  372. #ifndef CONFIG_SPL_BUILD
  373. static int deinstantiate_rng(u8 sec_idx, int state_handle_mask)
  374. {
  375. u32 *desc;
  376. int sh_idx, ret = 0;
  377. int desc_size = ALIGN(sizeof(u32) * 2, ARCH_DMA_MINALIGN);
  378. desc = memalign(ARCH_DMA_MINALIGN, desc_size);
  379. if (!desc) {
  380. debug("cannot allocate RNG init descriptor memory\n");
  381. return -ENOMEM;
  382. }
  383. for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
  384. /*
  385. * If the corresponding bit is set, then it means the state
  386. * handle was initialized by us, and thus it needs to be
  387. * deinitialized as well
  388. */
  389. if (state_handle_mask & RDSTA_IF(sh_idx)) {
  390. /*
  391. * Create the descriptor for deinstantating this state
  392. * handle.
  393. */
  394. inline_cnstr_jobdesc_rng_deinstantiation(desc, sh_idx);
  395. flush_dcache_range((unsigned long)desc,
  396. (unsigned long)desc + desc_size);
  397. ret = run_descriptor_jr_idx(desc, sec_idx);
  398. if (ret) {
  399. printf("SEC%u: RNG4 SH%d deinstantiation failed with error 0x%x\n",
  400. sec_idx, sh_idx, ret);
  401. ret = -EIO;
  402. break;
  403. }
  404. printf("SEC%u: Deinstantiated RNG4 SH%d\n",
  405. sec_idx, sh_idx);
  406. }
  407. }
  408. free(desc);
  409. return ret;
  410. }
  411. static int instantiate_rng(u8 sec_idx, int gen_sk)
  412. {
  413. u32 *desc;
  414. u32 rdsta_val;
  415. int ret = 0, sh_idx, size;
  416. ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
  417. struct rng4tst __iomem *rng =
  418. (struct rng4tst __iomem *)&sec->rng;
  419. desc = memalign(ARCH_DMA_MINALIGN, sizeof(uint32_t) * 6);
  420. if (!desc) {
  421. printf("cannot allocate RNG init descriptor memory\n");
  422. return -1;
  423. }
  424. for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
  425. /*
  426. * If the corresponding bit is set, this state handle
  427. * was initialized by somebody else, so it's left alone.
  428. */
  429. rdsta_val = sec_in32(&rng->rdsta);
  430. if (rdsta_val & (RDSTA_IF(sh_idx))) {
  431. if (rdsta_val & RDSTA_PR(sh_idx))
  432. continue;
  433. printf("SEC%u: RNG4 SH%d was instantiated w/o prediction resistance. Tearing it down\n",
  434. sec_idx, sh_idx);
  435. ret = deinstantiate_rng(sec_idx, RDSTA_IF(sh_idx));
  436. if (ret)
  437. break;
  438. }
  439. inline_cnstr_jobdesc_rng_instantiation(desc, sh_idx, gen_sk);
  440. size = roundup(sizeof(uint32_t) * 6, ARCH_DMA_MINALIGN);
  441. flush_dcache_range((unsigned long)desc,
  442. (unsigned long)desc + size);
  443. ret = run_descriptor_jr_idx(desc, sec_idx);
  444. if (ret)
  445. printf("SEC%u: RNG4 SH%d instantiation failed with error 0x%x\n",
  446. sec_idx, sh_idx, ret);
  447. rdsta_val = sec_in32(&rng->rdsta);
  448. if (!(rdsta_val & RDSTA_IF(sh_idx))) {
  449. free(desc);
  450. return -1;
  451. }
  452. memset(desc, 0, sizeof(uint32_t) * 6);
  453. }
  454. free(desc);
  455. return ret;
  456. }
  457. static u8 get_rng_vid(uint8_t sec_idx)
  458. {
  459. ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
  460. u8 vid;
  461. if (caam_get_era() < 10) {
  462. vid = (sec_in32(&sec->chavid_ls) & SEC_CHAVID_RNG_LS_MASK)
  463. >> SEC_CHAVID_LS_RNG_SHIFT;
  464. } else {
  465. vid = (sec_in32(&sec->vreg.rng) & CHA_VER_VID_MASK)
  466. >> CHA_VER_VID_SHIFT;
  467. }
  468. return vid;
  469. }
  470. /*
  471. * By default, the TRNG runs for 200 clocks per sample;
  472. * 1200 clocks per sample generates better entropy.
  473. */
  474. static void kick_trng(int ent_delay, uint8_t sec_idx)
  475. {
  476. ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
  477. struct rng4tst __iomem *rng =
  478. (struct rng4tst __iomem *)&sec->rng;
  479. u32 val;
  480. /* put RNG4 into program mode */
  481. sec_setbits32(&rng->rtmctl, RTMCTL_PRGM);
  482. /* rtsdctl bits 0-15 contain "Entropy Delay, which defines the
  483. * length (in system clocks) of each Entropy sample taken
  484. * */
  485. val = sec_in32(&rng->rtsdctl);
  486. val = (val & ~RTSDCTL_ENT_DLY_MASK) |
  487. (ent_delay << RTSDCTL_ENT_DLY_SHIFT);
  488. sec_out32(&rng->rtsdctl, val);
  489. /* min. freq. count, equal to 1/4 of the entropy sample length */
  490. sec_out32(&rng->rtfreqmin, ent_delay >> 2);
  491. /* disable maximum frequency count */
  492. sec_out32(&rng->rtfreqmax, RTFRQMAX_DISABLE);
  493. /*
  494. * select raw sampling in both entropy shifter
  495. * and statistical checker
  496. */
  497. sec_setbits32(&rng->rtmctl, RTMCTL_SAMP_MODE_RAW_ES_SC);
  498. /* put RNG4 into run mode */
  499. sec_clrbits32(&rng->rtmctl, RTMCTL_PRGM);
  500. }
  501. static int rng_init(uint8_t sec_idx)
  502. {
  503. int ret, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN;
  504. ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
  505. struct rng4tst __iomem *rng =
  506. (struct rng4tst __iomem *)&sec->rng;
  507. u32 inst_handles;
  508. gen_sk = !(sec_in32(&rng->rdsta) & RDSTA_SKVN);
  509. do {
  510. inst_handles = sec_in32(&rng->rdsta) & RDSTA_MASK;
  511. /*
  512. * If either of the SH's were instantiated by somebody else
  513. * then it is assumed that the entropy
  514. * parameters are properly set and thus the function
  515. * setting these (kick_trng(...)) is skipped.
  516. * Also, if a handle was instantiated, do not change
  517. * the TRNG parameters.
  518. */
  519. if (!inst_handles) {
  520. kick_trng(ent_delay, sec_idx);
  521. ent_delay += 400;
  522. }
  523. /*
  524. * if instantiate_rng(...) fails, the loop will rerun
  525. * and the kick_trng(...) function will modfiy the
  526. * upper and lower limits of the entropy sampling
  527. * interval, leading to a sucessful initialization of
  528. * the RNG.
  529. */
  530. ret = instantiate_rng(sec_idx, gen_sk);
  531. } while ((ret == -1) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
  532. if (ret) {
  533. printf("SEC%u: Failed to instantiate RNG\n", sec_idx);
  534. return ret;
  535. }
  536. /* Enable RDB bit so that RNG works faster */
  537. sec_setbits32(&sec->scfgr, SEC_SCFGR_RDBENABLE);
  538. return ret;
  539. }
  540. #endif
  541. int sec_init_idx(uint8_t sec_idx)
  542. {
  543. ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
  544. uint32_t mcr = sec_in32(&sec->mcfgr);
  545. int ret = 0;
  546. #ifdef CONFIG_FSL_CORENET
  547. uint32_t liodnr;
  548. uint32_t liodn_ns;
  549. uint32_t liodn_s;
  550. #endif
  551. if (!(sec_idx < CONFIG_SYS_FSL_MAX_NUM_OF_SEC)) {
  552. printf("SEC%u: initialization failed\n", sec_idx);
  553. return -1;
  554. }
  555. /*
  556. * Modifying CAAM Read/Write Attributes
  557. * For LS2080A
  558. * For AXI Write - Cacheable, Write Back, Write allocate
  559. * For AXI Read - Cacheable, Read allocate
  560. * Only For LS2080a, to solve CAAM coherency issues
  561. */
  562. #ifdef CONFIG_ARCH_LS2080A
  563. mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0xb << MCFGR_AWCACHE_SHIFT);
  564. mcr = (mcr & ~MCFGR_ARCACHE_MASK) | (0x6 << MCFGR_ARCACHE_SHIFT);
  565. #else
  566. mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0x2 << MCFGR_AWCACHE_SHIFT);
  567. #endif
  568. #ifdef CONFIG_CAAM_64BIT
  569. mcr |= (1 << MCFGR_PS_SHIFT);
  570. #endif
  571. sec_out32(&sec->mcfgr, mcr);
  572. #ifdef CONFIG_FSL_CORENET
  573. #ifdef CONFIG_SPL_BUILD
  574. /*
  575. * For SPL Build, Set the Liodns in SEC JR0 for
  576. * creating PAMU entries corresponding to these.
  577. * For normal build, these are set in set_liodns().
  578. */
  579. liodn_ns = CONFIG_SPL_JR0_LIODN_NS & JRNSLIODN_MASK;
  580. liodn_s = CONFIG_SPL_JR0_LIODN_S & JRSLIODN_MASK;
  581. liodnr = sec_in32(&sec->jrliodnr[0].ls) &
  582. ~(JRNSLIODN_MASK | JRSLIODN_MASK);
  583. liodnr = liodnr |
  584. (liodn_ns << JRNSLIODN_SHIFT) |
  585. (liodn_s << JRSLIODN_SHIFT);
  586. sec_out32(&sec->jrliodnr[0].ls, liodnr);
  587. #else
  588. liodnr = sec_in32(&sec->jrliodnr[0].ls);
  589. liodn_ns = (liodnr & JRNSLIODN_MASK) >> JRNSLIODN_SHIFT;
  590. liodn_s = (liodnr & JRSLIODN_MASK) >> JRSLIODN_SHIFT;
  591. #endif
  592. #endif
  593. ret = jr_init(sec_idx);
  594. if (ret < 0) {
  595. printf("SEC%u: initialization failed\n", sec_idx);
  596. return -1;
  597. }
  598. #ifdef CONFIG_FSL_CORENET
  599. ret = sec_config_pamu_table(liodn_ns, liodn_s);
  600. if (ret < 0)
  601. return -1;
  602. pamu_enable();
  603. #endif
  604. #ifndef CONFIG_SPL_BUILD
  605. if (get_rng_vid(sec_idx) >= 4) {
  606. if (rng_init(sec_idx) < 0) {
  607. printf("SEC%u: RNG instantiation failed\n", sec_idx);
  608. return -1;
  609. }
  610. if (IS_ENABLED(CONFIG_DM_RNG)) {
  611. ret = device_bind_driver(NULL, "caam-rng", "caam-rng",
  612. NULL);
  613. if (ret)
  614. printf("Couldn't bind rng driver (%d)\n", ret);
  615. }
  616. printf("SEC%u: RNG instantiated\n", sec_idx);
  617. }
  618. #endif
  619. return ret;
  620. }
  621. int sec_init(void)
  622. {
  623. return sec_init_idx(0);
  624. }