ace_sha.h 9.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Header file for Advanced Crypto Engine - SFR definitions
  4. *
  5. * Copyright (c) 2012 Samsung Electronics
  6. */
  7. #ifndef __ACE_SHA_H
  8. #define __ACE_SHA_H
  9. struct exynos_ace_sfr {
  10. unsigned int fc_intstat; /* base + 0 */
  11. unsigned int fc_intenset;
  12. unsigned int fc_intenclr;
  13. unsigned int fc_intpend;
  14. unsigned int fc_fifostat;
  15. unsigned int fc_fifoctrl;
  16. unsigned int fc_global;
  17. unsigned int res1;
  18. unsigned int fc_brdmas;
  19. unsigned int fc_brdmal;
  20. unsigned int fc_brdmac;
  21. unsigned int res2;
  22. unsigned int fc_btdmas;
  23. unsigned int fc_btdmal;
  24. unsigned int fc_btdmac;
  25. unsigned int res3;
  26. unsigned int fc_hrdmas;
  27. unsigned int fc_hrdmal;
  28. unsigned int fc_hrdmac;
  29. unsigned int res4;
  30. unsigned int fc_pkdmas;
  31. unsigned int fc_pkdmal;
  32. unsigned int fc_pkdmac;
  33. unsigned int fc_pkdmao;
  34. unsigned char res5[0x1a0];
  35. unsigned int aes_control; /* base + 0x200 */
  36. unsigned int aes_status;
  37. unsigned char res6[0x8];
  38. unsigned int aes_in[4];
  39. unsigned int aes_out[4];
  40. unsigned int aes_iv[4];
  41. unsigned int aes_cnt[4];
  42. unsigned char res7[0x30];
  43. unsigned int aes_key[8];
  44. unsigned char res8[0x60];
  45. unsigned int tdes_control; /* base + 0x300 */
  46. unsigned int tdes_status;
  47. unsigned char res9[0x8];
  48. unsigned int tdes_key[6];
  49. unsigned int tdes_iv[2];
  50. unsigned int tdes_in[2];
  51. unsigned int tdes_out[2];
  52. unsigned char res10[0xc0];
  53. unsigned int hash_control; /* base + 0x400 */
  54. unsigned int hash_control2;
  55. unsigned int hash_fifo_mode;
  56. unsigned int hash_byteswap;
  57. unsigned int hash_status;
  58. unsigned char res11[0xc];
  59. unsigned int hash_msgsize_low;
  60. unsigned int hash_msgsize_high;
  61. unsigned int hash_prelen_low;
  62. unsigned int hash_prelen_high;
  63. unsigned int hash_in[16];
  64. unsigned int hash_key_in[16];
  65. unsigned int hash_iv[8];
  66. unsigned char res12[0x30];
  67. unsigned int hash_result[8];
  68. unsigned char res13[0x20];
  69. unsigned int hash_seed[5];
  70. unsigned char res14[12];
  71. unsigned int hash_prng[5];
  72. unsigned char res15[0x18c];
  73. unsigned int pka_sfr[5]; /* base + 0x700 */
  74. };
  75. /* ACE_FC_INT */
  76. #define ACE_FC_PKDMA (1 << 0)
  77. #define ACE_FC_HRDMA (1 << 1)
  78. #define ACE_FC_BTDMA (1 << 2)
  79. #define ACE_FC_BRDMA (1 << 3)
  80. #define ACE_FC_PRNG_ERROR (1 << 4)
  81. #define ACE_FC_MSG_DONE (1 << 5)
  82. #define ACE_FC_PRNG_DONE (1 << 6)
  83. #define ACE_FC_PARTIAL_DONE (1 << 7)
  84. /* ACE_FC_FIFOSTAT */
  85. #define ACE_FC_PKFIFO_EMPTY (1 << 0)
  86. #define ACE_FC_PKFIFO_FULL (1 << 1)
  87. #define ACE_FC_HRFIFO_EMPTY (1 << 2)
  88. #define ACE_FC_HRFIFO_FULL (1 << 3)
  89. #define ACE_FC_BTFIFO_EMPTY (1 << 4)
  90. #define ACE_FC_BTFIFO_FULL (1 << 5)
  91. #define ACE_FC_BRFIFO_EMPTY (1 << 6)
  92. #define ACE_FC_BRFIFO_FULL (1 << 7)
  93. /* ACE_FC_FIFOCTRL */
  94. #define ACE_FC_SELHASH_MASK (3 << 0)
  95. #define ACE_FC_SELHASH_EXOUT (0 << 0) /* independent source */
  96. #define ACE_FC_SELHASH_BCIN (1 << 0) /* blk cipher input */
  97. #define ACE_FC_SELHASH_BCOUT (2 << 0) /* blk cipher output */
  98. #define ACE_FC_SELBC_MASK (1 << 2)
  99. #define ACE_FC_SELBC_AES (0 << 2)
  100. #define ACE_FC_SELBC_DES (1 << 2)
  101. /* ACE_FC_GLOBAL */
  102. #define ACE_FC_SSS_RESET (1 << 0)
  103. #define ACE_FC_DMA_RESET (1 << 1)
  104. #define ACE_FC_AES_RESET (1 << 2)
  105. #define ACE_FC_DES_RESET (1 << 3)
  106. #define ACE_FC_HASH_RESET (1 << 4)
  107. #define ACE_FC_AXI_ENDIAN_MASK (3 << 6)
  108. #define ACE_FC_AXI_ENDIAN_LE (0 << 6)
  109. #define ACE_FC_AXI_ENDIAN_BIBE (1 << 6)
  110. #define ACE_FC_AXI_ENDIAN_WIBE (2 << 6)
  111. /* Feed control - BRDMA control */
  112. #define ACE_FC_BRDMACFLUSH_OFF (0 << 0)
  113. #define ACE_FC_BRDMACFLUSH_ON (1 << 0)
  114. #define ACE_FC_BRDMACSWAP_ON (1 << 1)
  115. #define ACE_FC_BRDMACARPROT_MASK (0x7 << 2)
  116. #define ACE_FC_BRDMACARPROT_OFS 2
  117. #define ACE_FC_BRDMACARCACHE_MASK (0xf << 5)
  118. #define ACE_FC_BRDMACARCACHE_OFS 5
  119. /* Feed control - BTDMA control */
  120. #define ACE_FC_BTDMACFLUSH_OFF (0 << 0)
  121. #define ACE_FC_BTDMACFLUSH_ON (1 << 0)
  122. #define ACE_FC_BTDMACSWAP_ON (1 << 1)
  123. #define ACE_FC_BTDMACAWPROT_MASK (0x7 << 2)
  124. #define ACE_FC_BTDMACAWPROT_OFS 2
  125. #define ACE_FC_BTDMACAWCACHE_MASK (0xf << 5)
  126. #define ACE_FC_BTDMACAWCACHE_OFS 5
  127. /* Feed control - HRDMA control */
  128. #define ACE_FC_HRDMACFLUSH_OFF (0 << 0)
  129. #define ACE_FC_HRDMACFLUSH_ON (1 << 0)
  130. #define ACE_FC_HRDMACSWAP_ON (1 << 1)
  131. #define ACE_FC_HRDMACARPROT_MASK (0x7 << 2)
  132. #define ACE_FC_HRDMACARPROT_OFS 2
  133. #define ACE_FC_HRDMACARCACHE_MASK (0xf << 5)
  134. #define ACE_FC_HRDMACARCACHE_OFS 5
  135. /* Feed control - PKDMA control */
  136. #define ACE_FC_PKDMACBYTESWAP_ON (1 << 3)
  137. #define ACE_FC_PKDMACDESEND_ON (1 << 2)
  138. #define ACE_FC_PKDMACTRANSMIT_ON (1 << 1)
  139. #define ACE_FC_PKDMACFLUSH_ON (1 << 0)
  140. /* Feed control - PKDMA offset */
  141. #define ACE_FC_SRAMOFFSET_MASK 0xfff
  142. /* AES control */
  143. #define ACE_AES_MODE_MASK (1 << 0)
  144. #define ACE_AES_MODE_ENC (0 << 0)
  145. #define ACE_AES_MODE_DEC (1 << 0)
  146. #define ACE_AES_OPERMODE_MASK (3 << 1)
  147. #define ACE_AES_OPERMODE_ECB (0 << 1)
  148. #define ACE_AES_OPERMODE_CBC (1 << 1)
  149. #define ACE_AES_OPERMODE_CTR (2 << 1)
  150. #define ACE_AES_FIFO_MASK (1 << 3)
  151. #define ACE_AES_FIFO_OFF (0 << 3) /* CPU mode */
  152. #define ACE_AES_FIFO_ON (1 << 3) /* FIFO mode */
  153. #define ACE_AES_KEYSIZE_MASK (3 << 4)
  154. #define ACE_AES_KEYSIZE_128 (0 << 4)
  155. #define ACE_AES_KEYSIZE_192 (1 << 4)
  156. #define ACE_AES_KEYSIZE_256 (2 << 4)
  157. #define ACE_AES_KEYCNGMODE_MASK (1 << 6)
  158. #define ACE_AES_KEYCNGMODE_OFF (0 << 6)
  159. #define ACE_AES_KEYCNGMODE_ON (1 << 6)
  160. #define ACE_AES_SWAP_MASK (0x1f << 7)
  161. #define ACE_AES_SWAPKEY_OFF (0 << 7)
  162. #define ACE_AES_SWAPKEY_ON (1 << 7)
  163. #define ACE_AES_SWAPCNT_OFF (0 << 8)
  164. #define ACE_AES_SWAPCNT_ON (1 << 8)
  165. #define ACE_AES_SWAPIV_OFF (0 << 9)
  166. #define ACE_AES_SWAPIV_ON (1 << 9)
  167. #define ACE_AES_SWAPDO_OFF (0 << 10)
  168. #define ACE_AES_SWAPDO_ON (1 << 10)
  169. #define ACE_AES_SWAPDI_OFF (0 << 11)
  170. #define ACE_AES_SWAPDI_ON (1 << 11)
  171. #define ACE_AES_COUNTERSIZE_MASK (3 << 12)
  172. #define ACE_AES_COUNTERSIZE_128 (0 << 12)
  173. #define ACE_AES_COUNTERSIZE_64 (1 << 12)
  174. #define ACE_AES_COUNTERSIZE_32 (2 << 12)
  175. #define ACE_AES_COUNTERSIZE_16 (3 << 12)
  176. /* AES status */
  177. #define ACE_AES_OUTRDY_MASK (1 << 0)
  178. #define ACE_AES_OUTRDY_OFF (0 << 0)
  179. #define ACE_AES_OUTRDY_ON (1 << 0)
  180. #define ACE_AES_INRDY_MASK (1 << 1)
  181. #define ACE_AES_INRDY_OFF (0 << 1)
  182. #define ACE_AES_INRDY_ON (1 << 1)
  183. #define ACE_AES_BUSY_MASK (1 << 2)
  184. #define ACE_AES_BUSY_OFF (0 << 2)
  185. #define ACE_AES_BUSY_ON (1 << 2)
  186. /* TDES control */
  187. #define ACE_TDES_MODE_MASK (1 << 0)
  188. #define ACE_TDES_MODE_ENC (0 << 0)
  189. #define ACE_TDES_MODE_DEC (1 << 0)
  190. #define ACE_TDES_OPERMODE_MASK (1 << 1)
  191. #define ACE_TDES_OPERMODE_ECB (0 << 1)
  192. #define ACE_TDES_OPERMODE_CBC (1 << 1)
  193. #define ACE_TDES_SEL_MASK (3 << 3)
  194. #define ACE_TDES_SEL_DES (0 << 3)
  195. #define ACE_TDES_SEL_TDESEDE (1 << 3) /* TDES EDE mode */
  196. #define ACE_TDES_SEL_TDESEEE (3 << 3) /* TDES EEE mode */
  197. #define ACE_TDES_FIFO_MASK (1 << 5)
  198. #define ACE_TDES_FIFO_OFF (0 << 5) /* CPU mode */
  199. #define ACE_TDES_FIFO_ON (1 << 5) /* FIFO mode */
  200. #define ACE_TDES_SWAP_MASK (0xf << 6)
  201. #define ACE_TDES_SWAPKEY_OFF (0 << 6)
  202. #define ACE_TDES_SWAPKEY_ON (1 << 6)
  203. #define ACE_TDES_SWAPIV_OFF (0 << 7)
  204. #define ACE_TDES_SWAPIV_ON (1 << 7)
  205. #define ACE_TDES_SWAPDO_OFF (0 << 8)
  206. #define ACE_TDES_SWAPDO_ON (1 << 8)
  207. #define ACE_TDES_SWAPDI_OFF (0 << 9)
  208. #define ACE_TDES_SWAPDI_ON (1 << 9)
  209. /* TDES status */
  210. #define ACE_TDES_OUTRDY_MASK (1 << 0)
  211. #define ACE_TDES_OUTRDY_OFF (0 << 0)
  212. #define ACE_TDES_OUTRDY_ON (1 << 0)
  213. #define ACE_TDES_INRDY_MASK (1 << 1)
  214. #define ACE_TDES_INRDY_OFF (0 << 1)
  215. #define ACE_TDES_INRDY_ON (1 << 1)
  216. #define ACE_TDES_BUSY_MASK (1 << 2)
  217. #define ACE_TDES_BUSY_OFF (0 << 2)
  218. #define ACE_TDES_BUSY_ON (1 << 2)
  219. /* Hash control */
  220. #define ACE_HASH_ENGSEL_MASK (0xf << 0)
  221. #define ACE_HASH_ENGSEL_SHA1HASH (0x0 << 0)
  222. #define ACE_HASH_ENGSEL_SHA1HMAC (0x1 << 0)
  223. #define ACE_HASH_ENGSEL_SHA1HMACIN (0x1 << 0)
  224. #define ACE_HASH_ENGSEL_SHA1HMACOUT (0x9 << 0)
  225. #define ACE_HASH_ENGSEL_MD5HASH (0x2 << 0)
  226. #define ACE_HASH_ENGSEL_MD5HMAC (0x3 << 0)
  227. #define ACE_HASH_ENGSEL_MD5HMACIN (0x3 << 0)
  228. #define ACE_HASH_ENGSEL_MD5HMACOUT (0xb << 0)
  229. #define ACE_HASH_ENGSEL_SHA256HASH (0x4 << 0)
  230. #define ACE_HASH_ENGSEL_SHA256HMAC (0x5 << 0)
  231. #define ACE_HASH_ENGSEL_PRNG (0x8 << 0)
  232. #define ACE_HASH_STARTBIT_ON (1 << 4)
  233. #define ACE_HASH_USERIV_EN (1 << 5)
  234. #define ACE_HASH_PAUSE_ON (1 << 0)
  235. /* Hash control - FIFO mode */
  236. #define ACE_HASH_FIFO_MASK (1 << 0)
  237. #define ACE_HASH_FIFO_OFF (0 << 0)
  238. #define ACE_HASH_FIFO_ON (1 << 0)
  239. /* Hash control - byte swap */
  240. #define ACE_HASH_SWAP_MASK (0xf << 0)
  241. #define ACE_HASH_SWAPKEY_OFF (0 << 0)
  242. #define ACE_HASH_SWAPKEY_ON (1 << 0)
  243. #define ACE_HASH_SWAPIV_OFF (0 << 1)
  244. #define ACE_HASH_SWAPIV_ON (1 << 1)
  245. #define ACE_HASH_SWAPDO_OFF (0 << 2)
  246. #define ACE_HASH_SWAPDO_ON (1 << 2)
  247. #define ACE_HASH_SWAPDI_OFF (0 << 3)
  248. #define ACE_HASH_SWAPDI_ON (1 << 3)
  249. /* Hash status */
  250. #define ACE_HASH_BUFRDY_MASK (1 << 0)
  251. #define ACE_HASH_BUFRDY_OFF (0 << 0)
  252. #define ACE_HASH_BUFRDY_ON (1 << 0)
  253. #define ACE_HASH_SEEDSETTING_MASK (1 << 1)
  254. #define ACE_HASH_SEEDSETTING_OFF (0 << 1)
  255. #define ACE_HASH_SEEDSETTING_ON (1 << 1)
  256. #define ACE_HASH_PRNGBUSY_MASK (1 << 2)
  257. #define ACE_HASH_PRNGBUSY_OFF (0 << 2)
  258. #define ACE_HASH_PRNGBUSY_ON (1 << 2)
  259. #define ACE_HASH_PARTIALDONE_MASK (1 << 4)
  260. #define ACE_HASH_PARTIALDONE_OFF (0 << 4)
  261. #define ACE_HASH_PARTIALDONE_ON (1 << 4)
  262. #define ACE_HASH_PRNGDONE_MASK (1 << 5)
  263. #define ACE_HASH_PRNGDONE_OFF (0 << 5)
  264. #define ACE_HASH_PRNGDONE_ON (1 << 5)
  265. #define ACE_HASH_MSGDONE_MASK (1 << 6)
  266. #define ACE_HASH_MSGDONE_OFF (0 << 6)
  267. #define ACE_HASH_MSGDONE_ON (1 << 6)
  268. #define ACE_HASH_PRNGERROR_MASK (1 << 7)
  269. #define ACE_HASH_PRNGERROR_OFF (0 << 7)
  270. #define ACE_HASH_PRNGERROR_ON (1 << 7)
  271. #define ACE_HASH_PRNG_REG_NUM 5
  272. #define ACE_SHA_TYPE_SHA1 1
  273. #define ACE_SHA_TYPE_SHA256 2
  274. /**
  275. * Computes hash value of input pbuf using ACE
  276. *
  277. * @param in_addr A pointer to the input buffer
  278. * @param bufleni Byte length of input buffer
  279. * @param out_addr A pointer to the output buffer. When complete
  280. * 32 bytes are copied to pout[0]...pout[31]. Thus, a user
  281. * should allocate at least 32 bytes at pOut in advance.
  282. * @param hash_type SHA1 or SHA256
  283. *
  284. * @return 0 on Success, -1 on Failure (Timeout)
  285. */
  286. int ace_sha_hash_digest(const uchar * in_addr, uint buflen,
  287. uchar * out_addr, uint hash_type);
  288. #endif