riscv_cpu.c 3.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
  4. * Copyright (C) 2020, Sean Anderson <seanga2@gmail.com>
  5. */
  6. #include <clk.h>
  7. #include <common.h>
  8. #include <cpu.h>
  9. #include <dm.h>
  10. #include <errno.h>
  11. #include <log.h>
  12. #include <asm/global_data.h>
  13. #include <dm/device-internal.h>
  14. #include <dm/lists.h>
  15. #include <linux/bitops.h>
  16. #include <linux/err.h>
  17. DECLARE_GLOBAL_DATA_PTR;
  18. static int riscv_cpu_get_desc(const struct udevice *dev, char *buf, int size)
  19. {
  20. const char *isa;
  21. isa = dev_read_string(dev, "riscv,isa");
  22. if (size < (strlen(isa) + 1))
  23. return -ENOSPC;
  24. strcpy(buf, isa);
  25. return 0;
  26. }
  27. static int riscv_cpu_get_info(const struct udevice *dev, struct cpu_info *info)
  28. {
  29. int ret;
  30. struct clk clk;
  31. const char *mmu;
  32. u32 i_cache_size;
  33. u32 d_cache_size;
  34. /* First try getting the frequency from the assigned clock */
  35. ret = clk_get_by_index((struct udevice *)dev, 0, &clk);
  36. if (!ret) {
  37. ret = clk_get_rate(&clk);
  38. if (!IS_ERR_VALUE(ret))
  39. info->cpu_freq = ret;
  40. clk_free(&clk);
  41. }
  42. if (!info->cpu_freq)
  43. dev_read_u32(dev, "clock-frequency", (u32 *)&info->cpu_freq);
  44. mmu = dev_read_string(dev, "mmu-type");
  45. if (mmu)
  46. info->features |= BIT(CPU_FEAT_MMU);
  47. /* check if I cache is present */
  48. ret = dev_read_u32(dev, "i-cache-size", &i_cache_size);
  49. if (ret)
  50. /* if not found check if d-cache is present */
  51. ret = dev_read_u32(dev, "d-cache-size", &d_cache_size);
  52. /* if either I or D cache is present set L1 cache feature */
  53. if (!ret)
  54. info->features |= BIT(CPU_FEAT_L1_CACHE);
  55. return 0;
  56. }
  57. static int riscv_cpu_get_count(const struct udevice *dev)
  58. {
  59. ofnode node;
  60. int num = 0;
  61. ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) {
  62. const char *device_type;
  63. /* skip if hart is marked as not available in the device tree */
  64. if (!ofnode_is_available(node))
  65. continue;
  66. device_type = ofnode_read_string(node, "device_type");
  67. if (!device_type)
  68. continue;
  69. if (strcmp(device_type, "cpu") == 0)
  70. num++;
  71. }
  72. return num;
  73. }
  74. static int riscv_cpu_bind(struct udevice *dev)
  75. {
  76. struct cpu_plat *plat = dev_get_parent_plat(dev);
  77. struct driver *drv;
  78. int ret;
  79. /* save the hart id */
  80. plat->cpu_id = dev_read_addr(dev);
  81. /* first examine the property in current cpu node */
  82. ret = dev_read_u32(dev, "timebase-frequency", &plat->timebase_freq);
  83. /* if not found, then look at the parent /cpus node */
  84. if (ret)
  85. dev_read_u32(dev->parent, "timebase-frequency",
  86. &plat->timebase_freq);
  87. /*
  88. * Bind riscv-timer driver on boot hart.
  89. *
  90. * We only instantiate one timer device which is enough for U-Boot.
  91. * Pass the "timebase-frequency" value as the driver data for the
  92. * timer device.
  93. *
  94. * Return value is not checked since it's possible that the timer
  95. * driver is not included.
  96. */
  97. if (plat->cpu_id == gd->arch.boot_hart && plat->timebase_freq) {
  98. drv = lists_driver_lookup_name("riscv_timer");
  99. if (!drv) {
  100. debug("Cannot find the timer driver, not included?\n");
  101. return 0;
  102. }
  103. device_bind_with_driver_data(dev, drv, "riscv_timer",
  104. plat->timebase_freq, ofnode_null(),
  105. NULL);
  106. }
  107. return 0;
  108. }
  109. static int riscv_cpu_probe(struct udevice *dev)
  110. {
  111. int ret = 0;
  112. struct clk clk;
  113. /* Get a clock if it exists */
  114. ret = clk_get_by_index(dev, 0, &clk);
  115. if (ret)
  116. return 0;
  117. ret = clk_enable(&clk);
  118. clk_free(&clk);
  119. if (ret == -ENOSYS || ret == -ENOTSUPP)
  120. return 0;
  121. else
  122. return ret;
  123. }
  124. static const struct cpu_ops riscv_cpu_ops = {
  125. .get_desc = riscv_cpu_get_desc,
  126. .get_info = riscv_cpu_get_info,
  127. .get_count = riscv_cpu_get_count,
  128. };
  129. static const struct udevice_id riscv_cpu_ids[] = {
  130. { .compatible = "riscv" },
  131. { }
  132. };
  133. U_BOOT_DRIVER(riscv_cpu) = {
  134. .name = "riscv_cpu",
  135. .id = UCLASS_CPU,
  136. .of_match = riscv_cpu_ids,
  137. .bind = riscv_cpu_bind,
  138. .probe = riscv_cpu_probe,
  139. .ops = &riscv_cpu_ops,
  140. .flags = DM_FLAG_PRE_RELOC,
  141. };