imx8_cpu.c 4.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2019 NXP
  4. */
  5. #include <common.h>
  6. #include <cpu.h>
  7. #include <dm.h>
  8. #include <thermal.h>
  9. #include <asm/global_data.h>
  10. #include <asm/system.h>
  11. #include <asm/arch/sci/sci.h>
  12. #include <asm/arch/sys_proto.h>
  13. #include <asm/arch-imx/cpu.h>
  14. #include <asm/armv8/cpu.h>
  15. #include <linux/bitops.h>
  16. DECLARE_GLOBAL_DATA_PTR;
  17. struct cpu_imx_plat {
  18. const char *name;
  19. const char *rev;
  20. const char *type;
  21. u32 cpu_rsrc;
  22. u32 cpurev;
  23. u32 freq_mhz;
  24. u32 mpidr;
  25. };
  26. const char *get_imx8_type(u32 imxtype)
  27. {
  28. switch (imxtype) {
  29. case MXC_CPU_IMX8QXP:
  30. case MXC_CPU_IMX8QXP_A0:
  31. return "QXP";
  32. case MXC_CPU_IMX8QM:
  33. return "QM";
  34. default:
  35. return "??";
  36. }
  37. }
  38. const char *get_imx8_rev(u32 rev)
  39. {
  40. switch (rev) {
  41. case CHIP_REV_A:
  42. return "A";
  43. case CHIP_REV_B:
  44. return "B";
  45. case CHIP_REV_C:
  46. return "C";
  47. default:
  48. return "?";
  49. }
  50. }
  51. static void set_core_data(struct udevice *dev)
  52. {
  53. struct cpu_imx_plat *plat = dev_get_plat(dev);
  54. if (device_is_compatible(dev, "arm,cortex-a35")) {
  55. plat->cpu_rsrc = SC_R_A35;
  56. plat->name = "A35";
  57. } else if (device_is_compatible(dev, "arm,cortex-a53")) {
  58. plat->cpu_rsrc = SC_R_A53;
  59. plat->name = "A53";
  60. } else if (device_is_compatible(dev, "arm,cortex-a72")) {
  61. plat->cpu_rsrc = SC_R_A72;
  62. plat->name = "A72";
  63. } else {
  64. plat->cpu_rsrc = SC_R_A53;
  65. plat->name = "?";
  66. }
  67. }
  68. #if IS_ENABLED(CONFIG_IMX_SCU_THERMAL)
  69. static int cpu_imx_get_temp(struct cpu_imx_plat *plat)
  70. {
  71. struct udevice *thermal_dev;
  72. int cpu_tmp, ret;
  73. int idx = 1; /* use "cpu-thermal0" device */
  74. if (plat->cpu_rsrc == SC_R_A72)
  75. idx = 2; /* use "cpu-thermal1" device */
  76. ret = uclass_get_device(UCLASS_THERMAL, idx, &thermal_dev);
  77. if (!ret) {
  78. ret = thermal_get_temp(thermal_dev, &cpu_tmp);
  79. if (ret)
  80. return 0xdeadbeef;
  81. } else {
  82. return 0xdeadbeef;
  83. }
  84. return cpu_tmp;
  85. }
  86. #else
  87. static int cpu_imx_get_temp(struct cpu_imx_plat *plat)
  88. {
  89. return 0;
  90. }
  91. #endif
  92. int cpu_imx_get_desc(const struct udevice *dev, char *buf, int size)
  93. {
  94. struct cpu_imx_plat *plat = dev_get_plat(dev);
  95. int ret, temp;
  96. if (size < 100)
  97. return -ENOSPC;
  98. ret = snprintf(buf, size, "NXP i.MX8%s Rev%s %s at %u MHz",
  99. plat->type, plat->rev, plat->name, plat->freq_mhz);
  100. if (IS_ENABLED(CONFIG_IMX_SCU_THERMAL)) {
  101. temp = cpu_imx_get_temp(plat);
  102. buf = buf + ret;
  103. size = size - ret;
  104. if (temp != 0xdeadbeef)
  105. ret = snprintf(buf, size, " at %dC", temp);
  106. else
  107. ret = snprintf(buf, size, " - invalid sensor data");
  108. }
  109. snprintf(buf + ret, size - ret, "\n");
  110. return 0;
  111. }
  112. static int cpu_imx_get_info(const struct udevice *dev, struct cpu_info *info)
  113. {
  114. struct cpu_imx_plat *plat = dev_get_plat(dev);
  115. info->cpu_freq = plat->freq_mhz * 1000;
  116. info->features = BIT(CPU_FEAT_L1_CACHE) | BIT(CPU_FEAT_MMU);
  117. return 0;
  118. }
  119. static int cpu_imx_get_count(const struct udevice *dev)
  120. {
  121. ofnode node;
  122. int num = 0;
  123. ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) {
  124. const char *device_type;
  125. if (!ofnode_is_available(node))
  126. continue;
  127. device_type = ofnode_read_string(node, "device_type");
  128. if (!device_type)
  129. continue;
  130. if (!strcmp(device_type, "cpu"))
  131. num++;
  132. }
  133. return num;
  134. }
  135. static int cpu_imx_get_vendor(const struct udevice *dev, char *buf, int size)
  136. {
  137. snprintf(buf, size, "NXP");
  138. return 0;
  139. }
  140. static int cpu_imx_is_current(struct udevice *dev)
  141. {
  142. struct cpu_imx_plat *plat = dev_get_plat(dev);
  143. if (plat->mpidr == (read_mpidr() & 0xffff))
  144. return 1;
  145. return 0;
  146. }
  147. static const struct cpu_ops cpu_imx8_ops = {
  148. .get_desc = cpu_imx_get_desc,
  149. .get_info = cpu_imx_get_info,
  150. .get_count = cpu_imx_get_count,
  151. .get_vendor = cpu_imx_get_vendor,
  152. .is_current = cpu_imx_is_current,
  153. };
  154. static const struct udevice_id cpu_imx8_ids[] = {
  155. { .compatible = "arm,cortex-a35" },
  156. { .compatible = "arm,cortex-a53" },
  157. { .compatible = "arm,cortex-a72" },
  158. { }
  159. };
  160. static ulong imx8_get_cpu_rate(struct udevice *dev)
  161. {
  162. struct cpu_imx_plat *plat = dev_get_plat(dev);
  163. ulong rate;
  164. int ret;
  165. ret = sc_pm_get_clock_rate(-1, plat->cpu_rsrc, SC_PM_CLK_CPU,
  166. (sc_pm_clock_rate_t *)&rate);
  167. if (ret) {
  168. printf("Could not read CPU frequency: %d\n", ret);
  169. return 0;
  170. }
  171. return rate;
  172. }
  173. static int imx8_cpu_probe(struct udevice *dev)
  174. {
  175. struct cpu_imx_plat *plat = dev_get_plat(dev);
  176. u32 cpurev;
  177. set_core_data(dev);
  178. cpurev = get_cpu_rev();
  179. plat->cpurev = cpurev;
  180. plat->rev = get_imx8_rev(cpurev & 0xFFF);
  181. plat->type = get_imx8_type((cpurev & 0xFF000) >> 12);
  182. plat->freq_mhz = imx8_get_cpu_rate(dev) / 1000000;
  183. plat->mpidr = dev_read_addr(dev);
  184. if (plat->mpidr == FDT_ADDR_T_NONE) {
  185. printf("%s: Failed to get CPU reg property\n", __func__);
  186. return -EINVAL;
  187. }
  188. return 0;
  189. }
  190. U_BOOT_DRIVER(cpu_imx8_drv) = {
  191. .name = "imx8x_cpu",
  192. .id = UCLASS_CPU,
  193. .of_match = cpu_imx8_ids,
  194. .ops = &cpu_imx8_ops,
  195. .probe = imx8_cpu_probe,
  196. .plat_auto = sizeof(struct cpu_imx_plat),
  197. .flags = DM_FLAG_PRE_RELOC,
  198. };