clk_a64.c 2.8 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2018 Amarula Solutions.
  4. * Author: Jagan Teki <jagan@amarulasolutions.com>
  5. */
  6. #include <common.h>
  7. #include <clk-uclass.h>
  8. #include <dm.h>
  9. #include <errno.h>
  10. #include <asm/arch/ccu.h>
  11. #include <dt-bindings/clock/sun50i-a64-ccu.h>
  12. #include <dt-bindings/reset/sun50i-a64-ccu.h>
  13. #include <linux/bitops.h>
  14. static const struct ccu_clk_gate a64_gates[] = {
  15. [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
  16. [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
  17. [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
  18. [CLK_BUS_EMAC] = GATE(0x060, BIT(17)),
  19. [CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
  20. [CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
  21. [CLK_BUS_OTG] = GATE(0x060, BIT(23)),
  22. [CLK_BUS_EHCI0] = GATE(0x060, BIT(24)),
  23. [CLK_BUS_EHCI1] = GATE(0x060, BIT(25)),
  24. [CLK_BUS_OHCI0] = GATE(0x060, BIT(28)),
  25. [CLK_BUS_OHCI1] = GATE(0x060, BIT(29)),
  26. [CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
  27. [CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
  28. [CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
  29. [CLK_BUS_UART3] = GATE(0x06c, BIT(19)),
  30. [CLK_BUS_UART4] = GATE(0x06c, BIT(20)),
  31. [CLK_SPI0] = GATE(0x0a0, BIT(31)),
  32. [CLK_SPI1] = GATE(0x0a4, BIT(31)),
  33. [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
  34. [CLK_USB_PHY1] = GATE(0x0cc, BIT(9)),
  35. [CLK_USB_HSIC] = GATE(0x0cc, BIT(10)),
  36. [CLK_USB_HSIC_12M] = GATE(0x0cc, BIT(11)),
  37. [CLK_USB_OHCI0] = GATE(0x0cc, BIT(16)),
  38. [CLK_USB_OHCI1] = GATE(0x0cc, BIT(17)),
  39. };
  40. static const struct ccu_reset a64_resets[] = {
  41. [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
  42. [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
  43. [RST_USB_HSIC] = RESET(0x0cc, BIT(2)),
  44. [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
  45. [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
  46. [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
  47. [RST_BUS_EMAC] = RESET(0x2c0, BIT(17)),
  48. [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
  49. [RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
  50. [RST_BUS_OTG] = RESET(0x2c0, BIT(23)),
  51. [RST_BUS_EHCI0] = RESET(0x2c0, BIT(24)),
  52. [RST_BUS_EHCI1] = RESET(0x2c0, BIT(25)),
  53. [RST_BUS_OHCI0] = RESET(0x2c0, BIT(28)),
  54. [RST_BUS_OHCI1] = RESET(0x2c0, BIT(29)),
  55. [RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
  56. [RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
  57. [RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
  58. [RST_BUS_UART3] = RESET(0x2d8, BIT(19)),
  59. [RST_BUS_UART4] = RESET(0x2d8, BIT(20)),
  60. };
  61. static const struct ccu_desc a64_ccu_desc = {
  62. .gates = a64_gates,
  63. .resets = a64_resets,
  64. };
  65. static int a64_clk_bind(struct udevice *dev)
  66. {
  67. return sunxi_reset_bind(dev, ARRAY_SIZE(a64_resets));
  68. }
  69. static const struct udevice_id a64_ccu_ids[] = {
  70. { .compatible = "allwinner,sun50i-a64-ccu",
  71. .data = (ulong)&a64_ccu_desc },
  72. { }
  73. };
  74. U_BOOT_DRIVER(clk_sun50i_a64) = {
  75. .name = "sun50i_a64_ccu",
  76. .id = UCLASS_CLK,
  77. .of_match = a64_ccu_ids,
  78. .priv_auto = sizeof(struct ccu_priv),
  79. .ops = &sunxi_clk_ops,
  80. .probe = sunxi_clk_probe,
  81. .bind = a64_clk_bind,
  82. };