clk_a31.c 3.2 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * Copyright (C) 2018 Amarula Solutions B.V.
  4. * Author: Jagan Teki <jagan@amarulasolutions.com>
  5. */
  6. #include <common.h>
  7. #include <clk-uclass.h>
  8. #include <dm.h>
  9. #include <errno.h>
  10. #include <asm/arch/ccu.h>
  11. #include <dt-bindings/clock/sun6i-a31-ccu.h>
  12. #include <dt-bindings/reset/sun6i-a31-ccu.h>
  13. #include <linux/bitops.h>
  14. static struct ccu_clk_gate a31_gates[] = {
  15. [CLK_AHB1_MMC0] = GATE(0x060, BIT(8)),
  16. [CLK_AHB1_MMC1] = GATE(0x060, BIT(9)),
  17. [CLK_AHB1_MMC2] = GATE(0x060, BIT(10)),
  18. [CLK_AHB1_MMC3] = GATE(0x060, BIT(11)),
  19. [CLK_AHB1_EMAC] = GATE(0x060, BIT(17)),
  20. [CLK_AHB1_SPI0] = GATE(0x060, BIT(20)),
  21. [CLK_AHB1_SPI1] = GATE(0x060, BIT(21)),
  22. [CLK_AHB1_SPI2] = GATE(0x060, BIT(22)),
  23. [CLK_AHB1_SPI3] = GATE(0x060, BIT(23)),
  24. [CLK_AHB1_OTG] = GATE(0x060, BIT(24)),
  25. [CLK_AHB1_EHCI0] = GATE(0x060, BIT(26)),
  26. [CLK_AHB1_EHCI1] = GATE(0x060, BIT(27)),
  27. [CLK_AHB1_OHCI0] = GATE(0x060, BIT(29)),
  28. [CLK_AHB1_OHCI1] = GATE(0x060, BIT(30)),
  29. [CLK_AHB1_OHCI2] = GATE(0x060, BIT(31)),
  30. [CLK_APB2_UART0] = GATE(0x06c, BIT(16)),
  31. [CLK_APB2_UART1] = GATE(0x06c, BIT(17)),
  32. [CLK_APB2_UART2] = GATE(0x06c, BIT(18)),
  33. [CLK_APB2_UART3] = GATE(0x06c, BIT(19)),
  34. [CLK_APB2_UART4] = GATE(0x06c, BIT(20)),
  35. [CLK_APB2_UART5] = GATE(0x06c, BIT(21)),
  36. [CLK_SPI0] = GATE(0x0a0, BIT(31)),
  37. [CLK_SPI1] = GATE(0x0a4, BIT(31)),
  38. [CLK_SPI2] = GATE(0x0a8, BIT(31)),
  39. [CLK_SPI3] = GATE(0x0ac, BIT(31)),
  40. [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
  41. [CLK_USB_PHY1] = GATE(0x0cc, BIT(9)),
  42. [CLK_USB_PHY2] = GATE(0x0cc, BIT(10)),
  43. [CLK_USB_OHCI0] = GATE(0x0cc, BIT(16)),
  44. [CLK_USB_OHCI1] = GATE(0x0cc, BIT(17)),
  45. [CLK_USB_OHCI2] = GATE(0x0cc, BIT(18)),
  46. };
  47. static struct ccu_reset a31_resets[] = {
  48. [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
  49. [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
  50. [RST_USB_PHY2] = RESET(0x0cc, BIT(2)),
  51. [RST_AHB1_MMC0] = RESET(0x2c0, BIT(8)),
  52. [RST_AHB1_MMC1] = RESET(0x2c0, BIT(9)),
  53. [RST_AHB1_MMC2] = RESET(0x2c0, BIT(10)),
  54. [RST_AHB1_MMC3] = RESET(0x2c0, BIT(11)),
  55. [RST_AHB1_EMAC] = RESET(0x2c0, BIT(17)),
  56. [RST_AHB1_SPI0] = RESET(0x2c0, BIT(20)),
  57. [RST_AHB1_SPI1] = RESET(0x2c0, BIT(21)),
  58. [RST_AHB1_SPI2] = RESET(0x2c0, BIT(22)),
  59. [RST_AHB1_SPI3] = RESET(0x2c0, BIT(23)),
  60. [RST_AHB1_OTG] = RESET(0x2c0, BIT(24)),
  61. [RST_AHB1_EHCI0] = RESET(0x2c0, BIT(26)),
  62. [RST_AHB1_EHCI1] = RESET(0x2c0, BIT(27)),
  63. [RST_AHB1_OHCI0] = RESET(0x2c0, BIT(29)),
  64. [RST_AHB1_OHCI1] = RESET(0x2c0, BIT(30)),
  65. [RST_AHB1_OHCI2] = RESET(0x2c0, BIT(31)),
  66. [RST_APB2_UART0] = RESET(0x2d8, BIT(16)),
  67. [RST_APB2_UART1] = RESET(0x2d8, BIT(17)),
  68. [RST_APB2_UART2] = RESET(0x2d8, BIT(18)),
  69. [RST_APB2_UART3] = RESET(0x2d8, BIT(19)),
  70. [RST_APB2_UART4] = RESET(0x2d8, BIT(20)),
  71. [RST_APB2_UART5] = RESET(0x2d8, BIT(21)),
  72. };
  73. static const struct ccu_desc a31_ccu_desc = {
  74. .gates = a31_gates,
  75. .resets = a31_resets,
  76. };
  77. static int a31_clk_bind(struct udevice *dev)
  78. {
  79. return sunxi_reset_bind(dev, ARRAY_SIZE(a31_resets));
  80. }
  81. static const struct udevice_id a31_clk_ids[] = {
  82. { .compatible = "allwinner,sun6i-a31-ccu",
  83. .data = (ulong)&a31_ccu_desc },
  84. { }
  85. };
  86. U_BOOT_DRIVER(clk_sun6i_a31) = {
  87. .name = "sun6i_a31_ccu",
  88. .id = UCLASS_CLK,
  89. .of_match = a31_clk_ids,
  90. .priv_auto = sizeof(struct ccu_priv),
  91. .ops = &sunxi_clk_ops,
  92. .probe = sunxi_clk_probe,
  93. .bind = a31_clk_bind,
  94. };