fu540-prci.c 2.5 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2019 Western Digital Corporation or its affiliates.
  4. *
  5. * Copyright (C) 2018 SiFive, Inc.
  6. * Wesley Terpstra
  7. * Paul Walmsley
  8. * Zong Li
  9. * Pragnesh Patel
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License version 2 as
  13. * published by the Free Software Foundation.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * References:
  21. * - SiFive FU540-C000 manual v1p0, Chapter 7 "Clocking and Reset"
  22. */
  23. #include <dt-bindings/clock/sifive-fu540-prci.h>
  24. #include "sifive-prci.h"
  25. /* PRCI integration data for each WRPLL instance */
  26. static struct __prci_wrpll_data __prci_corepll_data = {
  27. .cfg0_offs = PRCI_COREPLLCFG0_OFFSET,
  28. .cfg1_offs = PRCI_COREPLLCFG1_OFFSET,
  29. .enable_bypass = sifive_prci_coreclksel_use_hfclk,
  30. .disable_bypass = sifive_prci_coreclksel_use_corepll,
  31. };
  32. static struct __prci_wrpll_data __prci_ddrpll_data = {
  33. .cfg0_offs = PRCI_DDRPLLCFG0_OFFSET,
  34. .cfg1_offs = PRCI_DDRPLLCFG1_OFFSET,
  35. .release_reset = sifive_prci_ddr_release_reset,
  36. };
  37. static struct __prci_wrpll_data __prci_gemgxlpll_data = {
  38. .cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET,
  39. .cfg1_offs = PRCI_GEMGXLPLLCFG1_OFFSET,
  40. .release_reset = sifive_prci_ethernet_release_reset,
  41. };
  42. /* Linux clock framework integration */
  43. static const struct __prci_clock_ops sifive_fu540_prci_wrpll_clk_ops = {
  44. .set_rate = sifive_prci_wrpll_set_rate,
  45. .round_rate = sifive_prci_wrpll_round_rate,
  46. .recalc_rate = sifive_prci_wrpll_recalc_rate,
  47. .enable_clk = sifive_prci_clock_enable,
  48. };
  49. static const struct __prci_clock_ops sifive_fu540_prci_tlclksel_clk_ops = {
  50. .recalc_rate = sifive_prci_tlclksel_recalc_rate,
  51. };
  52. /* List of clock controls provided by the PRCI */
  53. struct __prci_clock __prci_init_clocks_fu540[] = {
  54. [PRCI_CLK_COREPLL] = {
  55. .name = "corepll",
  56. .parent_name = "hfclk",
  57. .ops = &sifive_fu540_prci_wrpll_clk_ops,
  58. .pwd = &__prci_corepll_data,
  59. },
  60. [PRCI_CLK_DDRPLL] = {
  61. .name = "ddrpll",
  62. .parent_name = "hfclk",
  63. .ops = &sifive_fu540_prci_wrpll_clk_ops,
  64. .pwd = &__prci_ddrpll_data,
  65. },
  66. [PRCI_CLK_GEMGXLPLL] = {
  67. .name = "gemgxlpll",
  68. .parent_name = "hfclk",
  69. .ops = &sifive_fu540_prci_wrpll_clk_ops,
  70. .pwd = &__prci_gemgxlpll_data,
  71. },
  72. [PRCI_CLK_TLCLK] = {
  73. .name = "tlclk",
  74. .parent_name = "corepll",
  75. .ops = &sifive_fu540_prci_tlclksel_clk_ops,
  76. },
  77. };