clk_rk3568.c 70 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197219821992200220122022203220422052206220722082209221022112212221322142215221622172218221922202221222222232224222522262227222822292230223122322233223422352236223722382239224022412242224322442245224622472248224922502251225222532254225522562257225822592260226122622263226422652266226722682269227022712272227322742275227622772278227922802281228222832284228522862287228822892290229122922293229422952296229722982299230023012302230323042305230623072308230923102311231223132314231523162317231823192320232123222323232423252326232723282329233023312332233323342335233623372338233923402341234223432344234523462347234823492350235123522353235423552356235723582359236023612362236323642365236623672368236923702371237223732374237523762377237823792380238123822383238423852386238723882389239023912392239323942395239623972398239924002401240224032404240524062407240824092410241124122413241424152416241724182419242024212422242324242425242624272428242924302431243224332434243524362437243824392440244124422443244424452446244724482449245024512452245324542455245624572458245924602461246224632464246524662467246824692470247124722473247424752476247724782479248024812482248324842485248624872488248924902491249224932494249524962497249824992500250125022503250425052506250725082509251025112512251325142515251625172518251925202521252225232524252525262527252825292530253125322533253425352536253725382539254025412542254325442545254625472548254925502551255225532554255525562557255825592560256125622563256425652566256725682569257025712572257325742575257625772578257925802581258225832584258525862587258825892590259125922593259425952596259725982599260026012602260326042605260626072608260926102611261226132614261526162617261826192620262126222623262426252626262726282629263026312632263326342635263626372638263926402641264226432644264526462647264826492650265126522653265426552656265726582659266026612662266326642665266626672668266926702671267226732674267526762677267826792680268126822683268426852686268726882689269026912692269326942695269626972698269927002701270227032704270527062707270827092710271127122713271427152716271727182719272027212722272327242725272627272728272927302731273227332734273527362737273827392740274127422743274427452746274727482749275027512752275327542755275627572758275927602761276227632764276527662767276827692770277127722773277427752776277727782779278027812782278327842785278627872788278927902791279227932794279527962797279827992800280128022803280428052806280728082809281028112812281328142815281628172818281928202821282228232824282528262827282828292830283128322833283428352836283728382839284028412842284328442845284628472848284928502851285228532854285528562857285828592860286128622863286428652866286728682869287028712872287328742875287628772878287928802881288228832884288528862887288828892890289128922893289428952896289728982899290029012902290329042905290629072908290929102911291229132914291529162917291829192920292129222923292429252926292729282929293029312932293329342935293629372938293929402941294229432944294529462947294829492950295129522953295429552956295729582959
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2021 Rockchip Electronics Co., Ltd
  4. * Author: Elaine Zhang <zhangqing@rock-chips.com>
  5. */
  6. #include <common.h>
  7. #include <bitfield.h>
  8. #include <clk-uclass.h>
  9. #include <dm.h>
  10. #include <errno.h>
  11. #include <syscon.h>
  12. #include <asm/arch-rockchip/cru_rk3568.h>
  13. #include <asm/arch-rockchip/clock.h>
  14. #include <asm/arch-rockchip/hardware.h>
  15. #include <asm/io.h>
  16. #include <dm/lists.h>
  17. #include <dt-bindings/clock/rk3568-cru.h>
  18. DECLARE_GLOBAL_DATA_PTR;
  19. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  20. struct rk3568_clk_plat {
  21. struct dtd_rockchip_rk3568_cru dtd;
  22. };
  23. struct rk3568_pmuclk_plat {
  24. struct dtd_rockchip_rk3568_pmucru dtd;
  25. };
  26. #endif
  27. #define RK3568_CPUCLK_RATE(_rate, _aclk_div, _pclk_div) \
  28. { \
  29. .rate = _rate##U, \
  30. .aclk_div = _aclk_div, \
  31. .pclk_div = _pclk_div, \
  32. }
  33. #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
  34. static struct rockchip_cpu_rate_table rk3568_cpu_rates[] = {
  35. RK3568_CPUCLK_RATE(1416000000, 1, 5),
  36. RK3568_CPUCLK_RATE(1296000000, 1, 5),
  37. RK3568_CPUCLK_RATE(1200000000, 1, 3),
  38. RK3568_CPUCLK_RATE(1104000000, 1, 3),
  39. RK3568_CPUCLK_RATE(1008000000, 1, 3),
  40. RK3568_CPUCLK_RATE(912000000, 1, 3),
  41. RK3568_CPUCLK_RATE(816000000, 1, 3),
  42. RK3568_CPUCLK_RATE(600000000, 1, 1),
  43. RK3568_CPUCLK_RATE(408000000, 1, 1),
  44. { /* sentinel */ },
  45. };
  46. static struct rockchip_pll_rate_table rk3568_pll_rates[] = {
  47. /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
  48. RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
  49. RK3036_PLL_RATE(1416000000, 1, 118, 2, 1, 1, 0),
  50. RK3036_PLL_RATE(1296000000, 1, 108, 2, 1, 1, 0),
  51. RK3036_PLL_RATE(1200000000, 1, 100, 2, 1, 1, 0),
  52. RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0),
  53. RK3036_PLL_RATE(1104000000, 1, 92, 2, 1, 1, 0),
  54. RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
  55. RK3036_PLL_RATE(1000000000, 3, 250, 2, 1, 1, 0),
  56. RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
  57. RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
  58. RK3036_PLL_RATE(600000000, 1, 100, 4, 1, 1, 0),
  59. RK3036_PLL_RATE(594000000, 1, 99, 4, 1, 1, 0),
  60. RK3036_PLL_RATE(500000000, 1, 125, 6, 1, 1, 0),
  61. RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
  62. RK3036_PLL_RATE(400000000, 1, 100, 6, 1, 1, 0),
  63. RK3036_PLL_RATE(200000000, 1, 100, 6, 2, 1, 0),
  64. RK3036_PLL_RATE(100000000, 1, 150, 6, 6, 1, 0),
  65. { /* sentinel */ },
  66. };
  67. static struct rockchip_pll_clock rk3568_pll_clks[] = {
  68. [APLL] = PLL(pll_rk3328, PLL_APLL, RK3568_PLL_CON(0),
  69. RK3568_MODE_CON, 0, 10, 0, rk3568_pll_rates),
  70. [DPLL] = PLL(pll_rk3328, PLL_DPLL, RK3568_PLL_CON(8),
  71. RK3568_MODE_CON, 2, 10, 0, NULL),
  72. [CPLL] = PLL(pll_rk3328, PLL_CPLL, RK3568_PLL_CON(24),
  73. RK3568_MODE_CON, 4, 10, 0, rk3568_pll_rates),
  74. [GPLL] = PLL(pll_rk3328, PLL_HPLL, RK3568_PLL_CON(16),
  75. RK3568_MODE_CON, 6, 10, 0, rk3568_pll_rates),
  76. [NPLL] = PLL(pll_rk3328, PLL_NPLL, RK3568_PLL_CON(32),
  77. RK3568_MODE_CON, 10, 10, 0, rk3568_pll_rates),
  78. [VPLL] = PLL(pll_rk3328, PLL_VPLL, RK3568_PLL_CON(40),
  79. RK3568_MODE_CON, 12, 10, 0, rk3568_pll_rates),
  80. [PPLL] = PLL(pll_rk3328, PLL_PPLL, RK3568_PMU_PLL_CON(0),
  81. RK3568_PMU_MODE, 0, 10, 0, rk3568_pll_rates),
  82. [HPLL] = PLL(pll_rk3328, PLL_HPLL, RK3568_PMU_PLL_CON(16),
  83. RK3568_PMU_MODE, 2, 10, 0, rk3568_pll_rates),
  84. };
  85. #ifndef CONFIG_SPL_BUILD
  86. static ulong
  87. rk3568_pmu_pll_set_rate(struct rk3568_clk_priv *priv,
  88. ulong pll_id, ulong rate)
  89. {
  90. struct udevice *pmucru_dev;
  91. struct rk3568_pmuclk_priv *pmu_priv;
  92. int ret;
  93. ret = uclass_get_device_by_driver(UCLASS_CLK,
  94. DM_DRIVER_GET(rockchip_rk3568_pmucru),
  95. &pmucru_dev);
  96. if (ret) {
  97. printf("%s: could not find pmucru device\n", __func__);
  98. return ret;
  99. }
  100. pmu_priv = dev_get_priv(pmucru_dev);
  101. rockchip_pll_set_rate(&rk3568_pll_clks[pll_id],
  102. pmu_priv->pmucru, pll_id, rate);
  103. return 0;
  104. }
  105. #endif
  106. static ulong rk3568_pmu_pll_get_rate(struct rk3568_clk_priv *priv,
  107. ulong pll_id)
  108. {
  109. struct udevice *pmucru_dev;
  110. struct rk3568_pmuclk_priv *pmu_priv;
  111. int ret;
  112. ret = uclass_get_device_by_driver(UCLASS_CLK,
  113. DM_DRIVER_GET(rockchip_rk3568_pmucru),
  114. &pmucru_dev);
  115. if (ret) {
  116. printf("%s: could not find pmucru device\n", __func__);
  117. return ret;
  118. }
  119. pmu_priv = dev_get_priv(pmucru_dev);
  120. return rockchip_pll_get_rate(&rk3568_pll_clks[pll_id],
  121. pmu_priv->pmucru, pll_id);
  122. }
  123. /*
  124. *
  125. * rational_best_approximation(31415, 10000,
  126. * (1 << 8) - 1, (1 << 5) - 1, &n, &d);
  127. *
  128. * you may look at given_numerator as a fixed point number,
  129. * with the fractional part size described in given_denominator.
  130. *
  131. * for theoretical background, see:
  132. * http://en.wikipedia.org/wiki/Continued_fraction
  133. */
  134. static void rational_best_approximation(unsigned long given_numerator,
  135. unsigned long given_denominator,
  136. unsigned long max_numerator,
  137. unsigned long max_denominator,
  138. unsigned long *best_numerator,
  139. unsigned long *best_denominator)
  140. {
  141. unsigned long n, d, n0, d0, n1, d1;
  142. n = given_numerator;
  143. d = given_denominator;
  144. n0 = 0;
  145. d1 = 0;
  146. n1 = 1;
  147. d0 = 1;
  148. for (;;) {
  149. unsigned long t, a;
  150. if (n1 > max_numerator || d1 > max_denominator) {
  151. n1 = n0;
  152. d1 = d0;
  153. break;
  154. }
  155. if (d == 0)
  156. break;
  157. t = d;
  158. a = n / d;
  159. d = n % d;
  160. n = t;
  161. t = n0 + a * n1;
  162. n0 = n1;
  163. n1 = t;
  164. t = d0 + a * d1;
  165. d0 = d1;
  166. d1 = t;
  167. }
  168. *best_numerator = n1;
  169. *best_denominator = d1;
  170. }
  171. static ulong rk3568_rtc32k_get_pmuclk(struct rk3568_pmuclk_priv *priv)
  172. {
  173. struct rk3568_pmucru *pmucru = priv->pmucru;
  174. unsigned long m, n;
  175. u32 fracdiv;
  176. fracdiv = readl(&pmucru->pmu_clksel_con[1]);
  177. m = fracdiv & RTC32K_FRAC_NUMERATOR_MASK;
  178. m >>= RTC32K_FRAC_NUMERATOR_SHIFT;
  179. n = fracdiv & RTC32K_FRAC_DENOMINATOR_MASK;
  180. n >>= RTC32K_FRAC_DENOMINATOR_SHIFT;
  181. return OSC_HZ * m / n;
  182. }
  183. static ulong rk3568_rtc32k_set_pmuclk(struct rk3568_pmuclk_priv *priv,
  184. ulong rate)
  185. {
  186. struct rk3568_pmucru *pmucru = priv->pmucru;
  187. unsigned long m, n, val;
  188. rk_clrsetreg(&pmucru->pmu_clksel_con[0], RTC32K_SEL_MASK,
  189. RTC32K_SEL_OSC0_DIV32K << RTC32K_SEL_SHIFT);
  190. rational_best_approximation(rate, OSC_HZ,
  191. GENMASK(16 - 1, 0),
  192. GENMASK(16 - 1, 0),
  193. &m, &n);
  194. val = m << RTC32K_FRAC_NUMERATOR_SHIFT | n;
  195. writel(val, &pmucru->pmu_clksel_con[1]);
  196. return rk3568_rtc32k_get_pmuclk(priv);
  197. }
  198. static ulong rk3568_i2c_get_pmuclk(struct rk3568_pmuclk_priv *priv,
  199. ulong clk_id)
  200. {
  201. struct rk3568_pmucru *pmucru = priv->pmucru;
  202. u32 div, con;
  203. switch (clk_id) {
  204. case CLK_I2C0:
  205. con = readl(&pmucru->pmu_clksel_con[3]);
  206. div = (con & CLK_I2C0_DIV_MASK) >> CLK_I2C0_DIV_SHIFT;
  207. break;
  208. default:
  209. return -ENOENT;
  210. }
  211. return DIV_TO_RATE(priv->ppll_hz, div);
  212. }
  213. static ulong rk3568_i2c_set_pmuclk(struct rk3568_pmuclk_priv *priv,
  214. ulong clk_id, ulong rate)
  215. {
  216. struct rk3568_pmucru *pmucru = priv->pmucru;
  217. int src_clk_div;
  218. src_clk_div = DIV_ROUND_UP(priv->ppll_hz, rate);
  219. assert(src_clk_div - 1 <= 127);
  220. switch (clk_id) {
  221. case CLK_I2C0:
  222. rk_clrsetreg(&pmucru->pmu_clksel_con[3], CLK_I2C0_DIV_MASK,
  223. (src_clk_div - 1) << CLK_I2C0_DIV_SHIFT);
  224. break;
  225. default:
  226. return -ENOENT;
  227. }
  228. return rk3568_i2c_get_pmuclk(priv, clk_id);
  229. }
  230. static ulong rk3568_pwm_get_pmuclk(struct rk3568_pmuclk_priv *priv,
  231. ulong clk_id)
  232. {
  233. struct rk3568_pmucru *pmucru = priv->pmucru;
  234. u32 div, sel, con, parent;
  235. switch (clk_id) {
  236. case CLK_PWM0:
  237. con = readl(&pmucru->pmu_clksel_con[6]);
  238. sel = (con & CLK_PWM0_SEL_MASK) >> CLK_PWM0_SEL_SHIFT;
  239. div = (con & CLK_PWM0_DIV_MASK) >> CLK_PWM0_DIV_SHIFT;
  240. if (sel == CLK_PWM0_SEL_XIN24M)
  241. parent = OSC_HZ;
  242. else
  243. parent = priv->ppll_hz;
  244. break;
  245. default:
  246. return -ENOENT;
  247. }
  248. return DIV_TO_RATE(parent, div);
  249. }
  250. static ulong rk3568_pwm_set_pmuclk(struct rk3568_pmuclk_priv *priv,
  251. ulong clk_id, ulong rate)
  252. {
  253. struct rk3568_pmucru *pmucru = priv->pmucru;
  254. int src_clk_div;
  255. switch (clk_id) {
  256. case CLK_PWM0:
  257. if (rate == OSC_HZ) {
  258. rk_clrsetreg(&pmucru->pmu_clksel_con[6],
  259. CLK_PWM0_SEL_MASK | CLK_PWM0_DIV_MASK,
  260. (CLK_PWM0_SEL_XIN24M <<
  261. CLK_PWM0_SEL_SHIFT) |
  262. 0 << CLK_PWM0_SEL_SHIFT);
  263. } else {
  264. src_clk_div = DIV_ROUND_UP(priv->ppll_hz, rate);
  265. assert(src_clk_div - 1 <= 127);
  266. rk_clrsetreg(&pmucru->pmu_clksel_con[6],
  267. CLK_PWM0_DIV_MASK | CLK_PWM0_DIV_MASK,
  268. (CLK_PWM0_SEL_PPLL << CLK_PWM0_SEL_SHIFT) |
  269. (src_clk_div - 1) << CLK_PWM0_DIV_SHIFT);
  270. }
  271. break;
  272. default:
  273. return -ENOENT;
  274. }
  275. return rk3568_pwm_get_pmuclk(priv, clk_id);
  276. }
  277. static ulong rk3568_pmu_get_pmuclk(struct rk3568_pmuclk_priv *priv)
  278. {
  279. struct rk3568_pmucru *pmucru = priv->pmucru;
  280. u32 div, con, sel, parent;
  281. con = readl(&pmucru->pmu_clksel_con[2]);
  282. sel = (con & PCLK_PDPMU_SEL_MASK) >> PCLK_PDPMU_SEL_SHIFT;
  283. div = (con & PCLK_PDPMU_DIV_MASK) >> PCLK_PDPMU_DIV_SHIFT;
  284. if (sel)
  285. parent = GPLL_HZ;
  286. else
  287. parent = priv->ppll_hz;
  288. return DIV_TO_RATE(parent, div);
  289. }
  290. static ulong rk3568_pmu_set_pmuclk(struct rk3568_pmuclk_priv *priv,
  291. ulong rate)
  292. {
  293. struct rk3568_pmucru *pmucru = priv->pmucru;
  294. int src_clk_div;
  295. src_clk_div = DIV_ROUND_UP(priv->ppll_hz, rate);
  296. assert(src_clk_div - 1 <= 31);
  297. rk_clrsetreg(&pmucru->pmu_clksel_con[2],
  298. PCLK_PDPMU_DIV_MASK | PCLK_PDPMU_SEL_MASK,
  299. (PCLK_PDPMU_SEL_PPLL << PCLK_PDPMU_SEL_SHIFT) |
  300. ((src_clk_div - 1) << PCLK_PDPMU_DIV_SHIFT));
  301. return rk3568_pmu_get_pmuclk(priv);
  302. }
  303. static ulong rk3568_pmuclk_get_rate(struct clk *clk)
  304. {
  305. struct rk3568_pmuclk_priv *priv = dev_get_priv(clk->dev);
  306. ulong rate = 0;
  307. if (!priv->ppll_hz) {
  308. printf("%s ppll=%lu\n", __func__, priv->ppll_hz);
  309. return -ENOENT;
  310. }
  311. debug("%s %ld\n", __func__, clk->id);
  312. switch (clk->id) {
  313. case PLL_PPLL:
  314. rate = rockchip_pll_get_rate(&rk3568_pll_clks[PPLL],
  315. priv->pmucru, PPLL);
  316. break;
  317. case PLL_HPLL:
  318. rate = rockchip_pll_get_rate(&rk3568_pll_clks[HPLL],
  319. priv->pmucru, HPLL);
  320. break;
  321. case CLK_RTC_32K:
  322. case CLK_RTC32K_FRAC:
  323. rate = rk3568_rtc32k_get_pmuclk(priv);
  324. break;
  325. case CLK_I2C0:
  326. rate = rk3568_i2c_get_pmuclk(priv, clk->id);
  327. break;
  328. case CLK_PWM0:
  329. rate = rk3568_pwm_get_pmuclk(priv, clk->id);
  330. break;
  331. case PCLK_PMU:
  332. rate = rk3568_pmu_get_pmuclk(priv);
  333. break;
  334. default:
  335. return -ENOENT;
  336. }
  337. return rate;
  338. }
  339. static ulong rk3568_pmuclk_set_rate(struct clk *clk, ulong rate)
  340. {
  341. struct rk3568_pmuclk_priv *priv = dev_get_priv(clk->dev);
  342. ulong ret = 0;
  343. if (!priv->ppll_hz) {
  344. printf("%s ppll=%lu\n", __func__, priv->ppll_hz);
  345. return -ENOENT;
  346. }
  347. debug("%s %ld %ld\n", __func__, clk->id, rate);
  348. switch (clk->id) {
  349. case PLL_PPLL:
  350. ret = rockchip_pll_set_rate(&rk3568_pll_clks[PPLL],
  351. priv->pmucru, PPLL, rate);
  352. priv->ppll_hz = rockchip_pll_get_rate(&rk3568_pll_clks[PPLL],
  353. priv->pmucru, PPLL);
  354. break;
  355. case PLL_HPLL:
  356. ret = rockchip_pll_set_rate(&rk3568_pll_clks[HPLL],
  357. priv->pmucru, HPLL, rate);
  358. priv->hpll_hz = rockchip_pll_get_rate(&rk3568_pll_clks[HPLL],
  359. priv->pmucru, HPLL);
  360. break;
  361. case CLK_RTC_32K:
  362. case CLK_RTC32K_FRAC:
  363. ret = rk3568_rtc32k_set_pmuclk(priv, rate);
  364. break;
  365. case CLK_I2C0:
  366. ret = rk3568_i2c_set_pmuclk(priv, clk->id, rate);
  367. break;
  368. case CLK_PWM0:
  369. ret = rk3568_pwm_set_pmuclk(priv, clk->id, rate);
  370. break;
  371. case PCLK_PMU:
  372. ret = rk3568_pmu_set_pmuclk(priv, rate);
  373. break;
  374. default:
  375. return -ENOENT;
  376. }
  377. return ret;
  378. }
  379. static int rk3568_rtc32k_set_parent(struct clk *clk, struct clk *parent)
  380. {
  381. struct rk3568_pmuclk_priv *priv = dev_get_priv(clk->dev);
  382. struct rk3568_pmucru *pmucru = priv->pmucru;
  383. if (parent->id == CLK_RTC32K_FRAC)
  384. rk_clrsetreg(&pmucru->pmu_clksel_con[0], RTC32K_SEL_MASK,
  385. RTC32K_SEL_OSC0_DIV32K << RTC32K_SEL_SHIFT);
  386. else
  387. rk_clrsetreg(&pmucru->pmu_clksel_con[0], RTC32K_SEL_MASK,
  388. RTC32K_SEL_OSC1_32K << RTC32K_SEL_SHIFT);
  389. return 0;
  390. }
  391. static int rk3568_pmuclk_set_parent(struct clk *clk, struct clk *parent)
  392. {
  393. switch (clk->id) {
  394. case CLK_RTC_32K:
  395. return rk3568_rtc32k_set_parent(clk, parent);
  396. default:
  397. return -ENOENT;
  398. }
  399. }
  400. static struct clk_ops rk3568_pmuclk_ops = {
  401. .get_rate = rk3568_pmuclk_get_rate,
  402. .set_rate = rk3568_pmuclk_set_rate,
  403. .set_parent = rk3568_pmuclk_set_parent,
  404. };
  405. static int rk3568_pmuclk_probe(struct udevice *dev)
  406. {
  407. struct rk3568_pmuclk_priv *priv = dev_get_priv(dev);
  408. int ret = 0;
  409. if (priv->ppll_hz != PPLL_HZ) {
  410. ret = rockchip_pll_set_rate(&rk3568_pll_clks[PPLL],
  411. priv->pmucru,
  412. PPLL, PPLL_HZ);
  413. if (!ret)
  414. priv->ppll_hz = PPLL_HZ;
  415. }
  416. /* Ungate PCIe30phy refclk_m and refclk_n */
  417. rk_clrsetreg(&priv->pmucru->pmu_clkgate_con[2], 0x3 << 13, 0 << 13);
  418. return 0;
  419. }
  420. static int rk3568_pmuclk_ofdata_to_platdata(struct udevice *dev)
  421. {
  422. struct rk3568_pmuclk_priv *priv = dev_get_priv(dev);
  423. priv->pmucru = dev_read_addr_ptr(dev);
  424. return 0;
  425. }
  426. static int rk3568_pmuclk_bind(struct udevice *dev)
  427. {
  428. #if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
  429. int ret = 0;
  430. ret = offsetof(struct rk3568_pmucru, pmu_softrst_con[0]);
  431. ret = rockchip_reset_bind(dev, ret, 1);
  432. if (ret)
  433. debug("Warning: pmucru software reset driver bind faile\n");
  434. #endif
  435. return 0;
  436. }
  437. static const struct udevice_id rk3568_pmuclk_ids[] = {
  438. { .compatible = "rockchip,rk3568-pmucru" },
  439. { }
  440. };
  441. U_BOOT_DRIVER(rockchip_rk3568_pmucru) = {
  442. .name = "rockchip_rk3568_pmucru",
  443. .id = UCLASS_CLK,
  444. .of_match = rk3568_pmuclk_ids,
  445. .priv_auto = sizeof(struct rk3568_pmuclk_priv),
  446. .of_to_plat = rk3568_pmuclk_ofdata_to_platdata,
  447. .ops = &rk3568_pmuclk_ops,
  448. .bind = rk3568_pmuclk_bind,
  449. .probe = rk3568_pmuclk_probe,
  450. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  451. .plat_auto = sizeof(struct rk3568_pmuclk_plat),
  452. #endif
  453. };
  454. static int rk3568_armclk_set_clk(struct rk3568_clk_priv *priv, ulong hz)
  455. {
  456. struct rk3568_cru *cru = priv->cru;
  457. const struct rockchip_cpu_rate_table *rate;
  458. ulong old_rate;
  459. rate = rockchip_get_cpu_settings(rk3568_cpu_rates, hz);
  460. if (!rate) {
  461. printf("%s unsupported rate\n", __func__);
  462. return -EINVAL;
  463. }
  464. rk_clrsetreg(&cru->clksel_con[0],
  465. CLK_CORE_PRE_SEL_MASK,
  466. (CLK_CORE_PRE_SEL_SRC << CLK_CORE_PRE_SEL_SHIFT));
  467. rk_clrsetreg(&cru->clksel_con[2],
  468. SCLK_CORE_PRE_SEL_MASK |
  469. SCLK_CORE_SRC_SEL_MASK |
  470. SCLK_CORE_SRC_DIV_MASK,
  471. (SCLK_CORE_PRE_SEL_SRC <<
  472. SCLK_CORE_PRE_SEL_SHIFT) |
  473. (SCLK_CORE_SRC_SEL_APLL <<
  474. SCLK_CORE_SRC_SEL_SHIFT) |
  475. (1 << SCLK_CORE_SRC_DIV_SHIFT));
  476. /*
  477. * set up dependent divisors for DBG and ACLK clocks.
  478. */
  479. old_rate = rockchip_pll_get_rate(&rk3568_pll_clks[APLL],
  480. priv->cru, APLL);
  481. if (old_rate > hz) {
  482. if (rockchip_pll_set_rate(&rk3568_pll_clks[APLL],
  483. priv->cru, APLL, hz))
  484. return -EINVAL;
  485. rk_clrsetreg(&cru->clksel_con[3],
  486. GICCLK_CORE_DIV_MASK | ATCLK_CORE_DIV_MASK,
  487. rate->pclk_div << GICCLK_CORE_DIV_SHIFT |
  488. rate->pclk_div << ATCLK_CORE_DIV_SHIFT);
  489. rk_clrsetreg(&cru->clksel_con[4],
  490. PERIPHCLK_CORE_PRE_DIV_MASK |
  491. PCLK_CORE_PRE_DIV_MASK,
  492. rate->pclk_div << PCLK_CORE_PRE_DIV_SHIFT |
  493. rate->pclk_div << PERIPHCLK_CORE_PRE_DIV_SHIFT);
  494. rk_clrsetreg(&cru->clksel_con[5],
  495. ACLK_CORE_NDFT_DIV_MASK,
  496. rate->aclk_div << ACLK_CORE_NDFT_DIV_SHIFT);
  497. } else if (old_rate < hz) {
  498. rk_clrsetreg(&cru->clksel_con[3],
  499. GICCLK_CORE_DIV_MASK | ATCLK_CORE_DIV_MASK,
  500. rate->pclk_div << GICCLK_CORE_DIV_SHIFT |
  501. rate->pclk_div << ATCLK_CORE_DIV_SHIFT);
  502. rk_clrsetreg(&cru->clksel_con[4],
  503. PERIPHCLK_CORE_PRE_DIV_MASK |
  504. PCLK_CORE_PRE_DIV_MASK,
  505. rate->pclk_div << PCLK_CORE_PRE_DIV_SHIFT |
  506. rate->pclk_div << PERIPHCLK_CORE_PRE_DIV_SHIFT);
  507. rk_clrsetreg(&cru->clksel_con[5],
  508. ACLK_CORE_NDFT_DIV_MASK,
  509. rate->aclk_div << ACLK_CORE_NDFT_DIV_SHIFT);
  510. if (rockchip_pll_set_rate(&rk3568_pll_clks[APLL],
  511. priv->cru, APLL, hz))
  512. return -EINVAL;
  513. }
  514. return 0;
  515. }
  516. static ulong rk3568_cpll_div_get_rate(struct rk3568_clk_priv *priv,
  517. ulong clk_id)
  518. {
  519. struct rk3568_cru *cru = priv->cru;
  520. int div, mask, shift, con;
  521. switch (clk_id) {
  522. case CPLL_500M:
  523. con = 78;
  524. mask = CPLL_500M_DIV_MASK;
  525. shift = CPLL_500M_DIV_SHIFT;
  526. break;
  527. case CPLL_333M:
  528. con = 79;
  529. mask = CPLL_333M_DIV_MASK;
  530. shift = CPLL_333M_DIV_SHIFT;
  531. break;
  532. case CPLL_250M:
  533. con = 79;
  534. mask = CPLL_250M_DIV_MASK;
  535. shift = CPLL_250M_DIV_SHIFT;
  536. break;
  537. case CPLL_125M:
  538. con = 80;
  539. mask = CPLL_125M_DIV_MASK;
  540. shift = CPLL_125M_DIV_SHIFT;
  541. break;
  542. case CPLL_100M:
  543. con = 82;
  544. mask = CPLL_100M_DIV_MASK;
  545. shift = CPLL_100M_DIV_SHIFT;
  546. break;
  547. case CPLL_62P5M:
  548. con = 80;
  549. mask = CPLL_62P5M_DIV_MASK;
  550. shift = CPLL_62P5M_DIV_SHIFT;
  551. break;
  552. case CPLL_50M:
  553. con = 81;
  554. mask = CPLL_50M_DIV_MASK;
  555. shift = CPLL_50M_DIV_SHIFT;
  556. break;
  557. case CPLL_25M:
  558. con = 81;
  559. mask = CPLL_25M_DIV_MASK;
  560. shift = CPLL_25M_DIV_SHIFT;
  561. break;
  562. default:
  563. return -ENOENT;
  564. }
  565. div = (readl(&cru->clksel_con[con]) & mask) >> shift;
  566. return DIV_TO_RATE(priv->cpll_hz, div);
  567. }
  568. static ulong rk3568_cpll_div_set_rate(struct rk3568_clk_priv *priv,
  569. ulong clk_id, ulong rate)
  570. {
  571. struct rk3568_cru *cru = priv->cru;
  572. int div, mask, shift, con;
  573. switch (clk_id) {
  574. case CPLL_500M:
  575. con = 78;
  576. mask = CPLL_500M_DIV_MASK;
  577. shift = CPLL_500M_DIV_SHIFT;
  578. break;
  579. case CPLL_333M:
  580. con = 79;
  581. mask = CPLL_333M_DIV_MASK;
  582. shift = CPLL_333M_DIV_SHIFT;
  583. break;
  584. case CPLL_250M:
  585. con = 79;
  586. mask = CPLL_250M_DIV_MASK;
  587. shift = CPLL_250M_DIV_SHIFT;
  588. break;
  589. case CPLL_125M:
  590. con = 80;
  591. mask = CPLL_125M_DIV_MASK;
  592. shift = CPLL_125M_DIV_SHIFT;
  593. break;
  594. case CPLL_100M:
  595. con = 82;
  596. mask = CPLL_100M_DIV_MASK;
  597. shift = CPLL_100M_DIV_SHIFT;
  598. break;
  599. case CPLL_62P5M:
  600. con = 80;
  601. mask = CPLL_62P5M_DIV_MASK;
  602. shift = CPLL_62P5M_DIV_SHIFT;
  603. break;
  604. case CPLL_50M:
  605. con = 81;
  606. mask = CPLL_50M_DIV_MASK;
  607. shift = CPLL_50M_DIV_SHIFT;
  608. break;
  609. case CPLL_25M:
  610. con = 81;
  611. mask = CPLL_25M_DIV_MASK;
  612. shift = CPLL_25M_DIV_SHIFT;
  613. break;
  614. default:
  615. return -ENOENT;
  616. }
  617. div = DIV_ROUND_UP(priv->cpll_hz, rate);
  618. assert(div - 1 <= 31);
  619. rk_clrsetreg(&cru->clksel_con[con],
  620. mask, (div - 1) << shift);
  621. return rk3568_cpll_div_get_rate(priv, clk_id);
  622. }
  623. static ulong rk3568_bus_get_clk(struct rk3568_clk_priv *priv, ulong clk_id)
  624. {
  625. struct rk3568_cru *cru = priv->cru;
  626. u32 con, sel, rate;
  627. switch (clk_id) {
  628. case ACLK_BUS:
  629. con = readl(&cru->clksel_con[50]);
  630. sel = (con & ACLK_BUS_SEL_MASK) >> ACLK_BUS_SEL_SHIFT;
  631. if (sel == ACLK_BUS_SEL_200M)
  632. rate = 200 * MHz;
  633. else if (sel == ACLK_BUS_SEL_150M)
  634. rate = 150 * MHz;
  635. else if (sel == ACLK_BUS_SEL_100M)
  636. rate = 100 * MHz;
  637. else
  638. rate = OSC_HZ;
  639. break;
  640. case PCLK_BUS:
  641. case PCLK_WDT_NS:
  642. con = readl(&cru->clksel_con[50]);
  643. sel = (con & PCLK_BUS_SEL_MASK) >> PCLK_BUS_SEL_SHIFT;
  644. if (sel == PCLK_BUS_SEL_100M)
  645. rate = 100 * MHz;
  646. else if (sel == PCLK_BUS_SEL_75M)
  647. rate = 75 * MHz;
  648. else if (sel == PCLK_BUS_SEL_50M)
  649. rate = 50 * MHz;
  650. else
  651. rate = OSC_HZ;
  652. break;
  653. default:
  654. return -ENOENT;
  655. }
  656. return rate;
  657. }
  658. static ulong rk3568_bus_set_clk(struct rk3568_clk_priv *priv,
  659. ulong clk_id, ulong rate)
  660. {
  661. struct rk3568_cru *cru = priv->cru;
  662. int src_clk;
  663. switch (clk_id) {
  664. case ACLK_BUS:
  665. if (rate == 200 * MHz)
  666. src_clk = ACLK_BUS_SEL_200M;
  667. else if (rate == 150 * MHz)
  668. src_clk = ACLK_BUS_SEL_150M;
  669. else if (rate == 100 * MHz)
  670. src_clk = ACLK_BUS_SEL_100M;
  671. else
  672. src_clk = ACLK_BUS_SEL_24M;
  673. rk_clrsetreg(&cru->clksel_con[50],
  674. ACLK_BUS_SEL_MASK,
  675. src_clk << ACLK_BUS_SEL_SHIFT);
  676. break;
  677. case PCLK_BUS:
  678. case PCLK_WDT_NS:
  679. if (rate == 100 * MHz)
  680. src_clk = PCLK_BUS_SEL_100M;
  681. else if (rate == 75 * MHz)
  682. src_clk = PCLK_BUS_SEL_75M;
  683. else if (rate == 50 * MHz)
  684. src_clk = PCLK_BUS_SEL_50M;
  685. else
  686. src_clk = PCLK_BUS_SEL_24M;
  687. rk_clrsetreg(&cru->clksel_con[50],
  688. PCLK_BUS_SEL_MASK,
  689. src_clk << PCLK_BUS_SEL_SHIFT);
  690. break;
  691. default:
  692. printf("do not support this bus freq\n");
  693. return -EINVAL;
  694. }
  695. return rk3568_bus_get_clk(priv, clk_id);
  696. }
  697. static ulong rk3568_perimid_get_clk(struct rk3568_clk_priv *priv, ulong clk_id)
  698. {
  699. struct rk3568_cru *cru = priv->cru;
  700. u32 con, sel, rate;
  701. switch (clk_id) {
  702. case ACLK_PERIMID:
  703. con = readl(&cru->clksel_con[10]);
  704. sel = (con & ACLK_PERIMID_SEL_MASK) >> ACLK_PERIMID_SEL_SHIFT;
  705. if (sel == ACLK_PERIMID_SEL_300M)
  706. rate = 300 * MHz;
  707. else if (sel == ACLK_PERIMID_SEL_200M)
  708. rate = 200 * MHz;
  709. else if (sel == ACLK_PERIMID_SEL_100M)
  710. rate = 100 * MHz;
  711. else
  712. rate = OSC_HZ;
  713. break;
  714. case HCLK_PERIMID:
  715. con = readl(&cru->clksel_con[10]);
  716. sel = (con & HCLK_PERIMID_SEL_MASK) >> HCLK_PERIMID_SEL_SHIFT;
  717. if (sel == HCLK_PERIMID_SEL_150M)
  718. rate = 150 * MHz;
  719. else if (sel == HCLK_PERIMID_SEL_100M)
  720. rate = 100 * MHz;
  721. else if (sel == HCLK_PERIMID_SEL_75M)
  722. rate = 75 * MHz;
  723. else
  724. rate = OSC_HZ;
  725. break;
  726. default:
  727. return -ENOENT;
  728. }
  729. return rate;
  730. }
  731. static ulong rk3568_perimid_set_clk(struct rk3568_clk_priv *priv,
  732. ulong clk_id, ulong rate)
  733. {
  734. struct rk3568_cru *cru = priv->cru;
  735. int src_clk;
  736. switch (clk_id) {
  737. case ACLK_PERIMID:
  738. if (rate == 300 * MHz)
  739. src_clk = ACLK_PERIMID_SEL_300M;
  740. else if (rate == 200 * MHz)
  741. src_clk = ACLK_PERIMID_SEL_200M;
  742. else if (rate == 100 * MHz)
  743. src_clk = ACLK_PERIMID_SEL_100M;
  744. else
  745. src_clk = ACLK_PERIMID_SEL_24M;
  746. rk_clrsetreg(&cru->clksel_con[10],
  747. ACLK_PERIMID_SEL_MASK,
  748. src_clk << ACLK_PERIMID_SEL_SHIFT);
  749. break;
  750. case HCLK_PERIMID:
  751. if (rate == 150 * MHz)
  752. src_clk = HCLK_PERIMID_SEL_150M;
  753. else if (rate == 100 * MHz)
  754. src_clk = HCLK_PERIMID_SEL_100M;
  755. else if (rate == 75 * MHz)
  756. src_clk = HCLK_PERIMID_SEL_75M;
  757. else
  758. src_clk = HCLK_PERIMID_SEL_24M;
  759. rk_clrsetreg(&cru->clksel_con[10],
  760. HCLK_PERIMID_SEL_MASK,
  761. src_clk << HCLK_PERIMID_SEL_SHIFT);
  762. break;
  763. default:
  764. printf("do not support this permid freq\n");
  765. return -EINVAL;
  766. }
  767. return rk3568_perimid_get_clk(priv, clk_id);
  768. }
  769. static ulong rk3568_top_get_clk(struct rk3568_clk_priv *priv, ulong clk_id)
  770. {
  771. struct rk3568_cru *cru = priv->cru;
  772. u32 con, sel, rate;
  773. switch (clk_id) {
  774. case ACLK_TOP_HIGH:
  775. con = readl(&cru->clksel_con[73]);
  776. sel = (con & ACLK_TOP_HIGH_SEL_MASK) >> ACLK_TOP_HIGH_SEL_SHIFT;
  777. if (sel == ACLK_TOP_HIGH_SEL_500M)
  778. rate = 500 * MHz;
  779. else if (sel == ACLK_TOP_HIGH_SEL_400M)
  780. rate = 400 * MHz;
  781. else if (sel == ACLK_TOP_HIGH_SEL_300M)
  782. rate = 300 * MHz;
  783. else
  784. rate = OSC_HZ;
  785. break;
  786. case ACLK_TOP_LOW:
  787. con = readl(&cru->clksel_con[73]);
  788. sel = (con & ACLK_TOP_LOW_SEL_MASK) >> ACLK_TOP_LOW_SEL_SHIFT;
  789. if (sel == ACLK_TOP_LOW_SEL_400M)
  790. rate = 400 * MHz;
  791. else if (sel == ACLK_TOP_LOW_SEL_300M)
  792. rate = 300 * MHz;
  793. else if (sel == ACLK_TOP_LOW_SEL_200M)
  794. rate = 200 * MHz;
  795. else
  796. rate = OSC_HZ;
  797. break;
  798. case HCLK_TOP:
  799. con = readl(&cru->clksel_con[73]);
  800. sel = (con & HCLK_TOP_SEL_MASK) >> HCLK_TOP_SEL_SHIFT;
  801. if (sel == HCLK_TOP_SEL_150M)
  802. rate = 150 * MHz;
  803. else if (sel == HCLK_TOP_SEL_100M)
  804. rate = 100 * MHz;
  805. else if (sel == HCLK_TOP_SEL_75M)
  806. rate = 75 * MHz;
  807. else
  808. rate = OSC_HZ;
  809. break;
  810. case PCLK_TOP:
  811. con = readl(&cru->clksel_con[73]);
  812. sel = (con & PCLK_TOP_SEL_MASK) >> PCLK_TOP_SEL_SHIFT;
  813. if (sel == PCLK_TOP_SEL_100M)
  814. rate = 100 * MHz;
  815. else if (sel == PCLK_TOP_SEL_75M)
  816. rate = 75 * MHz;
  817. else if (sel == PCLK_TOP_SEL_50M)
  818. rate = 50 * MHz;
  819. else
  820. rate = OSC_HZ;
  821. break;
  822. default:
  823. return -ENOENT;
  824. }
  825. return rate;
  826. }
  827. static ulong rk3568_top_set_clk(struct rk3568_clk_priv *priv,
  828. ulong clk_id, ulong rate)
  829. {
  830. struct rk3568_cru *cru = priv->cru;
  831. int src_clk;
  832. switch (clk_id) {
  833. case ACLK_TOP_HIGH:
  834. if (rate == 500 * MHz)
  835. src_clk = ACLK_TOP_HIGH_SEL_500M;
  836. else if (rate == 400 * MHz)
  837. src_clk = ACLK_TOP_HIGH_SEL_400M;
  838. else if (rate == 300 * MHz)
  839. src_clk = ACLK_TOP_HIGH_SEL_300M;
  840. else
  841. src_clk = ACLK_TOP_HIGH_SEL_24M;
  842. rk_clrsetreg(&cru->clksel_con[73],
  843. ACLK_TOP_HIGH_SEL_MASK,
  844. src_clk << ACLK_TOP_HIGH_SEL_SHIFT);
  845. break;
  846. case ACLK_TOP_LOW:
  847. if (rate == 400 * MHz)
  848. src_clk = ACLK_TOP_LOW_SEL_400M;
  849. else if (rate == 300 * MHz)
  850. src_clk = ACLK_TOP_LOW_SEL_300M;
  851. else if (rate == 200 * MHz)
  852. src_clk = ACLK_TOP_LOW_SEL_200M;
  853. else
  854. src_clk = ACLK_TOP_LOW_SEL_24M;
  855. rk_clrsetreg(&cru->clksel_con[73],
  856. ACLK_TOP_LOW_SEL_MASK,
  857. src_clk << ACLK_TOP_LOW_SEL_SHIFT);
  858. break;
  859. case HCLK_TOP:
  860. if (rate == 150 * MHz)
  861. src_clk = HCLK_TOP_SEL_150M;
  862. else if (rate == 100 * MHz)
  863. src_clk = HCLK_TOP_SEL_100M;
  864. else if (rate == 75 * MHz)
  865. src_clk = HCLK_TOP_SEL_75M;
  866. else
  867. src_clk = HCLK_TOP_SEL_24M;
  868. rk_clrsetreg(&cru->clksel_con[73],
  869. HCLK_TOP_SEL_MASK,
  870. src_clk << HCLK_TOP_SEL_SHIFT);
  871. break;
  872. case PCLK_TOP:
  873. if (rate == 100 * MHz)
  874. src_clk = PCLK_TOP_SEL_100M;
  875. else if (rate == 75 * MHz)
  876. src_clk = PCLK_TOP_SEL_75M;
  877. else if (rate == 50 * MHz)
  878. src_clk = PCLK_TOP_SEL_50M;
  879. else
  880. src_clk = PCLK_TOP_SEL_24M;
  881. rk_clrsetreg(&cru->clksel_con[73],
  882. PCLK_TOP_SEL_MASK,
  883. src_clk << PCLK_TOP_SEL_SHIFT);
  884. break;
  885. default:
  886. printf("do not support this permid freq\n");
  887. return -EINVAL;
  888. }
  889. return rk3568_top_get_clk(priv, clk_id);
  890. }
  891. static ulong rk3568_i2c_get_clk(struct rk3568_clk_priv *priv, ulong clk_id)
  892. {
  893. struct rk3568_cru *cru = priv->cru;
  894. u32 sel, con;
  895. ulong rate;
  896. switch (clk_id) {
  897. case CLK_I2C1:
  898. case CLK_I2C2:
  899. case CLK_I2C3:
  900. case CLK_I2C4:
  901. case CLK_I2C5:
  902. con = readl(&cru->clksel_con[71]);
  903. sel = (con & CLK_I2C_SEL_MASK) >> CLK_I2C_SEL_SHIFT;
  904. if (sel == CLK_I2C_SEL_200M)
  905. rate = 200 * MHz;
  906. else if (sel == CLK_I2C_SEL_100M)
  907. rate = 100 * MHz;
  908. else if (sel == CLK_I2C_SEL_CPLL_100M)
  909. rate = 100 * MHz;
  910. else
  911. rate = OSC_HZ;
  912. break;
  913. default:
  914. return -ENOENT;
  915. }
  916. return rate;
  917. }
  918. static ulong rk3568_i2c_set_clk(struct rk3568_clk_priv *priv, ulong clk_id,
  919. ulong rate)
  920. {
  921. struct rk3568_cru *cru = priv->cru;
  922. int src_clk;
  923. if (rate == 200 * MHz)
  924. src_clk = CLK_I2C_SEL_200M;
  925. else if (rate == 100 * MHz)
  926. src_clk = CLK_I2C_SEL_100M;
  927. else
  928. src_clk = CLK_I2C_SEL_24M;
  929. switch (clk_id) {
  930. case CLK_I2C1:
  931. case CLK_I2C2:
  932. case CLK_I2C3:
  933. case CLK_I2C4:
  934. case CLK_I2C5:
  935. rk_clrsetreg(&cru->clksel_con[71], CLK_I2C_SEL_MASK,
  936. src_clk << CLK_I2C_SEL_SHIFT);
  937. break;
  938. default:
  939. return -ENOENT;
  940. }
  941. return rk3568_i2c_get_clk(priv, clk_id);
  942. }
  943. static ulong rk3568_spi_get_clk(struct rk3568_clk_priv *priv, ulong clk_id)
  944. {
  945. struct rk3568_cru *cru = priv->cru;
  946. u32 sel, con;
  947. con = readl(&cru->clksel_con[72]);
  948. switch (clk_id) {
  949. case CLK_SPI0:
  950. sel = (con & CLK_SPI0_SEL_MASK) >> CLK_SPI0_SEL_SHIFT;
  951. break;
  952. case CLK_SPI1:
  953. sel = (con & CLK_SPI1_SEL_MASK) >> CLK_SPI1_SEL_SHIFT;
  954. break;
  955. case CLK_SPI2:
  956. sel = (con & CLK_SPI2_SEL_MASK) >> CLK_SPI2_SEL_SHIFT;
  957. break;
  958. case CLK_SPI3:
  959. sel = (con & CLK_SPI3_SEL_MASK) >> CLK_SPI3_SEL_SHIFT;
  960. break;
  961. default:
  962. return -ENOENT;
  963. }
  964. switch (sel) {
  965. case CLK_SPI_SEL_200M:
  966. return 200 * MHz;
  967. case CLK_SPI_SEL_24M:
  968. return OSC_HZ;
  969. case CLK_SPI_SEL_CPLL_100M:
  970. return 100 * MHz;
  971. default:
  972. return -ENOENT;
  973. }
  974. }
  975. static ulong rk3568_spi_set_clk(struct rk3568_clk_priv *priv,
  976. ulong clk_id, ulong rate)
  977. {
  978. struct rk3568_cru *cru = priv->cru;
  979. int src_clk;
  980. if (rate == 200 * MHz)
  981. src_clk = CLK_SPI_SEL_200M;
  982. else if (rate == 100 * MHz)
  983. src_clk = CLK_SPI_SEL_CPLL_100M;
  984. else
  985. src_clk = CLK_SPI_SEL_24M;
  986. switch (clk_id) {
  987. case CLK_SPI0:
  988. rk_clrsetreg(&cru->clksel_con[72],
  989. CLK_SPI0_SEL_MASK,
  990. src_clk << CLK_SPI0_SEL_SHIFT);
  991. break;
  992. case CLK_SPI1:
  993. rk_clrsetreg(&cru->clksel_con[72],
  994. CLK_SPI1_SEL_MASK,
  995. src_clk << CLK_SPI1_SEL_SHIFT);
  996. break;
  997. case CLK_SPI2:
  998. rk_clrsetreg(&cru->clksel_con[72],
  999. CLK_SPI2_SEL_MASK,
  1000. src_clk << CLK_SPI2_SEL_SHIFT);
  1001. break;
  1002. case CLK_SPI3:
  1003. rk_clrsetreg(&cru->clksel_con[72],
  1004. CLK_SPI3_SEL_MASK,
  1005. src_clk << CLK_SPI3_SEL_SHIFT);
  1006. break;
  1007. default:
  1008. return -ENOENT;
  1009. }
  1010. return rk3568_spi_get_clk(priv, clk_id);
  1011. }
  1012. static ulong rk3568_pwm_get_clk(struct rk3568_clk_priv *priv, ulong clk_id)
  1013. {
  1014. struct rk3568_cru *cru = priv->cru;
  1015. u32 sel, con;
  1016. con = readl(&cru->clksel_con[72]);
  1017. switch (clk_id) {
  1018. case CLK_PWM1:
  1019. sel = (con & CLK_PWM1_SEL_MASK) >> CLK_PWM3_SEL_SHIFT;
  1020. break;
  1021. case CLK_PWM2:
  1022. sel = (con & CLK_PWM2_SEL_MASK) >> CLK_PWM2_SEL_SHIFT;
  1023. break;
  1024. case CLK_PWM3:
  1025. sel = (con & CLK_PWM3_SEL_MASK) >> CLK_PWM3_SEL_SHIFT;
  1026. break;
  1027. default:
  1028. return -ENOENT;
  1029. }
  1030. switch (sel) {
  1031. case CLK_PWM_SEL_100M:
  1032. return 100 * MHz;
  1033. case CLK_PWM_SEL_24M:
  1034. return OSC_HZ;
  1035. case CLK_PWM_SEL_CPLL_100M:
  1036. return 100 * MHz;
  1037. default:
  1038. return -ENOENT;
  1039. }
  1040. }
  1041. static ulong rk3568_pwm_set_clk(struct rk3568_clk_priv *priv,
  1042. ulong clk_id, ulong rate)
  1043. {
  1044. struct rk3568_cru *cru = priv->cru;
  1045. int src_clk;
  1046. if (rate == 100 * MHz)
  1047. src_clk = CLK_PWM_SEL_100M;
  1048. else
  1049. src_clk = CLK_PWM_SEL_24M;
  1050. switch (clk_id) {
  1051. case CLK_PWM1:
  1052. rk_clrsetreg(&cru->clksel_con[72],
  1053. CLK_PWM1_SEL_MASK,
  1054. src_clk << CLK_PWM1_SEL_SHIFT);
  1055. break;
  1056. case CLK_PWM2:
  1057. rk_clrsetreg(&cru->clksel_con[72],
  1058. CLK_PWM2_SEL_MASK,
  1059. src_clk << CLK_PWM2_SEL_SHIFT);
  1060. break;
  1061. case CLK_PWM3:
  1062. rk_clrsetreg(&cru->clksel_con[72],
  1063. CLK_PWM3_SEL_MASK,
  1064. src_clk << CLK_PWM3_SEL_SHIFT);
  1065. break;
  1066. default:
  1067. return -ENOENT;
  1068. }
  1069. return rk3568_pwm_get_clk(priv, clk_id);
  1070. }
  1071. static ulong rk3568_adc_get_clk(struct rk3568_clk_priv *priv, ulong clk_id)
  1072. {
  1073. struct rk3568_cru *cru = priv->cru;
  1074. u32 div, sel, con, prate;
  1075. switch (clk_id) {
  1076. case CLK_SARADC:
  1077. return OSC_HZ;
  1078. case CLK_TSADC_TSEN:
  1079. con = readl(&cru->clksel_con[51]);
  1080. div = (con & CLK_TSADC_TSEN_DIV_MASK) >>
  1081. CLK_TSADC_TSEN_DIV_SHIFT;
  1082. sel = (con & CLK_TSADC_TSEN_SEL_MASK) >>
  1083. CLK_TSADC_TSEN_SEL_SHIFT;
  1084. if (sel == CLK_TSADC_TSEN_SEL_24M)
  1085. prate = OSC_HZ;
  1086. else
  1087. prate = 100 * MHz;
  1088. return DIV_TO_RATE(prate, div);
  1089. case CLK_TSADC:
  1090. con = readl(&cru->clksel_con[51]);
  1091. div = (con & CLK_TSADC_DIV_MASK) >> CLK_TSADC_DIV_SHIFT;
  1092. prate = rk3568_adc_get_clk(priv, CLK_TSADC_TSEN);
  1093. return DIV_TO_RATE(prate, div);
  1094. default:
  1095. return -ENOENT;
  1096. }
  1097. }
  1098. static ulong rk3568_adc_set_clk(struct rk3568_clk_priv *priv,
  1099. ulong clk_id, ulong rate)
  1100. {
  1101. struct rk3568_cru *cru = priv->cru;
  1102. int src_clk_div;
  1103. ulong prate = 0;
  1104. switch (clk_id) {
  1105. case CLK_SARADC:
  1106. return OSC_HZ;
  1107. case CLK_TSADC_TSEN:
  1108. if (!(OSC_HZ % rate)) {
  1109. src_clk_div = DIV_ROUND_UP(OSC_HZ, rate);
  1110. assert(src_clk_div - 1 <= 7);
  1111. rk_clrsetreg(&cru->clksel_con[51],
  1112. CLK_TSADC_TSEN_SEL_MASK |
  1113. CLK_TSADC_TSEN_DIV_MASK,
  1114. (CLK_TSADC_TSEN_SEL_24M <<
  1115. CLK_TSADC_TSEN_SEL_SHIFT) |
  1116. (src_clk_div - 1) <<
  1117. CLK_TSADC_TSEN_DIV_SHIFT);
  1118. } else {
  1119. src_clk_div = DIV_ROUND_UP(100 * MHz, rate);
  1120. assert(src_clk_div - 1 <= 7);
  1121. rk_clrsetreg(&cru->clksel_con[51],
  1122. CLK_TSADC_TSEN_SEL_MASK |
  1123. CLK_TSADC_TSEN_DIV_MASK,
  1124. (CLK_TSADC_TSEN_SEL_100M <<
  1125. CLK_TSADC_TSEN_SEL_SHIFT) |
  1126. (src_clk_div - 1) <<
  1127. CLK_TSADC_TSEN_DIV_SHIFT);
  1128. }
  1129. break;
  1130. case CLK_TSADC:
  1131. prate = rk3568_adc_get_clk(priv, CLK_TSADC_TSEN);
  1132. src_clk_div = DIV_ROUND_UP(prate, rate);
  1133. assert(src_clk_div - 1 <= 128);
  1134. rk_clrsetreg(&cru->clksel_con[51],
  1135. CLK_TSADC_DIV_MASK,
  1136. (src_clk_div - 1) << CLK_TSADC_DIV_SHIFT);
  1137. break;
  1138. default:
  1139. return -ENOENT;
  1140. }
  1141. return rk3568_adc_get_clk(priv, clk_id);
  1142. }
  1143. static ulong rk3568_crypto_get_rate(struct rk3568_clk_priv *priv, ulong clk_id)
  1144. {
  1145. struct rk3568_cru *cru = priv->cru;
  1146. u32 sel, con;
  1147. switch (clk_id) {
  1148. case ACLK_SECURE_FLASH:
  1149. case ACLK_CRYPTO_NS:
  1150. con = readl(&cru->clksel_con[27]);
  1151. sel = (con & ACLK_SECURE_FLASH_SEL_MASK) >>
  1152. ACLK_SECURE_FLASH_SEL_SHIFT;
  1153. if (sel == ACLK_SECURE_FLASH_SEL_200M)
  1154. return 200 * MHz;
  1155. else if (sel == ACLK_SECURE_FLASH_SEL_150M)
  1156. return 150 * MHz;
  1157. else if (sel == ACLK_SECURE_FLASH_SEL_100M)
  1158. return 100 * MHz;
  1159. else
  1160. return 24 * MHz;
  1161. case HCLK_SECURE_FLASH:
  1162. case HCLK_CRYPTO_NS:
  1163. case CLK_CRYPTO_NS_RNG:
  1164. con = readl(&cru->clksel_con[27]);
  1165. sel = (con & HCLK_SECURE_FLASH_SEL_MASK) >>
  1166. HCLK_SECURE_FLASH_SEL_SHIFT;
  1167. if (sel == HCLK_SECURE_FLASH_SEL_150M)
  1168. return 150 * MHz;
  1169. else if (sel == HCLK_SECURE_FLASH_SEL_100M)
  1170. return 100 * MHz;
  1171. else if (sel == HCLK_SECURE_FLASH_SEL_75M)
  1172. return 75 * MHz;
  1173. else
  1174. return 24 * MHz;
  1175. case CLK_CRYPTO_NS_CORE:
  1176. con = readl(&cru->clksel_con[27]);
  1177. sel = (con & CLK_CRYPTO_CORE_SEL_MASK) >>
  1178. CLK_CRYPTO_CORE_SEL_SHIFT;
  1179. if (sel == CLK_CRYPTO_CORE_SEL_200M)
  1180. return 200 * MHz;
  1181. else if (sel == CLK_CRYPTO_CORE_SEL_150M)
  1182. return 150 * MHz;
  1183. else
  1184. return 100 * MHz;
  1185. case CLK_CRYPTO_NS_PKA:
  1186. con = readl(&cru->clksel_con[27]);
  1187. sel = (con & CLK_CRYPTO_PKA_SEL_MASK) >>
  1188. CLK_CRYPTO_PKA_SEL_SHIFT;
  1189. if (sel == CLK_CRYPTO_PKA_SEL_300M)
  1190. return 300 * MHz;
  1191. else if (sel == CLK_CRYPTO_PKA_SEL_200M)
  1192. return 200 * MHz;
  1193. else
  1194. return 100 * MHz;
  1195. default:
  1196. return -ENOENT;
  1197. }
  1198. }
  1199. static ulong rk3568_crypto_set_rate(struct rk3568_clk_priv *priv,
  1200. ulong clk_id, ulong rate)
  1201. {
  1202. struct rk3568_cru *cru = priv->cru;
  1203. u32 src_clk, mask, shift;
  1204. switch (clk_id) {
  1205. case ACLK_SECURE_FLASH:
  1206. case ACLK_CRYPTO_NS:
  1207. mask = ACLK_SECURE_FLASH_SEL_MASK;
  1208. shift = ACLK_SECURE_FLASH_SEL_SHIFT;
  1209. if (rate == 200 * MHz)
  1210. src_clk = ACLK_SECURE_FLASH_SEL_200M;
  1211. else if (rate == 150 * MHz)
  1212. src_clk = ACLK_SECURE_FLASH_SEL_150M;
  1213. else if (rate == 100 * MHz)
  1214. src_clk = ACLK_SECURE_FLASH_SEL_100M;
  1215. else
  1216. src_clk = ACLK_SECURE_FLASH_SEL_24M;
  1217. break;
  1218. case HCLK_SECURE_FLASH:
  1219. case HCLK_CRYPTO_NS:
  1220. case CLK_CRYPTO_NS_RNG:
  1221. mask = HCLK_SECURE_FLASH_SEL_MASK;
  1222. shift = HCLK_SECURE_FLASH_SEL_SHIFT;
  1223. if (rate == 150 * MHz)
  1224. src_clk = HCLK_SECURE_FLASH_SEL_150M;
  1225. else if (rate == 100 * MHz)
  1226. src_clk = HCLK_SECURE_FLASH_SEL_100M;
  1227. else if (rate == 75 * MHz)
  1228. src_clk = HCLK_SECURE_FLASH_SEL_75M;
  1229. else
  1230. src_clk = HCLK_SECURE_FLASH_SEL_24M;
  1231. break;
  1232. case CLK_CRYPTO_NS_CORE:
  1233. mask = CLK_CRYPTO_CORE_SEL_MASK;
  1234. shift = CLK_CRYPTO_CORE_SEL_SHIFT;
  1235. if (rate == 200 * MHz)
  1236. src_clk = CLK_CRYPTO_CORE_SEL_200M;
  1237. else if (rate == 150 * MHz)
  1238. src_clk = CLK_CRYPTO_CORE_SEL_150M;
  1239. else
  1240. src_clk = CLK_CRYPTO_CORE_SEL_100M;
  1241. break;
  1242. case CLK_CRYPTO_NS_PKA:
  1243. mask = CLK_CRYPTO_PKA_SEL_MASK;
  1244. shift = CLK_CRYPTO_PKA_SEL_SHIFT;
  1245. if (rate == 300 * MHz)
  1246. src_clk = CLK_CRYPTO_PKA_SEL_300M;
  1247. else if (rate == 200 * MHz)
  1248. src_clk = CLK_CRYPTO_PKA_SEL_200M;
  1249. else
  1250. src_clk = CLK_CRYPTO_PKA_SEL_100M;
  1251. break;
  1252. default:
  1253. return -ENOENT;
  1254. }
  1255. rk_clrsetreg(&cru->clksel_con[27], mask, src_clk << shift);
  1256. return rk3568_crypto_get_rate(priv, clk_id);
  1257. }
  1258. static ulong rk3568_sdmmc_get_clk(struct rk3568_clk_priv *priv, ulong clk_id)
  1259. {
  1260. struct rk3568_cru *cru = priv->cru;
  1261. u32 sel, con;
  1262. switch (clk_id) {
  1263. case HCLK_SDMMC0:
  1264. case CLK_SDMMC0:
  1265. con = readl(&cru->clksel_con[30]);
  1266. sel = (con & CLK_SDMMC0_SEL_MASK) >> CLK_SDMMC0_SEL_SHIFT;
  1267. break;
  1268. case CLK_SDMMC1:
  1269. con = readl(&cru->clksel_con[30]);
  1270. sel = (con & CLK_SDMMC1_SEL_MASK) >> CLK_SDMMC1_SEL_SHIFT;
  1271. break;
  1272. case CLK_SDMMC2:
  1273. con = readl(&cru->clksel_con[32]);
  1274. sel = (con & CLK_SDMMC2_SEL_MASK) >> CLK_SDMMC2_SEL_SHIFT;
  1275. break;
  1276. default:
  1277. return -ENOENT;
  1278. }
  1279. switch (sel) {
  1280. case CLK_SDMMC_SEL_24M:
  1281. return OSC_HZ;
  1282. case CLK_SDMMC_SEL_400M:
  1283. return 400 * MHz;
  1284. case CLK_SDMMC_SEL_300M:
  1285. return 300 * MHz;
  1286. case CLK_SDMMC_SEL_100M:
  1287. return 100 * MHz;
  1288. case CLK_SDMMC_SEL_50M:
  1289. return 50 * MHz;
  1290. case CLK_SDMMC_SEL_750K:
  1291. return 750 * KHz;
  1292. default:
  1293. return -ENOENT;
  1294. }
  1295. }
  1296. static ulong rk3568_sdmmc_set_clk(struct rk3568_clk_priv *priv,
  1297. ulong clk_id, ulong rate)
  1298. {
  1299. struct rk3568_cru *cru = priv->cru;
  1300. int src_clk;
  1301. switch (rate) {
  1302. case OSC_HZ:
  1303. src_clk = CLK_SDMMC_SEL_24M;
  1304. break;
  1305. case 400 * MHz:
  1306. src_clk = CLK_SDMMC_SEL_400M;
  1307. break;
  1308. case 300 * MHz:
  1309. src_clk = CLK_SDMMC_SEL_300M;
  1310. break;
  1311. case 100 * MHz:
  1312. src_clk = CLK_SDMMC_SEL_100M;
  1313. break;
  1314. case 52 * MHz:
  1315. case 50 * MHz:
  1316. src_clk = CLK_SDMMC_SEL_50M;
  1317. break;
  1318. case 750 * KHz:
  1319. case 400 * KHz:
  1320. src_clk = CLK_SDMMC_SEL_750K;
  1321. break;
  1322. default:
  1323. return -ENOENT;
  1324. }
  1325. switch (clk_id) {
  1326. case HCLK_SDMMC0:
  1327. case CLK_SDMMC0:
  1328. rk_clrsetreg(&cru->clksel_con[30],
  1329. CLK_SDMMC0_SEL_MASK,
  1330. src_clk << CLK_SDMMC0_SEL_SHIFT);
  1331. break;
  1332. case CLK_SDMMC1:
  1333. rk_clrsetreg(&cru->clksel_con[30],
  1334. CLK_SDMMC1_SEL_MASK,
  1335. src_clk << CLK_SDMMC1_SEL_SHIFT);
  1336. break;
  1337. case CLK_SDMMC2:
  1338. rk_clrsetreg(&cru->clksel_con[32],
  1339. CLK_SDMMC2_SEL_MASK,
  1340. src_clk << CLK_SDMMC2_SEL_SHIFT);
  1341. break;
  1342. default:
  1343. return -ENOENT;
  1344. }
  1345. return rk3568_sdmmc_get_clk(priv, clk_id);
  1346. }
  1347. static ulong rk3568_sfc_get_clk(struct rk3568_clk_priv *priv)
  1348. {
  1349. struct rk3568_cru *cru = priv->cru;
  1350. u32 sel, con;
  1351. con = readl(&cru->clksel_con[28]);
  1352. sel = (con & SCLK_SFC_SEL_MASK) >> SCLK_SFC_SEL_SHIFT;
  1353. switch (sel) {
  1354. case SCLK_SFC_SEL_24M:
  1355. return OSC_HZ;
  1356. case SCLK_SFC_SEL_50M:
  1357. return 50 * MHz;
  1358. case SCLK_SFC_SEL_75M:
  1359. return 75 * MHz;
  1360. case SCLK_SFC_SEL_100M:
  1361. return 100 * MHz;
  1362. case SCLK_SFC_SEL_125M:
  1363. return 125 * MHz;
  1364. case SCLK_SFC_SEL_150M:
  1365. return 150 * KHz;
  1366. default:
  1367. return -ENOENT;
  1368. }
  1369. }
  1370. static ulong rk3568_sfc_set_clk(struct rk3568_clk_priv *priv, ulong rate)
  1371. {
  1372. struct rk3568_cru *cru = priv->cru;
  1373. int src_clk;
  1374. switch (rate) {
  1375. case OSC_HZ:
  1376. src_clk = SCLK_SFC_SEL_24M;
  1377. break;
  1378. case 50 * MHz:
  1379. src_clk = SCLK_SFC_SEL_50M;
  1380. break;
  1381. case 75 * MHz:
  1382. src_clk = SCLK_SFC_SEL_75M;
  1383. break;
  1384. case 100 * MHz:
  1385. src_clk = SCLK_SFC_SEL_100M;
  1386. break;
  1387. case 125 * MHz:
  1388. src_clk = SCLK_SFC_SEL_125M;
  1389. break;
  1390. case 150 * KHz:
  1391. src_clk = SCLK_SFC_SEL_150M;
  1392. break;
  1393. default:
  1394. return -ENOENT;
  1395. }
  1396. rk_clrsetreg(&cru->clksel_con[28],
  1397. SCLK_SFC_SEL_MASK,
  1398. src_clk << SCLK_SFC_SEL_SHIFT);
  1399. return rk3568_sfc_get_clk(priv);
  1400. }
  1401. static ulong rk3568_nand_get_clk(struct rk3568_clk_priv *priv)
  1402. {
  1403. struct rk3568_cru *cru = priv->cru;
  1404. u32 sel, con;
  1405. con = readl(&cru->clksel_con[28]);
  1406. sel = (con & NCLK_NANDC_SEL_MASK) >> NCLK_NANDC_SEL_SHIFT;
  1407. switch (sel) {
  1408. case NCLK_NANDC_SEL_200M:
  1409. return 200 * MHz;
  1410. case NCLK_NANDC_SEL_150M:
  1411. return 150 * MHz;
  1412. case NCLK_NANDC_SEL_100M:
  1413. return 100 * MHz;
  1414. case NCLK_NANDC_SEL_24M:
  1415. return OSC_HZ;
  1416. default:
  1417. return -ENOENT;
  1418. }
  1419. }
  1420. static ulong rk3568_nand_set_clk(struct rk3568_clk_priv *priv, ulong rate)
  1421. {
  1422. struct rk3568_cru *cru = priv->cru;
  1423. int src_clk;
  1424. switch (rate) {
  1425. case OSC_HZ:
  1426. src_clk = NCLK_NANDC_SEL_24M;
  1427. break;
  1428. case 100 * MHz:
  1429. src_clk = NCLK_NANDC_SEL_100M;
  1430. break;
  1431. case 150 * MHz:
  1432. src_clk = NCLK_NANDC_SEL_150M;
  1433. break;
  1434. case 200 * MHz:
  1435. src_clk = NCLK_NANDC_SEL_200M;
  1436. break;
  1437. default:
  1438. return -ENOENT;
  1439. }
  1440. rk_clrsetreg(&cru->clksel_con[28],
  1441. NCLK_NANDC_SEL_MASK,
  1442. src_clk << NCLK_NANDC_SEL_SHIFT);
  1443. return rk3568_nand_get_clk(priv);
  1444. }
  1445. static ulong rk3568_emmc_get_clk(struct rk3568_clk_priv *priv)
  1446. {
  1447. struct rk3568_cru *cru = priv->cru;
  1448. u32 sel, con;
  1449. con = readl(&cru->clksel_con[28]);
  1450. sel = (con & CCLK_EMMC_SEL_MASK) >> CCLK_EMMC_SEL_SHIFT;
  1451. switch (sel) {
  1452. case CCLK_EMMC_SEL_200M:
  1453. return 200 * MHz;
  1454. case CCLK_EMMC_SEL_150M:
  1455. return 150 * MHz;
  1456. case CCLK_EMMC_SEL_100M:
  1457. return 100 * MHz;
  1458. case CCLK_EMMC_SEL_50M:
  1459. return 50 * MHz;
  1460. case CCLK_EMMC_SEL_375K:
  1461. return 375 * KHz;
  1462. case CCLK_EMMC_SEL_24M:
  1463. return OSC_HZ;
  1464. default:
  1465. return -ENOENT;
  1466. }
  1467. }
  1468. static ulong rk3568_emmc_set_clk(struct rk3568_clk_priv *priv, ulong rate)
  1469. {
  1470. struct rk3568_cru *cru = priv->cru;
  1471. int src_clk;
  1472. switch (rate) {
  1473. case OSC_HZ:
  1474. src_clk = CCLK_EMMC_SEL_24M;
  1475. break;
  1476. case 52 * MHz:
  1477. case 50 * MHz:
  1478. src_clk = CCLK_EMMC_SEL_50M;
  1479. break;
  1480. case 100 * MHz:
  1481. src_clk = CCLK_EMMC_SEL_100M;
  1482. break;
  1483. case 150 * MHz:
  1484. src_clk = CCLK_EMMC_SEL_150M;
  1485. break;
  1486. case 200 * MHz:
  1487. src_clk = CCLK_EMMC_SEL_200M;
  1488. break;
  1489. case 400 * KHz:
  1490. case 375 * KHz:
  1491. src_clk = CCLK_EMMC_SEL_375K;
  1492. break;
  1493. default:
  1494. return -ENOENT;
  1495. }
  1496. rk_clrsetreg(&cru->clksel_con[28],
  1497. CCLK_EMMC_SEL_MASK,
  1498. src_clk << CCLK_EMMC_SEL_SHIFT);
  1499. return rk3568_emmc_get_clk(priv);
  1500. }
  1501. static ulong rk3568_emmc_get_bclk(struct rk3568_clk_priv *priv)
  1502. {
  1503. struct rk3568_cru *cru = priv->cru;
  1504. u32 sel, con;
  1505. con = readl(&cru->clksel_con[28]);
  1506. sel = (con & BCLK_EMMC_SEL_MASK) >> BCLK_EMMC_SEL_SHIFT;
  1507. switch (sel) {
  1508. case BCLK_EMMC_SEL_200M:
  1509. return 200 * MHz;
  1510. case BCLK_EMMC_SEL_150M:
  1511. return 150 * MHz;
  1512. case BCLK_EMMC_SEL_125M:
  1513. return 125 * MHz;
  1514. default:
  1515. return -ENOENT;
  1516. }
  1517. }
  1518. static ulong rk3568_emmc_set_bclk(struct rk3568_clk_priv *priv, ulong rate)
  1519. {
  1520. struct rk3568_cru *cru = priv->cru;
  1521. int src_clk;
  1522. switch (rate) {
  1523. case 200 * MHz:
  1524. src_clk = BCLK_EMMC_SEL_200M;
  1525. break;
  1526. case 150 * MHz:
  1527. src_clk = BCLK_EMMC_SEL_150M;
  1528. break;
  1529. case 125 * MHz:
  1530. src_clk = BCLK_EMMC_SEL_125M;
  1531. break;
  1532. default:
  1533. return -ENOENT;
  1534. }
  1535. rk_clrsetreg(&cru->clksel_con[28],
  1536. BCLK_EMMC_SEL_MASK,
  1537. src_clk << BCLK_EMMC_SEL_SHIFT);
  1538. return rk3568_emmc_get_bclk(priv);
  1539. }
  1540. #ifndef CONFIG_SPL_BUILD
  1541. static ulong rk3568_aclk_vop_get_clk(struct rk3568_clk_priv *priv)
  1542. {
  1543. struct rk3568_cru *cru = priv->cru;
  1544. u32 div, sel, con, parent;
  1545. con = readl(&cru->clksel_con[38]);
  1546. div = (con & ACLK_VOP_PRE_DIV_MASK) >> ACLK_VOP_PRE_DIV_SHIFT;
  1547. sel = (con & ACLK_VOP_PRE_SEL_MASK) >> ACLK_VOP_PRE_SEL_SHIFT;
  1548. if (sel == ACLK_VOP_PRE_SEL_GPLL)
  1549. parent = priv->gpll_hz;
  1550. else if (sel == ACLK_VOP_PRE_SEL_CPLL)
  1551. parent = priv->cpll_hz;
  1552. else if (sel == ACLK_VOP_PRE_SEL_VPLL)
  1553. parent = priv->vpll_hz;
  1554. else
  1555. parent = priv->hpll_hz;
  1556. return DIV_TO_RATE(parent, div);
  1557. }
  1558. static ulong rk3568_aclk_vop_set_clk(struct rk3568_clk_priv *priv, ulong rate)
  1559. {
  1560. struct rk3568_cru *cru = priv->cru;
  1561. int src_clk_div, src_clk_mux;
  1562. if ((priv->cpll_hz % rate) == 0) {
  1563. src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate);
  1564. src_clk_mux = ACLK_VOP_PRE_SEL_CPLL;
  1565. } else {
  1566. src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate);
  1567. src_clk_mux = ACLK_VOP_PRE_SEL_GPLL;
  1568. }
  1569. assert(src_clk_div - 1 <= 31);
  1570. rk_clrsetreg(&cru->clksel_con[38],
  1571. ACLK_VOP_PRE_SEL_MASK | ACLK_VOP_PRE_DIV_MASK,
  1572. src_clk_mux << ACLK_VOP_PRE_SEL_SHIFT |
  1573. (src_clk_div - 1) << ACLK_VOP_PRE_DIV_SHIFT);
  1574. return rk3568_aclk_vop_get_clk(priv);
  1575. }
  1576. static ulong rk3568_dclk_vop_get_clk(struct rk3568_clk_priv *priv, ulong clk_id)
  1577. {
  1578. struct rk3568_cru *cru = priv->cru;
  1579. u32 conid, div, sel, con, parent;
  1580. switch (clk_id) {
  1581. case DCLK_VOP0:
  1582. conid = 39;
  1583. break;
  1584. case DCLK_VOP1:
  1585. conid = 40;
  1586. break;
  1587. case DCLK_VOP2:
  1588. conid = 41;
  1589. break;
  1590. default:
  1591. return -ENOENT;
  1592. }
  1593. con = readl(&cru->clksel_con[conid]);
  1594. div = (con & DCLK0_VOP_DIV_MASK) >> DCLK0_VOP_DIV_SHIFT;
  1595. sel = (con & DCLK0_VOP_SEL_MASK) >> DCLK0_VOP_SEL_SHIFT;
  1596. if (sel == DCLK_VOP_SEL_HPLL)
  1597. parent = rk3568_pmu_pll_get_rate(priv, HPLL);
  1598. else if (sel == DCLK_VOP_SEL_VPLL)
  1599. parent = rockchip_pll_get_rate(&rk3568_pll_clks[VPLL],
  1600. priv->cru, VPLL);
  1601. else if (sel == DCLK_VOP_SEL_GPLL)
  1602. parent = priv->gpll_hz;
  1603. else if (sel == DCLK_VOP_SEL_CPLL)
  1604. parent = priv->cpll_hz;
  1605. else
  1606. return -ENOENT;
  1607. return DIV_TO_RATE(parent, div);
  1608. }
  1609. #define RK3568_VOP_PLL_LIMIT_FREQ 600000000
  1610. static ulong rk3568_dclk_vop_set_clk(struct rk3568_clk_priv *priv,
  1611. ulong clk_id, ulong rate)
  1612. {
  1613. struct rk3568_cru *cru = priv->cru;
  1614. ulong pll_rate, now, best_rate = 0;
  1615. u32 i, conid, con, sel, div, best_div = 0, best_sel = 0;
  1616. switch (clk_id) {
  1617. case DCLK_VOP0:
  1618. conid = 39;
  1619. break;
  1620. case DCLK_VOP1:
  1621. conid = 40;
  1622. break;
  1623. case DCLK_VOP2:
  1624. conid = 41;
  1625. break;
  1626. default:
  1627. return -ENOENT;
  1628. }
  1629. con = readl(&cru->clksel_con[conid]);
  1630. sel = (con & DCLK0_VOP_SEL_MASK) >> DCLK0_VOP_SEL_SHIFT;
  1631. if (sel == DCLK_VOP_SEL_HPLL) {
  1632. div = 1;
  1633. rk_clrsetreg(&cru->clksel_con[conid],
  1634. DCLK0_VOP_DIV_MASK | DCLK0_VOP_SEL_MASK,
  1635. (DCLK_VOP_SEL_HPLL << DCLK0_VOP_SEL_SHIFT) |
  1636. ((div - 1) << DCLK0_VOP_DIV_SHIFT));
  1637. rk3568_pmu_pll_set_rate(priv, HPLL, div * rate);
  1638. } else if (sel == DCLK_VOP_SEL_VPLL) {
  1639. div = DIV_ROUND_UP(RK3568_VOP_PLL_LIMIT_FREQ, rate);
  1640. rk_clrsetreg(&cru->clksel_con[conid],
  1641. DCLK0_VOP_DIV_MASK | DCLK0_VOP_SEL_MASK,
  1642. (DCLK_VOP_SEL_VPLL << DCLK0_VOP_SEL_SHIFT) |
  1643. ((div - 1) << DCLK0_VOP_DIV_SHIFT));
  1644. rockchip_pll_set_rate(&rk3568_pll_clks[VPLL],
  1645. priv->cru, VPLL, div * rate);
  1646. } else {
  1647. for (i = 0; i <= DCLK_VOP_SEL_CPLL; i++) {
  1648. switch (i) {
  1649. case DCLK_VOP_SEL_GPLL:
  1650. pll_rate = priv->gpll_hz;
  1651. break;
  1652. case DCLK_VOP_SEL_CPLL:
  1653. pll_rate = priv->cpll_hz;
  1654. break;
  1655. default:
  1656. printf("do not support this vop pll sel\n");
  1657. return -EINVAL;
  1658. }
  1659. div = DIV_ROUND_UP(pll_rate, rate);
  1660. if (div > 255)
  1661. continue;
  1662. now = pll_rate / div;
  1663. if (abs(rate - now) < abs(rate - best_rate)) {
  1664. best_rate = now;
  1665. best_div = div;
  1666. best_sel = i;
  1667. }
  1668. debug("p_rate=%lu, best_rate=%lu, div=%u, sel=%u\n",
  1669. pll_rate, best_rate, best_div, best_sel);
  1670. }
  1671. if (best_rate) {
  1672. rk_clrsetreg(&cru->clksel_con[conid],
  1673. DCLK0_VOP_DIV_MASK | DCLK0_VOP_SEL_MASK,
  1674. best_sel << DCLK0_VOP_SEL_SHIFT |
  1675. (best_div - 1) << DCLK0_VOP_DIV_SHIFT);
  1676. } else {
  1677. printf("do not support this vop freq %lu\n", rate);
  1678. return -EINVAL;
  1679. }
  1680. }
  1681. return rk3568_dclk_vop_get_clk(priv, clk_id);
  1682. }
  1683. static ulong rk3568_gmac_src_get_clk(struct rk3568_clk_priv *priv,
  1684. ulong mac_id)
  1685. {
  1686. struct rk3568_cru *cru = priv->cru;
  1687. u32 sel, con;
  1688. con = readl(&cru->clksel_con[31 + mac_id * 2]);
  1689. sel = (con & CLK_MAC0_2TOP_SEL_MASK) >> CLK_MAC0_2TOP_SEL_SHIFT;
  1690. switch (sel) {
  1691. case CLK_MAC0_2TOP_SEL_125M:
  1692. return 125 * MHz;
  1693. case CLK_MAC0_2TOP_SEL_50M:
  1694. return 50 * MHz;
  1695. case CLK_MAC0_2TOP_SEL_25M:
  1696. return 25 * MHz;
  1697. case CLK_MAC0_2TOP_SEL_PPLL:
  1698. return rk3568_pmu_pll_get_rate(priv, HPLL);
  1699. default:
  1700. return -ENOENT;
  1701. }
  1702. }
  1703. static ulong rk3568_gmac_src_set_clk(struct rk3568_clk_priv *priv,
  1704. ulong mac_id, ulong rate)
  1705. {
  1706. struct rk3568_cru *cru = priv->cru;
  1707. int src_clk;
  1708. switch (rate) {
  1709. case 125 * MHz:
  1710. src_clk = CLK_MAC0_2TOP_SEL_125M;
  1711. break;
  1712. case 50 * MHz:
  1713. src_clk = CLK_MAC0_2TOP_SEL_50M;
  1714. break;
  1715. case 25 * MHz:
  1716. src_clk = CLK_MAC0_2TOP_SEL_25M;
  1717. break;
  1718. default:
  1719. return -ENOENT;
  1720. }
  1721. rk_clrsetreg(&cru->clksel_con[31 + mac_id * 2],
  1722. CLK_MAC0_2TOP_SEL_MASK,
  1723. src_clk << CLK_MAC0_2TOP_SEL_SHIFT);
  1724. return rk3568_gmac_src_get_clk(priv, mac_id);
  1725. }
  1726. static ulong rk3568_gmac_out_get_clk(struct rk3568_clk_priv *priv,
  1727. ulong mac_id)
  1728. {
  1729. struct rk3568_cru *cru = priv->cru;
  1730. u32 sel, con;
  1731. con = readl(&cru->clksel_con[31 + mac_id * 2]);
  1732. sel = (con & CLK_MAC0_OUT_SEL_MASK) >> CLK_MAC0_OUT_SEL_SHIFT;
  1733. switch (sel) {
  1734. case CLK_MAC0_OUT_SEL_125M:
  1735. return 125 * MHz;
  1736. case CLK_MAC0_OUT_SEL_50M:
  1737. return 50 * MHz;
  1738. case CLK_MAC0_OUT_SEL_25M:
  1739. return 25 * MHz;
  1740. case CLK_MAC0_OUT_SEL_24M:
  1741. return OSC_HZ;
  1742. default:
  1743. return -ENOENT;
  1744. }
  1745. }
  1746. static ulong rk3568_gmac_out_set_clk(struct rk3568_clk_priv *priv,
  1747. ulong mac_id, ulong rate)
  1748. {
  1749. struct rk3568_cru *cru = priv->cru;
  1750. int src_clk;
  1751. switch (rate) {
  1752. case 125 * MHz:
  1753. src_clk = CLK_MAC0_OUT_SEL_125M;
  1754. break;
  1755. case 50 * MHz:
  1756. src_clk = CLK_MAC0_OUT_SEL_50M;
  1757. break;
  1758. case 25 * MHz:
  1759. src_clk = CLK_MAC0_OUT_SEL_25M;
  1760. break;
  1761. case 24 * MHz:
  1762. src_clk = CLK_MAC0_OUT_SEL_24M;
  1763. break;
  1764. default:
  1765. return -ENOENT;
  1766. }
  1767. rk_clrsetreg(&cru->clksel_con[31 + mac_id * 2],
  1768. CLK_MAC0_OUT_SEL_MASK,
  1769. src_clk << CLK_MAC0_OUT_SEL_SHIFT);
  1770. return rk3568_gmac_out_get_clk(priv, mac_id);
  1771. }
  1772. static ulong rk3568_gmac_ptp_ref_get_clk(struct rk3568_clk_priv *priv,
  1773. ulong mac_id)
  1774. {
  1775. struct rk3568_cru *cru = priv->cru;
  1776. u32 sel, con;
  1777. con = readl(&cru->clksel_con[31 + mac_id * 2]);
  1778. sel = (con & CLK_GMAC0_PTP_REF_SEL_MASK) >> CLK_GMAC0_PTP_REF_SEL_SHIFT;
  1779. switch (sel) {
  1780. case CLK_GMAC0_PTP_REF_SEL_62_5M:
  1781. return 62500 * KHz;
  1782. case CLK_GMAC0_PTP_REF_SEL_100M:
  1783. return 100 * MHz;
  1784. case CLK_GMAC0_PTP_REF_SEL_50M:
  1785. return 50 * MHz;
  1786. case CLK_GMAC0_PTP_REF_SEL_24M:
  1787. return OSC_HZ;
  1788. default:
  1789. return -ENOENT;
  1790. }
  1791. }
  1792. static ulong rk3568_gmac_ptp_ref_set_clk(struct rk3568_clk_priv *priv,
  1793. ulong mac_id, ulong rate)
  1794. {
  1795. struct rk3568_cru *cru = priv->cru;
  1796. int src_clk;
  1797. switch (rate) {
  1798. case 62500 * KHz:
  1799. src_clk = CLK_GMAC0_PTP_REF_SEL_62_5M;
  1800. break;
  1801. case 100 * MHz:
  1802. src_clk = CLK_GMAC0_PTP_REF_SEL_100M;
  1803. break;
  1804. case 50 * MHz:
  1805. src_clk = CLK_GMAC0_PTP_REF_SEL_50M;
  1806. break;
  1807. case 24 * MHz:
  1808. src_clk = CLK_GMAC0_PTP_REF_SEL_24M;
  1809. break;
  1810. default:
  1811. return -ENOENT;
  1812. }
  1813. rk_clrsetreg(&cru->clksel_con[31 + mac_id * 2],
  1814. CLK_GMAC0_PTP_REF_SEL_MASK,
  1815. src_clk << CLK_GMAC0_PTP_REF_SEL_SHIFT);
  1816. return rk3568_gmac_ptp_ref_get_clk(priv, mac_id);
  1817. }
  1818. static ulong rk3568_gmac_tx_rx_set_clk(struct rk3568_clk_priv *priv,
  1819. ulong mac_id, ulong rate)
  1820. {
  1821. struct rk3568_cru *cru = priv->cru;
  1822. u32 con, sel, div_sel;
  1823. con = readl(&cru->clksel_con[31 + mac_id * 2]);
  1824. sel = (con & RMII0_MODE_MASK) >> RMII0_MODE_SHIFT;
  1825. if (sel == RMII0_MODE_SEL_RGMII) {
  1826. if (rate == 2500000)
  1827. div_sel = RGMII0_CLK_SEL_2_5M;
  1828. else if (rate == 25000000)
  1829. div_sel = RGMII0_CLK_SEL_25M;
  1830. else
  1831. div_sel = RGMII0_CLK_SEL_125M;
  1832. rk_clrsetreg(&cru->clksel_con[31 + mac_id * 2],
  1833. RGMII0_CLK_SEL_MASK,
  1834. div_sel << RGMII0_CLK_SEL_SHIFT);
  1835. } else if (sel == RMII0_MODE_SEL_RMII) {
  1836. if (rate == 2500000)
  1837. div_sel = RMII0_CLK_SEL_2_5M;
  1838. else
  1839. div_sel = RMII0_CLK_SEL_25M;
  1840. rk_clrsetreg(&cru->clksel_con[31 + mac_id * 2],
  1841. RMII0_CLK_SEL_MASK,
  1842. div_sel << RMII0_CLK_SEL_SHIFT);
  1843. }
  1844. return 0;
  1845. }
  1846. static ulong rk3568_ebc_get_clk(struct rk3568_clk_priv *priv)
  1847. {
  1848. struct rk3568_cru *cru = priv->cru;
  1849. u32 con, div, p_rate;
  1850. con = readl(&cru->clksel_con[79]);
  1851. div = (con & CPLL_333M_DIV_MASK) >> CPLL_333M_DIV_SHIFT;
  1852. p_rate = DIV_TO_RATE(priv->cpll_hz, div);
  1853. con = readl(&cru->clksel_con[43]);
  1854. div = (con & DCLK_EBC_SEL_MASK) >> DCLK_EBC_SEL_SHIFT;
  1855. switch (div) {
  1856. case DCLK_EBC_SEL_GPLL_400M:
  1857. return 400 * MHz;
  1858. case DCLK_EBC_SEL_CPLL_333M:
  1859. return p_rate;
  1860. case DCLK_EBC_SEL_GPLL_200M:
  1861. return 200 * MHz;
  1862. default:
  1863. return -ENOENT;
  1864. }
  1865. }
  1866. static ulong rk3568_ebc_set_clk(struct rk3568_clk_priv *priv, ulong rate)
  1867. {
  1868. struct rk3568_cru *cru = priv->cru;
  1869. int src_clk_div;
  1870. src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate);
  1871. assert(src_clk_div - 1 <= 31);
  1872. rk_clrsetreg(&cru->clksel_con[79],
  1873. CPLL_333M_DIV_MASK,
  1874. (src_clk_div - 1) << CPLL_333M_DIV_SHIFT);
  1875. rk_clrsetreg(&cru->clksel_con[43],
  1876. DCLK_EBC_SEL_MASK,
  1877. DCLK_EBC_SEL_CPLL_333M << DCLK_EBC_SEL_SHIFT);
  1878. return rk3568_ebc_get_clk(priv);
  1879. }
  1880. static ulong rk3568_rkvdec_get_clk(struct rk3568_clk_priv *priv, ulong clk_id)
  1881. {
  1882. struct rk3568_cru *cru = priv->cru;
  1883. u32 con, div, src, p_rate;
  1884. switch (clk_id) {
  1885. case ACLK_RKVDEC_PRE:
  1886. case ACLK_RKVDEC:
  1887. con = readl(&cru->clksel_con[47]);
  1888. src = (con & ACLK_RKVDEC_SEL_MASK) >> ACLK_RKVDEC_SEL_SHIFT;
  1889. div = (con & ACLK_RKVDEC_DIV_MASK) >> ACLK_RKVDEC_DIV_SHIFT;
  1890. if (src == ACLK_RKVDEC_SEL_CPLL)
  1891. p_rate = priv->cpll_hz;
  1892. else
  1893. p_rate = priv->gpll_hz;
  1894. return DIV_TO_RATE(p_rate, div);
  1895. case CLK_RKVDEC_CORE:
  1896. con = readl(&cru->clksel_con[49]);
  1897. src = (con & CLK_RKVDEC_CORE_SEL_MASK)
  1898. >> CLK_RKVDEC_CORE_SEL_SHIFT;
  1899. div = (con & CLK_RKVDEC_CORE_DIV_MASK)
  1900. >> CLK_RKVDEC_CORE_DIV_SHIFT;
  1901. if (src == CLK_RKVDEC_CORE_SEL_CPLL)
  1902. p_rate = priv->cpll_hz;
  1903. else if (src == CLK_RKVDEC_CORE_SEL_NPLL)
  1904. p_rate = priv->npll_hz;
  1905. else if (src == CLK_RKVDEC_CORE_SEL_VPLL)
  1906. p_rate = priv->vpll_hz;
  1907. else
  1908. p_rate = priv->gpll_hz;
  1909. return DIV_TO_RATE(p_rate, div);
  1910. default:
  1911. return -ENOENT;
  1912. }
  1913. }
  1914. static ulong rk3568_rkvdec_set_clk(struct rk3568_clk_priv *priv,
  1915. ulong clk_id, ulong rate)
  1916. {
  1917. struct rk3568_cru *cru = priv->cru;
  1918. int src_clk_div, src, p_rate;
  1919. switch (clk_id) {
  1920. case ACLK_RKVDEC_PRE:
  1921. case ACLK_RKVDEC:
  1922. src = (readl(&cru->clksel_con[47]) & ACLK_RKVDEC_SEL_MASK)
  1923. >> ACLK_RKVDEC_SEL_SHIFT;
  1924. if (src == ACLK_RKVDEC_SEL_CPLL)
  1925. p_rate = priv->cpll_hz;
  1926. else
  1927. p_rate = priv->gpll_hz;
  1928. src_clk_div = DIV_ROUND_UP(p_rate, rate);
  1929. assert(src_clk_div - 1 <= 31);
  1930. rk_clrsetreg(&cru->clksel_con[47],
  1931. ACLK_RKVDEC_SEL_MASK |
  1932. ACLK_RKVDEC_DIV_MASK,
  1933. (src << ACLK_RKVDEC_SEL_SHIFT) |
  1934. (src_clk_div - 1) << ACLK_RKVDEC_DIV_SHIFT);
  1935. break;
  1936. case CLK_RKVDEC_CORE:
  1937. src = (readl(&cru->clksel_con[49]) & CLK_RKVDEC_CORE_SEL_MASK)
  1938. >> CLK_RKVDEC_CORE_SEL_SHIFT;
  1939. if (src == CLK_RKVDEC_CORE_SEL_CPLL)
  1940. p_rate = priv->cpll_hz;
  1941. else if (src == CLK_RKVDEC_CORE_SEL_NPLL)
  1942. p_rate = priv->npll_hz;
  1943. else if (src == CLK_RKVDEC_CORE_SEL_VPLL)
  1944. p_rate = priv->vpll_hz;
  1945. else
  1946. p_rate = priv->gpll_hz;
  1947. src_clk_div = DIV_ROUND_UP(p_rate, rate);
  1948. assert(src_clk_div - 1 <= 31);
  1949. rk_clrsetreg(&cru->clksel_con[49],
  1950. CLK_RKVDEC_CORE_SEL_MASK |
  1951. CLK_RKVDEC_CORE_DIV_MASK,
  1952. (src << CLK_RKVDEC_CORE_SEL_SHIFT) |
  1953. (src_clk_div - 1) << CLK_RKVDEC_CORE_DIV_SHIFT);
  1954. break;
  1955. default:
  1956. return -ENOENT;
  1957. }
  1958. return rk3568_rkvdec_get_clk(priv, clk_id);
  1959. }
  1960. static ulong rk3568_uart_get_rate(struct rk3568_clk_priv *priv, ulong clk_id)
  1961. {
  1962. struct rk3568_cru *cru = priv->cru;
  1963. u32 reg, con, fracdiv, div, src, p_src, p_rate;
  1964. unsigned long m, n;
  1965. switch (clk_id) {
  1966. case SCLK_UART1:
  1967. reg = 52;
  1968. break;
  1969. case SCLK_UART2:
  1970. reg = 54;
  1971. break;
  1972. case SCLK_UART3:
  1973. reg = 56;
  1974. break;
  1975. case SCLK_UART4:
  1976. reg = 58;
  1977. break;
  1978. case SCLK_UART5:
  1979. reg = 60;
  1980. break;
  1981. case SCLK_UART6:
  1982. reg = 62;
  1983. break;
  1984. case SCLK_UART7:
  1985. reg = 64;
  1986. break;
  1987. case SCLK_UART8:
  1988. reg = 66;
  1989. break;
  1990. case SCLK_UART9:
  1991. reg = 68;
  1992. break;
  1993. default:
  1994. return -ENOENT;
  1995. }
  1996. con = readl(&cru->clksel_con[reg]);
  1997. src = (con & CLK_UART_SEL_MASK) >> CLK_UART_SEL_SHIFT;
  1998. div = (con & CLK_UART_SRC_DIV_MASK) >> CLK_UART_SRC_DIV_SHIFT;
  1999. p_src = (con & CLK_UART_SRC_SEL_MASK) >> CLK_UART_SRC_SEL_SHIFT;
  2000. if (p_src == CLK_UART_SRC_SEL_GPLL)
  2001. p_rate = priv->gpll_hz;
  2002. else if (p_src == CLK_UART_SRC_SEL_CPLL)
  2003. p_rate = priv->cpll_hz;
  2004. else
  2005. p_rate = 480000000;
  2006. if (src == CLK_UART_SEL_SRC) {
  2007. return DIV_TO_RATE(p_rate, div);
  2008. } else if (src == CLK_UART_SEL_FRAC) {
  2009. fracdiv = readl(&cru->clksel_con[reg + 1]);
  2010. n = fracdiv & CLK_UART_FRAC_NUMERATOR_MASK;
  2011. n >>= CLK_UART_FRAC_NUMERATOR_SHIFT;
  2012. m = fracdiv & CLK_UART_FRAC_DENOMINATOR_MASK;
  2013. m >>= CLK_UART_FRAC_DENOMINATOR_SHIFT;
  2014. return DIV_TO_RATE(p_rate, div) * n / m;
  2015. } else {
  2016. return OSC_HZ;
  2017. }
  2018. }
  2019. static ulong rk3568_uart_set_rate(struct rk3568_clk_priv *priv,
  2020. ulong clk_id, ulong rate)
  2021. {
  2022. struct rk3568_cru *cru = priv->cru;
  2023. u32 reg, clk_src, uart_src, div;
  2024. unsigned long m = 0, n = 0, val;
  2025. if (priv->gpll_hz % rate == 0) {
  2026. clk_src = CLK_UART_SRC_SEL_GPLL;
  2027. uart_src = CLK_UART_SEL_SRC;
  2028. div = DIV_ROUND_UP(priv->gpll_hz, rate);
  2029. } else if (priv->cpll_hz % rate == 0) {
  2030. clk_src = CLK_UART_SRC_SEL_CPLL;
  2031. uart_src = CLK_UART_SEL_SRC;
  2032. div = DIV_ROUND_UP(priv->gpll_hz, rate);
  2033. } else if (rate == OSC_HZ) {
  2034. clk_src = CLK_UART_SRC_SEL_GPLL;
  2035. uart_src = CLK_UART_SEL_XIN24M;
  2036. div = 2;
  2037. } else {
  2038. clk_src = CLK_UART_SRC_SEL_GPLL;
  2039. uart_src = CLK_UART_SEL_FRAC;
  2040. div = 2;
  2041. rational_best_approximation(rate, priv->gpll_hz / div,
  2042. GENMASK(16 - 1, 0),
  2043. GENMASK(16 - 1, 0),
  2044. &m, &n);
  2045. }
  2046. switch (clk_id) {
  2047. case SCLK_UART1:
  2048. reg = 52;
  2049. break;
  2050. case SCLK_UART2:
  2051. reg = 54;
  2052. break;
  2053. case SCLK_UART3:
  2054. reg = 56;
  2055. break;
  2056. case SCLK_UART4:
  2057. reg = 58;
  2058. break;
  2059. case SCLK_UART5:
  2060. reg = 60;
  2061. break;
  2062. case SCLK_UART6:
  2063. reg = 62;
  2064. break;
  2065. case SCLK_UART7:
  2066. reg = 64;
  2067. break;
  2068. case SCLK_UART8:
  2069. reg = 66;
  2070. break;
  2071. case SCLK_UART9:
  2072. reg = 68;
  2073. break;
  2074. default:
  2075. return -ENOENT;
  2076. }
  2077. rk_clrsetreg(&cru->clksel_con[reg],
  2078. CLK_UART_SEL_MASK | CLK_UART_SRC_SEL_MASK |
  2079. CLK_UART_SRC_DIV_MASK,
  2080. (clk_src << CLK_UART_SRC_SEL_SHIFT) |
  2081. (uart_src << CLK_UART_SEL_SHIFT) |
  2082. ((div - 1) << CLK_UART_SRC_DIV_SHIFT));
  2083. if (m && n) {
  2084. val = m << CLK_UART_FRAC_NUMERATOR_SHIFT | n;
  2085. writel(val, &cru->clksel_con[reg + 1]);
  2086. }
  2087. return rk3568_uart_get_rate(priv, clk_id);
  2088. }
  2089. #endif
  2090. static ulong rk3568_clk_get_rate(struct clk *clk)
  2091. {
  2092. struct rk3568_clk_priv *priv = dev_get_priv(clk->dev);
  2093. ulong rate = 0;
  2094. if (!priv->gpll_hz) {
  2095. printf("%s gpll=%lu\n", __func__, priv->gpll_hz);
  2096. return -ENOENT;
  2097. }
  2098. switch (clk->id) {
  2099. case PLL_APLL:
  2100. case ARMCLK:
  2101. rate = rockchip_pll_get_rate(&rk3568_pll_clks[APLL], priv->cru,
  2102. APLL);
  2103. break;
  2104. case PLL_CPLL:
  2105. rate = rockchip_pll_get_rate(&rk3568_pll_clks[CPLL], priv->cru,
  2106. CPLL);
  2107. break;
  2108. case PLL_GPLL:
  2109. rate = rockchip_pll_get_rate(&rk3568_pll_clks[GPLL], priv->cru,
  2110. GPLL);
  2111. break;
  2112. case PLL_NPLL:
  2113. rate = rockchip_pll_get_rate(&rk3568_pll_clks[NPLL], priv->cru,
  2114. NPLL);
  2115. break;
  2116. case PLL_VPLL:
  2117. rate = rockchip_pll_get_rate(&rk3568_pll_clks[VPLL], priv->cru,
  2118. VPLL);
  2119. break;
  2120. case PLL_DPLL:
  2121. rate = rockchip_pll_get_rate(&rk3568_pll_clks[DPLL], priv->cru,
  2122. DPLL);
  2123. break;
  2124. case ACLK_BUS:
  2125. case PCLK_BUS:
  2126. case PCLK_WDT_NS:
  2127. rate = rk3568_bus_get_clk(priv, clk->id);
  2128. break;
  2129. case ACLK_PERIMID:
  2130. case HCLK_PERIMID:
  2131. rate = rk3568_perimid_get_clk(priv, clk->id);
  2132. break;
  2133. case ACLK_TOP_HIGH:
  2134. case ACLK_TOP_LOW:
  2135. case HCLK_TOP:
  2136. case PCLK_TOP:
  2137. rate = rk3568_top_get_clk(priv, clk->id);
  2138. break;
  2139. case CLK_I2C1:
  2140. case CLK_I2C2:
  2141. case CLK_I2C3:
  2142. case CLK_I2C4:
  2143. case CLK_I2C5:
  2144. rate = rk3568_i2c_get_clk(priv, clk->id);
  2145. break;
  2146. case CLK_SPI0:
  2147. case CLK_SPI1:
  2148. case CLK_SPI2:
  2149. case CLK_SPI3:
  2150. rate = rk3568_spi_get_clk(priv, clk->id);
  2151. break;
  2152. case CLK_PWM1:
  2153. case CLK_PWM2:
  2154. case CLK_PWM3:
  2155. rate = rk3568_pwm_get_clk(priv, clk->id);
  2156. break;
  2157. case CLK_SARADC:
  2158. case CLK_TSADC_TSEN:
  2159. case CLK_TSADC:
  2160. rate = rk3568_adc_get_clk(priv, clk->id);
  2161. break;
  2162. case HCLK_SDMMC0:
  2163. case CLK_SDMMC0:
  2164. case CLK_SDMMC1:
  2165. case CLK_SDMMC2:
  2166. rate = rk3568_sdmmc_get_clk(priv, clk->id);
  2167. break;
  2168. case SCLK_SFC:
  2169. rate = rk3568_sfc_get_clk(priv);
  2170. break;
  2171. case NCLK_NANDC:
  2172. rate = rk3568_nand_get_clk(priv);
  2173. break;
  2174. case CCLK_EMMC:
  2175. rate = rk3568_emmc_get_clk(priv);
  2176. break;
  2177. case BCLK_EMMC:
  2178. rate = rk3568_emmc_get_bclk(priv);
  2179. break;
  2180. #ifndef CONFIG_SPL_BUILD
  2181. case ACLK_VOP:
  2182. rate = rk3568_aclk_vop_get_clk(priv);
  2183. break;
  2184. case DCLK_VOP0:
  2185. case DCLK_VOP1:
  2186. case DCLK_VOP2:
  2187. rate = rk3568_dclk_vop_get_clk(priv, clk->id);
  2188. break;
  2189. case SCLK_GMAC0:
  2190. case CLK_MAC0_2TOP:
  2191. case CLK_MAC0_REFOUT:
  2192. rate = rk3568_gmac_src_get_clk(priv, 0);
  2193. break;
  2194. case CLK_MAC0_OUT:
  2195. rate = rk3568_gmac_out_get_clk(priv, 0);
  2196. break;
  2197. case CLK_GMAC0_PTP_REF:
  2198. rate = rk3568_gmac_ptp_ref_get_clk(priv, 0);
  2199. break;
  2200. case SCLK_GMAC1:
  2201. case CLK_MAC1_2TOP:
  2202. case CLK_MAC1_REFOUT:
  2203. rate = rk3568_gmac_src_get_clk(priv, 1);
  2204. break;
  2205. case CLK_MAC1_OUT:
  2206. rate = rk3568_gmac_out_get_clk(priv, 1);
  2207. break;
  2208. case CLK_GMAC1_PTP_REF:
  2209. rate = rk3568_gmac_ptp_ref_get_clk(priv, 1);
  2210. break;
  2211. case DCLK_EBC:
  2212. rate = rk3568_ebc_get_clk(priv);
  2213. break;
  2214. case ACLK_RKVDEC_PRE:
  2215. case ACLK_RKVDEC:
  2216. case CLK_RKVDEC_CORE:
  2217. rate = rk3568_rkvdec_get_clk(priv, clk->id);
  2218. break;
  2219. case TCLK_WDT_NS:
  2220. rate = OSC_HZ;
  2221. break;
  2222. case SCLK_UART1:
  2223. case SCLK_UART2:
  2224. case SCLK_UART3:
  2225. case SCLK_UART4:
  2226. case SCLK_UART5:
  2227. case SCLK_UART6:
  2228. case SCLK_UART7:
  2229. case SCLK_UART8:
  2230. case SCLK_UART9:
  2231. rate = rk3568_uart_get_rate(priv, clk->id);
  2232. break;
  2233. #endif
  2234. case ACLK_SECURE_FLASH:
  2235. case ACLK_CRYPTO_NS:
  2236. case HCLK_SECURE_FLASH:
  2237. case HCLK_CRYPTO_NS:
  2238. case CLK_CRYPTO_NS_RNG:
  2239. case CLK_CRYPTO_NS_CORE:
  2240. case CLK_CRYPTO_NS_PKA:
  2241. rate = rk3568_crypto_get_rate(priv, clk->id);
  2242. break;
  2243. case CPLL_500M:
  2244. case CPLL_333M:
  2245. case CPLL_250M:
  2246. case CPLL_125M:
  2247. case CPLL_100M:
  2248. case CPLL_62P5M:
  2249. case CPLL_50M:
  2250. case CPLL_25M:
  2251. rate = rk3568_cpll_div_get_rate(priv, clk->id);
  2252. break;
  2253. default:
  2254. return -ENOENT;
  2255. }
  2256. return rate;
  2257. };
  2258. static ulong rk3568_clk_set_rate(struct clk *clk, ulong rate)
  2259. {
  2260. struct rk3568_clk_priv *priv = dev_get_priv(clk->dev);
  2261. ulong ret = 0;
  2262. if (!priv->gpll_hz) {
  2263. printf("%s gpll=%lu\n", __func__, priv->gpll_hz);
  2264. return -ENOENT;
  2265. }
  2266. switch (clk->id) {
  2267. case PLL_APLL:
  2268. case ARMCLK:
  2269. if (priv->armclk_hz)
  2270. rk3568_armclk_set_clk(priv, rate);
  2271. priv->armclk_hz = rate;
  2272. break;
  2273. case PLL_CPLL:
  2274. ret = rockchip_pll_set_rate(&rk3568_pll_clks[CPLL], priv->cru,
  2275. CPLL, rate);
  2276. priv->cpll_hz = rockchip_pll_get_rate(&rk3568_pll_clks[CPLL],
  2277. priv->cru, CPLL);
  2278. break;
  2279. case PLL_GPLL:
  2280. ret = rockchip_pll_set_rate(&rk3568_pll_clks[GPLL], priv->cru,
  2281. GPLL, rate);
  2282. priv->gpll_hz = rockchip_pll_get_rate(&rk3568_pll_clks[GPLL],
  2283. priv->cru, GPLL);
  2284. break;
  2285. case PLL_NPLL:
  2286. ret = rockchip_pll_set_rate(&rk3568_pll_clks[NPLL], priv->cru,
  2287. NPLL, rate);
  2288. break;
  2289. case PLL_VPLL:
  2290. ret = rockchip_pll_set_rate(&rk3568_pll_clks[VPLL], priv->cru,
  2291. VPLL, rate);
  2292. priv->vpll_hz = rockchip_pll_get_rate(&rk3568_pll_clks[VPLL],
  2293. priv->cru,
  2294. VPLL);
  2295. break;
  2296. case ACLK_BUS:
  2297. case PCLK_BUS:
  2298. case PCLK_WDT_NS:
  2299. ret = rk3568_bus_set_clk(priv, clk->id, rate);
  2300. break;
  2301. case ACLK_PERIMID:
  2302. case HCLK_PERIMID:
  2303. ret = rk3568_perimid_set_clk(priv, clk->id, rate);
  2304. break;
  2305. case ACLK_TOP_HIGH:
  2306. case ACLK_TOP_LOW:
  2307. case HCLK_TOP:
  2308. case PCLK_TOP:
  2309. ret = rk3568_top_set_clk(priv, clk->id, rate);
  2310. break;
  2311. case CLK_I2C1:
  2312. case CLK_I2C2:
  2313. case CLK_I2C3:
  2314. case CLK_I2C4:
  2315. case CLK_I2C5:
  2316. ret = rk3568_i2c_set_clk(priv, clk->id, rate);
  2317. break;
  2318. case CLK_SPI0:
  2319. case CLK_SPI1:
  2320. case CLK_SPI2:
  2321. case CLK_SPI3:
  2322. ret = rk3568_spi_set_clk(priv, clk->id, rate);
  2323. break;
  2324. case CLK_PWM1:
  2325. case CLK_PWM2:
  2326. case CLK_PWM3:
  2327. ret = rk3568_pwm_set_clk(priv, clk->id, rate);
  2328. break;
  2329. case CLK_SARADC:
  2330. case CLK_TSADC_TSEN:
  2331. case CLK_TSADC:
  2332. ret = rk3568_adc_set_clk(priv, clk->id, rate);
  2333. break;
  2334. case HCLK_SDMMC0:
  2335. case CLK_SDMMC0:
  2336. case CLK_SDMMC1:
  2337. case CLK_SDMMC2:
  2338. ret = rk3568_sdmmc_set_clk(priv, clk->id, rate);
  2339. break;
  2340. case SCLK_SFC:
  2341. ret = rk3568_sfc_set_clk(priv, rate);
  2342. break;
  2343. case NCLK_NANDC:
  2344. ret = rk3568_nand_set_clk(priv, rate);
  2345. break;
  2346. case CCLK_EMMC:
  2347. ret = rk3568_emmc_set_clk(priv, rate);
  2348. break;
  2349. case BCLK_EMMC:
  2350. ret = rk3568_emmc_set_bclk(priv, rate);
  2351. break;
  2352. #ifndef CONFIG_SPL_BUILD
  2353. case ACLK_VOP:
  2354. ret = rk3568_aclk_vop_set_clk(priv, rate);
  2355. break;
  2356. case DCLK_VOP0:
  2357. case DCLK_VOP1:
  2358. case DCLK_VOP2:
  2359. ret = rk3568_dclk_vop_set_clk(priv, clk->id, rate);
  2360. break;
  2361. case SCLK_GMAC0:
  2362. case CLK_MAC0_2TOP:
  2363. case CLK_MAC0_REFOUT:
  2364. ret = rk3568_gmac_src_set_clk(priv, 0, rate);
  2365. break;
  2366. case CLK_MAC0_OUT:
  2367. ret = rk3568_gmac_out_set_clk(priv, 0, rate);
  2368. break;
  2369. case SCLK_GMAC0_RX_TX:
  2370. ret = rk3568_gmac_tx_rx_set_clk(priv, 0, rate);
  2371. break;
  2372. case CLK_GMAC0_PTP_REF:
  2373. ret = rk3568_gmac_ptp_ref_set_clk(priv, 0, rate);
  2374. break;
  2375. case SCLK_GMAC1:
  2376. case CLK_MAC1_2TOP:
  2377. case CLK_MAC1_REFOUT:
  2378. ret = rk3568_gmac_src_set_clk(priv, 1, rate);
  2379. break;
  2380. case CLK_MAC1_OUT:
  2381. ret = rk3568_gmac_out_set_clk(priv, 1, rate);
  2382. break;
  2383. case SCLK_GMAC1_RX_TX:
  2384. ret = rk3568_gmac_tx_rx_set_clk(priv, 1, rate);
  2385. break;
  2386. case CLK_GMAC1_PTP_REF:
  2387. ret = rk3568_gmac_ptp_ref_set_clk(priv, 1, rate);
  2388. break;
  2389. case DCLK_EBC:
  2390. ret = rk3568_ebc_set_clk(priv, rate);
  2391. break;
  2392. case ACLK_RKVDEC_PRE:
  2393. case ACLK_RKVDEC:
  2394. case CLK_RKVDEC_CORE:
  2395. ret = rk3568_rkvdec_set_clk(priv, clk->id, rate);
  2396. break;
  2397. case TCLK_WDT_NS:
  2398. ret = OSC_HZ;
  2399. break;
  2400. case SCLK_UART1:
  2401. case SCLK_UART2:
  2402. case SCLK_UART3:
  2403. case SCLK_UART4:
  2404. case SCLK_UART5:
  2405. case SCLK_UART6:
  2406. case SCLK_UART7:
  2407. case SCLK_UART8:
  2408. case SCLK_UART9:
  2409. ret = rk3568_uart_set_rate(priv, clk->id, rate);
  2410. break;
  2411. #endif
  2412. case ACLK_SECURE_FLASH:
  2413. case ACLK_CRYPTO_NS:
  2414. case HCLK_SECURE_FLASH:
  2415. case HCLK_CRYPTO_NS:
  2416. case CLK_CRYPTO_NS_RNG:
  2417. case CLK_CRYPTO_NS_CORE:
  2418. case CLK_CRYPTO_NS_PKA:
  2419. ret = rk3568_crypto_set_rate(priv, clk->id, rate);
  2420. break;
  2421. case CPLL_500M:
  2422. case CPLL_333M:
  2423. case CPLL_250M:
  2424. case CPLL_125M:
  2425. case CPLL_100M:
  2426. case CPLL_62P5M:
  2427. case CPLL_50M:
  2428. case CPLL_25M:
  2429. ret = rk3568_cpll_div_set_rate(priv, clk->id, rate);
  2430. break;
  2431. default:
  2432. return -ENOENT;
  2433. }
  2434. return ret;
  2435. };
  2436. #if (IS_ENABLED(OF_CONTROL)) || (!IS_ENABLED(OF_PLATDATA))
  2437. static int rk3568_gmac0_src_set_parent(struct clk *clk, struct clk *parent)
  2438. {
  2439. struct rk3568_clk_priv *priv = dev_get_priv(clk->dev);
  2440. struct rk3568_cru *cru = priv->cru;
  2441. if (parent->id == CLK_MAC0_2TOP)
  2442. rk_clrsetreg(&cru->clksel_con[31],
  2443. RMII0_EXTCLK_SEL_MASK,
  2444. RMII0_EXTCLK_SEL_MAC0_TOP <<
  2445. RMII0_EXTCLK_SEL_SHIFT);
  2446. else
  2447. rk_clrsetreg(&cru->clksel_con[31],
  2448. RMII0_EXTCLK_SEL_MASK,
  2449. RMII0_EXTCLK_SEL_IO << RMII0_EXTCLK_SEL_SHIFT);
  2450. return 0;
  2451. }
  2452. static int rk3568_gmac1_src_set_parent(struct clk *clk, struct clk *parent)
  2453. {
  2454. struct rk3568_clk_priv *priv = dev_get_priv(clk->dev);
  2455. struct rk3568_cru *cru = priv->cru;
  2456. if (parent->id == CLK_MAC1_2TOP)
  2457. rk_clrsetreg(&cru->clksel_con[33],
  2458. RMII0_EXTCLK_SEL_MASK,
  2459. RMII0_EXTCLK_SEL_MAC0_TOP <<
  2460. RMII0_EXTCLK_SEL_SHIFT);
  2461. else
  2462. rk_clrsetreg(&cru->clksel_con[33],
  2463. RMII0_EXTCLK_SEL_MASK,
  2464. RMII0_EXTCLK_SEL_IO << RMII0_EXTCLK_SEL_SHIFT);
  2465. return 0;
  2466. }
  2467. static int rk3568_gmac0_tx_rx_set_parent(struct clk *clk, struct clk *parent)
  2468. {
  2469. struct rk3568_clk_priv *priv = dev_get_priv(clk->dev);
  2470. struct rk3568_cru *cru = priv->cru;
  2471. if (parent->id == SCLK_GMAC0_RGMII_SPEED)
  2472. rk_clrsetreg(&cru->clksel_con[31],
  2473. RMII0_MODE_MASK,
  2474. RMII0_MODE_SEL_RGMII << RMII0_MODE_SHIFT);
  2475. else if (parent->id == SCLK_GMAC0_RMII_SPEED)
  2476. rk_clrsetreg(&cru->clksel_con[31],
  2477. RMII0_MODE_MASK,
  2478. RMII0_MODE_SEL_RMII << RMII0_MODE_SHIFT);
  2479. else
  2480. rk_clrsetreg(&cru->clksel_con[31],
  2481. RMII0_MODE_MASK,
  2482. RMII0_MODE_SEL_GMII << RMII0_MODE_SHIFT);
  2483. return 0;
  2484. }
  2485. static int rk3568_gmac1_tx_rx_set_parent(struct clk *clk, struct clk *parent)
  2486. {
  2487. struct rk3568_clk_priv *priv = dev_get_priv(clk->dev);
  2488. struct rk3568_cru *cru = priv->cru;
  2489. if (parent->id == SCLK_GMAC1_RGMII_SPEED)
  2490. rk_clrsetreg(&cru->clksel_con[33],
  2491. RMII0_MODE_MASK,
  2492. RMII0_MODE_SEL_RGMII << RMII0_MODE_SHIFT);
  2493. else if (parent->id == SCLK_GMAC1_RMII_SPEED)
  2494. rk_clrsetreg(&cru->clksel_con[33],
  2495. RMII0_MODE_MASK,
  2496. RMII0_MODE_SEL_RMII << RMII0_MODE_SHIFT);
  2497. else
  2498. rk_clrsetreg(&cru->clksel_con[33],
  2499. RMII0_MODE_MASK,
  2500. RMII0_MODE_SEL_GMII << RMII0_MODE_SHIFT);
  2501. return 0;
  2502. }
  2503. static int rk3568_dclk_vop_set_parent(struct clk *clk, struct clk *parent)
  2504. {
  2505. struct rk3568_clk_priv *priv = dev_get_priv(clk->dev);
  2506. struct rk3568_cru *cru = priv->cru;
  2507. u32 con_id;
  2508. switch (clk->id) {
  2509. case DCLK_VOP0:
  2510. con_id = 39;
  2511. break;
  2512. case DCLK_VOP1:
  2513. con_id = 40;
  2514. break;
  2515. case DCLK_VOP2:
  2516. con_id = 41;
  2517. break;
  2518. default:
  2519. return -EINVAL;
  2520. }
  2521. if (parent->id == PLL_VPLL) {
  2522. rk_clrsetreg(&cru->clksel_con[con_id], DCLK0_VOP_SEL_MASK,
  2523. DCLK_VOP_SEL_VPLL << DCLK0_VOP_SEL_SHIFT);
  2524. } else {
  2525. rk_clrsetreg(&cru->clksel_con[con_id], DCLK0_VOP_SEL_MASK,
  2526. DCLK_VOP_SEL_HPLL << DCLK0_VOP_SEL_SHIFT);
  2527. }
  2528. return 0;
  2529. }
  2530. static int rk3568_rkvdec_set_parent(struct clk *clk, struct clk *parent)
  2531. {
  2532. struct rk3568_clk_priv *priv = dev_get_priv(clk->dev);
  2533. struct rk3568_cru *cru = priv->cru;
  2534. u32 con_id, mask, shift;
  2535. switch (clk->id) {
  2536. case ACLK_RKVDEC_PRE:
  2537. con_id = 47;
  2538. mask = ACLK_RKVDEC_SEL_MASK;
  2539. shift = ACLK_RKVDEC_SEL_SHIFT;
  2540. break;
  2541. case CLK_RKVDEC_CORE:
  2542. con_id = 49;
  2543. mask = CLK_RKVDEC_CORE_SEL_MASK;
  2544. shift = CLK_RKVDEC_CORE_SEL_SHIFT;
  2545. break;
  2546. default:
  2547. return -EINVAL;
  2548. }
  2549. if (parent->id == PLL_CPLL) {
  2550. rk_clrsetreg(&cru->clksel_con[con_id], mask,
  2551. ACLK_RKVDEC_SEL_CPLL << shift);
  2552. } else {
  2553. rk_clrsetreg(&cru->clksel_con[con_id], mask,
  2554. ACLK_RKVDEC_SEL_GPLL << shift);
  2555. }
  2556. return 0;
  2557. }
  2558. static int rk3568_clk_set_parent(struct clk *clk, struct clk *parent)
  2559. {
  2560. switch (clk->id) {
  2561. case SCLK_GMAC0:
  2562. return rk3568_gmac0_src_set_parent(clk, parent);
  2563. case SCLK_GMAC1:
  2564. return rk3568_gmac1_src_set_parent(clk, parent);
  2565. case SCLK_GMAC0_RX_TX:
  2566. return rk3568_gmac0_tx_rx_set_parent(clk, parent);
  2567. case SCLK_GMAC1_RX_TX:
  2568. return rk3568_gmac1_tx_rx_set_parent(clk, parent);
  2569. case DCLK_VOP0:
  2570. case DCLK_VOP1:
  2571. case DCLK_VOP2:
  2572. return rk3568_dclk_vop_set_parent(clk, parent);
  2573. case ACLK_RKVDEC_PRE:
  2574. case CLK_RKVDEC_CORE:
  2575. return rk3568_rkvdec_set_parent(clk, parent);
  2576. default:
  2577. return -ENOENT;
  2578. }
  2579. return 0;
  2580. }
  2581. #endif
  2582. static struct clk_ops rk3568_clk_ops = {
  2583. .get_rate = rk3568_clk_get_rate,
  2584. .set_rate = rk3568_clk_set_rate,
  2585. #if (IS_ENABLED(OF_CONTROL)) || (!IS_ENABLED(OF_PLATDATA))
  2586. .set_parent = rk3568_clk_set_parent,
  2587. #endif
  2588. };
  2589. static void rk3568_clk_init(struct rk3568_clk_priv *priv)
  2590. {
  2591. int ret;
  2592. priv->sync_kernel = false;
  2593. if (!priv->armclk_enter_hz) {
  2594. priv->armclk_enter_hz =
  2595. rockchip_pll_get_rate(&rk3568_pll_clks[APLL],
  2596. priv->cru, APLL);
  2597. priv->armclk_init_hz = priv->armclk_enter_hz;
  2598. }
  2599. if (priv->armclk_init_hz != APLL_HZ) {
  2600. ret = rk3568_armclk_set_clk(priv, APLL_HZ);
  2601. if (!ret)
  2602. priv->armclk_init_hz = APLL_HZ;
  2603. }
  2604. if (priv->cpll_hz != CPLL_HZ) {
  2605. ret = rockchip_pll_set_rate(&rk3568_pll_clks[CPLL], priv->cru,
  2606. CPLL, CPLL_HZ);
  2607. if (!ret)
  2608. priv->cpll_hz = CPLL_HZ;
  2609. }
  2610. if (priv->gpll_hz != GPLL_HZ) {
  2611. ret = rockchip_pll_set_rate(&rk3568_pll_clks[GPLL], priv->cru,
  2612. GPLL, GPLL_HZ);
  2613. if (!ret)
  2614. priv->gpll_hz = GPLL_HZ;
  2615. }
  2616. #ifdef CONFIG_SPL_BUILD
  2617. ret = rk3568_bus_set_clk(priv, ACLK_BUS, 150000000);
  2618. if (ret < 0)
  2619. printf("Fail to set the ACLK_BUS clock.\n");
  2620. #endif
  2621. priv->ppll_hz = rk3568_pmu_pll_get_rate(priv, PPLL);
  2622. priv->hpll_hz = rk3568_pmu_pll_get_rate(priv, HPLL);
  2623. }
  2624. static int rk3568_clk_probe(struct udevice *dev)
  2625. {
  2626. struct rk3568_clk_priv *priv = dev_get_priv(dev);
  2627. int ret;
  2628. priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  2629. if (IS_ERR(priv->grf))
  2630. return PTR_ERR(priv->grf);
  2631. rk3568_clk_init(priv);
  2632. /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */
  2633. ret = clk_set_defaults(dev, 1);
  2634. if (ret)
  2635. debug("%s clk_set_defaults failed %d\n", __func__, ret);
  2636. else
  2637. priv->sync_kernel = true;
  2638. return 0;
  2639. }
  2640. static int rk3568_clk_ofdata_to_platdata(struct udevice *dev)
  2641. {
  2642. struct rk3568_clk_priv *priv = dev_get_priv(dev);
  2643. priv->cru = dev_read_addr_ptr(dev);
  2644. return 0;
  2645. }
  2646. static int rk3568_clk_bind(struct udevice *dev)
  2647. {
  2648. int ret;
  2649. struct udevice *sys_child;
  2650. struct sysreset_reg *priv;
  2651. /* The reset driver does not have a device node, so bind it here */
  2652. ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
  2653. &sys_child);
  2654. if (ret) {
  2655. debug("Warning: No sysreset driver: ret=%d\n", ret);
  2656. } else {
  2657. priv = malloc(sizeof(struct sysreset_reg));
  2658. priv->glb_srst_fst_value = offsetof(struct rk3568_cru,
  2659. glb_srst_fst);
  2660. priv->glb_srst_snd_value = offsetof(struct rk3568_cru,
  2661. glb_srsr_snd);
  2662. }
  2663. #if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
  2664. ret = offsetof(struct rk3568_cru, softrst_con[0]);
  2665. ret = rockchip_reset_bind(dev, ret, 30);
  2666. if (ret)
  2667. debug("Warning: software reset driver bind faile\n");
  2668. #endif
  2669. return 0;
  2670. }
  2671. static const struct udevice_id rk3568_clk_ids[] = {
  2672. { .compatible = "rockchip,rk3568-cru" },
  2673. { }
  2674. };
  2675. U_BOOT_DRIVER(rockchip_rk3568_cru) = {
  2676. .name = "rockchip_rk3568_cru",
  2677. .id = UCLASS_CLK,
  2678. .of_match = rk3568_clk_ids,
  2679. .priv_auto = sizeof(struct rk3568_clk_priv),
  2680. .of_to_plat = rk3568_clk_ofdata_to_platdata,
  2681. .ops = &rk3568_clk_ops,
  2682. .bind = rk3568_clk_bind,
  2683. .probe = rk3568_clk_probe,
  2684. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  2685. .plat_auto = sizeof(struct rk3568_clk_plat),
  2686. #endif
  2687. };