clk_rk3368.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * (C) Copyright 2017 Rockchip Electronics Co., Ltd
  4. * Author: Andy Yan <andy.yan@rock-chips.com>
  5. * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
  6. */
  7. #include <common.h>
  8. #include <clk-uclass.h>
  9. #include <dm.h>
  10. #include <dt-structs.h>
  11. #include <errno.h>
  12. #include <log.h>
  13. #include <malloc.h>
  14. #include <mapmem.h>
  15. #include <syscon.h>
  16. #include <bitfield.h>
  17. #include <asm/arch-rockchip/clock.h>
  18. #include <asm/arch-rockchip/cru_rk3368.h>
  19. #include <asm/arch-rockchip/hardware.h>
  20. #include <asm/io.h>
  21. #include <dm/device-internal.h>
  22. #include <dm/lists.h>
  23. #include <dt-bindings/clock/rk3368-cru.h>
  24. #include <linux/delay.h>
  25. #include <linux/stringify.h>
  26. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  27. struct rk3368_clk_plat {
  28. struct dtd_rockchip_rk3368_cru dtd;
  29. };
  30. #endif
  31. struct pll_div {
  32. u32 nr;
  33. u32 nf;
  34. u32 no;
  35. };
  36. #define OSC_HZ (24 * 1000 * 1000)
  37. #define APLL_L_HZ (800 * 1000 * 1000)
  38. #define APLL_B_HZ (816 * 1000 * 1000)
  39. #define GPLL_HZ (576 * 1000 * 1000)
  40. #define CPLL_HZ (400 * 1000 * 1000)
  41. #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
  42. #define PLL_DIVISORS(hz, _nr, _no) { \
  43. .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no}; \
  44. _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
  45. (_nr * _no) == hz, #hz "Hz cannot be hit with PLL " \
  46. "divisors on line " __stringify(__LINE__));
  47. #if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
  48. static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2);
  49. static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2);
  50. #if !defined(CONFIG_TPL_BUILD)
  51. static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 2);
  52. static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6);
  53. #endif
  54. #endif
  55. static ulong rk3368_clk_get_rate(struct clk *clk);
  56. /* Get pll rate by id */
  57. static uint32_t rkclk_pll_get_rate(struct rk3368_cru *cru,
  58. enum rk3368_pll_id pll_id)
  59. {
  60. uint32_t nr, no, nf;
  61. uint32_t con;
  62. struct rk3368_pll *pll = &cru->pll[pll_id];
  63. con = readl(&pll->con3);
  64. switch ((con & PLL_MODE_MASK) >> PLL_MODE_SHIFT) {
  65. case PLL_MODE_SLOW:
  66. return OSC_HZ;
  67. case PLL_MODE_NORMAL:
  68. con = readl(&pll->con0);
  69. no = ((con & PLL_OD_MASK) >> PLL_OD_SHIFT) + 1;
  70. nr = ((con & PLL_NR_MASK) >> PLL_NR_SHIFT) + 1;
  71. con = readl(&pll->con1);
  72. nf = ((con & PLL_NF_MASK) >> PLL_NF_SHIFT) + 1;
  73. return (24 * nf / (nr * no)) * 1000000;
  74. case PLL_MODE_DEEP_SLOW:
  75. default:
  76. return 32768;
  77. }
  78. }
  79. #if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
  80. static int rkclk_set_pll(struct rk3368_cru *cru, enum rk3368_pll_id pll_id,
  81. const struct pll_div *div)
  82. {
  83. struct rk3368_pll *pll = &cru->pll[pll_id];
  84. /* All PLLs have same VCO and output frequency range restrictions*/
  85. uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000;
  86. uint output_hz = vco_hz / div->no;
  87. debug("PLL at %p: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n",
  88. pll, div->nf, div->nr, div->no, vco_hz, output_hz);
  89. /* enter slow mode and reset pll */
  90. rk_clrsetreg(&pll->con3, PLL_MODE_MASK | PLL_RESET_MASK,
  91. PLL_RESET << PLL_RESET_SHIFT);
  92. rk_clrsetreg(&pll->con0, PLL_NR_MASK | PLL_OD_MASK,
  93. ((div->nr - 1) << PLL_NR_SHIFT) |
  94. ((div->no - 1) << PLL_OD_SHIFT));
  95. writel((div->nf - 1) << PLL_NF_SHIFT, &pll->con1);
  96. /*
  97. * BWADJ should be set to NF / 2 to ensure the nominal bandwidth.
  98. * Compare the RK3368 TRM, section "3.6.4 PLL Bandwidth Adjustment".
  99. */
  100. clrsetbits_le32(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1);
  101. udelay(10);
  102. /* return from reset */
  103. rk_clrreg(&pll->con3, PLL_RESET_MASK);
  104. /* waiting for pll lock */
  105. while (!(readl(&pll->con1) & PLL_LOCK_STA))
  106. udelay(1);
  107. rk_clrsetreg(&pll->con3, PLL_MODE_MASK,
  108. PLL_MODE_NORMAL << PLL_MODE_SHIFT);
  109. return 0;
  110. }
  111. #endif
  112. #if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
  113. static void rkclk_init(struct rk3368_cru *cru)
  114. {
  115. u32 apllb, aplll, dpll, cpll, gpll;
  116. rkclk_set_pll(cru, APLLB, &apll_b_init_cfg);
  117. rkclk_set_pll(cru, APLLL, &apll_l_init_cfg);
  118. #if !defined(CONFIG_TPL_BUILD)
  119. /*
  120. * If we plan to return to the boot ROM, we can't increase the
  121. * GPLL rate from the SPL stage.
  122. */
  123. rkclk_set_pll(cru, GPLL, &gpll_init_cfg);
  124. rkclk_set_pll(cru, CPLL, &cpll_init_cfg);
  125. #endif
  126. apllb = rkclk_pll_get_rate(cru, APLLB);
  127. aplll = rkclk_pll_get_rate(cru, APLLL);
  128. dpll = rkclk_pll_get_rate(cru, DPLL);
  129. cpll = rkclk_pll_get_rate(cru, CPLL);
  130. gpll = rkclk_pll_get_rate(cru, GPLL);
  131. debug("%s apllb(%d) apll(%d) dpll(%d) cpll(%d) gpll(%d)\n",
  132. __func__, apllb, aplll, dpll, cpll, gpll);
  133. }
  134. #endif
  135. #if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC_SUPPORT)
  136. static ulong rk3368_mmc_get_clk(struct rk3368_cru *cru, uint clk_id)
  137. {
  138. u32 div, con, con_id, rate;
  139. u32 pll_rate;
  140. switch (clk_id) {
  141. case HCLK_SDMMC:
  142. con_id = 50;
  143. break;
  144. case HCLK_EMMC:
  145. con_id = 51;
  146. break;
  147. case SCLK_SDIO0:
  148. con_id = 48;
  149. break;
  150. default:
  151. return -EINVAL;
  152. }
  153. con = readl(&cru->clksel_con[con_id]);
  154. switch (con & MMC_PLL_SEL_MASK) {
  155. case MMC_PLL_SEL_GPLL:
  156. pll_rate = rkclk_pll_get_rate(cru, GPLL);
  157. break;
  158. case MMC_PLL_SEL_24M:
  159. pll_rate = OSC_HZ;
  160. break;
  161. case MMC_PLL_SEL_CPLL:
  162. pll_rate = rkclk_pll_get_rate(cru, CPLL);
  163. break;
  164. case MMC_PLL_SEL_USBPHY_480M:
  165. default:
  166. return -EINVAL;
  167. }
  168. div = (con & MMC_CLK_DIV_MASK) >> MMC_CLK_DIV_SHIFT;
  169. rate = DIV_TO_RATE(pll_rate, div);
  170. debug("%s: raw rate %d (post-divide by 2)\n", __func__, rate);
  171. return rate >> 1;
  172. }
  173. static ulong rk3368_mmc_find_best_rate_and_parent(struct clk *clk,
  174. ulong rate,
  175. u32 *best_mux,
  176. u32 *best_div)
  177. {
  178. int i;
  179. ulong best_rate = 0;
  180. const ulong MHz = 1000000;
  181. const struct {
  182. u32 mux;
  183. ulong rate;
  184. } parents[] = {
  185. { .mux = MMC_PLL_SEL_CPLL, .rate = CPLL_HZ },
  186. { .mux = MMC_PLL_SEL_GPLL, .rate = GPLL_HZ },
  187. { .mux = MMC_PLL_SEL_24M, .rate = 24 * MHz }
  188. };
  189. debug("%s: target rate %ld\n", __func__, rate);
  190. for (i = 0; i < ARRAY_SIZE(parents); ++i) {
  191. /*
  192. * Find the largest rate no larger than the target-rate for
  193. * the current parent.
  194. */
  195. ulong parent_rate = parents[i].rate;
  196. u32 div = DIV_ROUND_UP(parent_rate, rate);
  197. u32 adj_div = div;
  198. ulong new_rate = parent_rate / adj_div;
  199. debug("%s: rate %ld, parent-mux %d, parent-rate %ld, div %d\n",
  200. __func__, rate, parents[i].mux, parents[i].rate, div);
  201. /* Skip, if not representable */
  202. if ((div - 1) > MMC_CLK_DIV_MASK)
  203. continue;
  204. /* Skip, if we already have a better (or equal) solution */
  205. if (new_rate <= best_rate)
  206. continue;
  207. /* This is our new best rate. */
  208. best_rate = new_rate;
  209. *best_mux = parents[i].mux;
  210. *best_div = div - 1;
  211. }
  212. debug("%s: best_mux = %x, best_div = %d, best_rate = %ld\n",
  213. __func__, *best_mux, *best_div, best_rate);
  214. return best_rate;
  215. }
  216. static ulong rk3368_mmc_set_clk(struct clk *clk, ulong rate)
  217. {
  218. struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
  219. struct rk3368_cru *cru = priv->cru;
  220. ulong clk_id = clk->id;
  221. u32 con_id, mux = 0, div = 0;
  222. /* Find the best parent and rate */
  223. rk3368_mmc_find_best_rate_and_parent(clk, rate << 1, &mux, &div);
  224. switch (clk_id) {
  225. case HCLK_SDMMC:
  226. con_id = 50;
  227. break;
  228. case HCLK_EMMC:
  229. con_id = 51;
  230. break;
  231. case SCLK_SDIO0:
  232. con_id = 48;
  233. break;
  234. default:
  235. return -EINVAL;
  236. }
  237. rk_clrsetreg(&cru->clksel_con[con_id],
  238. MMC_PLL_SEL_MASK | MMC_CLK_DIV_MASK,
  239. mux | div);
  240. return rk3368_mmc_get_clk(cru, clk_id);
  241. }
  242. #endif
  243. #if IS_ENABLED(CONFIG_TPL_BUILD)
  244. static ulong rk3368_ddr_set_clk(struct rk3368_cru *cru, ulong set_rate)
  245. {
  246. const struct pll_div *dpll_cfg = NULL;
  247. const ulong MHz = 1000000;
  248. /* Fout = ((Fin /NR) * NF )/ NO */
  249. static const struct pll_div dpll_1200 = PLL_DIVISORS(1200 * MHz, 1, 1);
  250. static const struct pll_div dpll_1332 = PLL_DIVISORS(1332 * MHz, 2, 1);
  251. static const struct pll_div dpll_1600 = PLL_DIVISORS(1600 * MHz, 3, 2);
  252. switch (set_rate) {
  253. case 1200*MHz:
  254. dpll_cfg = &dpll_1200;
  255. break;
  256. case 1332*MHz:
  257. dpll_cfg = &dpll_1332;
  258. break;
  259. case 1600*MHz:
  260. dpll_cfg = &dpll_1600;
  261. break;
  262. default:
  263. pr_err("Unsupported SDRAM frequency!,%ld\n", set_rate);
  264. }
  265. rkclk_set_pll(cru, DPLL, dpll_cfg);
  266. return set_rate;
  267. }
  268. #endif
  269. #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
  270. static ulong rk3368_gmac_set_clk(struct rk3368_cru *cru, ulong set_rate)
  271. {
  272. ulong ret;
  273. /*
  274. * The gmac clock can be derived either from an external clock
  275. * or can be generated from internally by a divider from SCLK_MAC.
  276. */
  277. if (readl(&cru->clksel_con[43]) & GMAC_MUX_SEL_EXTCLK) {
  278. /* An external clock will always generate the right rate... */
  279. ret = set_rate;
  280. } else {
  281. u32 con = readl(&cru->clksel_con[43]);
  282. ulong pll_rate;
  283. u8 div;
  284. if (((con >> GMAC_PLL_SHIFT) & GMAC_PLL_MASK) ==
  285. GMAC_PLL_SELECT_GENERAL)
  286. pll_rate = GPLL_HZ;
  287. else if (((con >> GMAC_PLL_SHIFT) & GMAC_PLL_MASK) ==
  288. GMAC_PLL_SELECT_CODEC)
  289. pll_rate = CPLL_HZ;
  290. else
  291. /* CPLL is not set */
  292. return -EPERM;
  293. div = DIV_ROUND_UP(pll_rate, set_rate) - 1;
  294. if (div <= 0x1f)
  295. rk_clrsetreg(&cru->clksel_con[43], GMAC_DIV_CON_MASK,
  296. div << GMAC_DIV_CON_SHIFT);
  297. else
  298. debug("Unsupported div for gmac:%d\n", div);
  299. return DIV_TO_RATE(pll_rate, div);
  300. }
  301. return ret;
  302. }
  303. #endif
  304. /*
  305. * RK3368 SPI clocks have a common divider-width (7 bits) and a single bit
  306. * to select either CPLL or GPLL as the clock-parent. The location within
  307. * the enclosing CLKSEL_CON (i.e. div_shift and sel_shift) are variable.
  308. */
  309. struct spi_clkreg {
  310. uint8_t reg; /* CLKSEL_CON[reg] register in CRU */
  311. uint8_t div_shift;
  312. uint8_t sel_shift;
  313. };
  314. /*
  315. * The entries are numbered relative to their offset from SCLK_SPI0.
  316. */
  317. static const struct spi_clkreg spi_clkregs[] = {
  318. [0] = { .reg = 45, .div_shift = 0, .sel_shift = 7, },
  319. [1] = { .reg = 45, .div_shift = 8, .sel_shift = 15, },
  320. [2] = { .reg = 46, .div_shift = 8, .sel_shift = 15, },
  321. };
  322. static inline u32 extract_bits(u32 val, unsigned width, unsigned shift)
  323. {
  324. return (val >> shift) & ((1 << width) - 1);
  325. }
  326. static ulong rk3368_spi_get_clk(struct rk3368_cru *cru, ulong clk_id)
  327. {
  328. const struct spi_clkreg *spiclk = NULL;
  329. u32 div, val;
  330. switch (clk_id) {
  331. case SCLK_SPI0 ... SCLK_SPI2:
  332. spiclk = &spi_clkregs[clk_id - SCLK_SPI0];
  333. break;
  334. default:
  335. pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
  336. return -EINVAL;
  337. }
  338. val = readl(&cru->clksel_con[spiclk->reg]);
  339. div = extract_bits(val, 7, spiclk->div_shift);
  340. debug("%s: div 0x%x\n", __func__, div);
  341. return DIV_TO_RATE(GPLL_HZ, div);
  342. }
  343. static ulong rk3368_spi_set_clk(struct rk3368_cru *cru, ulong clk_id, uint hz)
  344. {
  345. const struct spi_clkreg *spiclk = NULL;
  346. int src_clk_div;
  347. src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz);
  348. assert(src_clk_div < 127);
  349. switch (clk_id) {
  350. case SCLK_SPI0 ... SCLK_SPI2:
  351. spiclk = &spi_clkregs[clk_id - SCLK_SPI0];
  352. break;
  353. default:
  354. pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
  355. return -EINVAL;
  356. }
  357. rk_clrsetreg(&cru->clksel_con[spiclk->reg],
  358. ((0x7f << spiclk->div_shift) |
  359. (0x1 << spiclk->sel_shift)),
  360. ((src_clk_div << spiclk->div_shift) |
  361. (1 << spiclk->sel_shift)));
  362. return rk3368_spi_get_clk(cru, clk_id);
  363. }
  364. static ulong rk3368_saradc_get_clk(struct rk3368_cru *cru)
  365. {
  366. u32 div, val;
  367. val = readl(&cru->clksel_con[25]);
  368. div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,
  369. CLK_SARADC_DIV_CON_WIDTH);
  370. return DIV_TO_RATE(OSC_HZ, div);
  371. }
  372. static ulong rk3368_saradc_set_clk(struct rk3368_cru *cru, uint hz)
  373. {
  374. int src_clk_div;
  375. src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
  376. assert(src_clk_div < 128);
  377. rk_clrsetreg(&cru->clksel_con[25],
  378. CLK_SARADC_DIV_CON_MASK,
  379. src_clk_div << CLK_SARADC_DIV_CON_SHIFT);
  380. return rk3368_saradc_get_clk(cru);
  381. }
  382. static ulong rk3368_clk_get_rate(struct clk *clk)
  383. {
  384. struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
  385. ulong rate = 0;
  386. debug("%s: id %ld\n", __func__, clk->id);
  387. switch (clk->id) {
  388. case PLL_CPLL:
  389. rate = rkclk_pll_get_rate(priv->cru, CPLL);
  390. break;
  391. case PLL_GPLL:
  392. rate = rkclk_pll_get_rate(priv->cru, GPLL);
  393. break;
  394. case SCLK_SPI0 ... SCLK_SPI2:
  395. rate = rk3368_spi_get_clk(priv->cru, clk->id);
  396. break;
  397. #if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC_SUPPORT)
  398. case HCLK_SDMMC:
  399. case HCLK_EMMC:
  400. rate = rk3368_mmc_get_clk(priv->cru, clk->id);
  401. break;
  402. #endif
  403. case SCLK_SARADC:
  404. rate = rk3368_saradc_get_clk(priv->cru);
  405. break;
  406. default:
  407. return -ENOENT;
  408. }
  409. return rate;
  410. }
  411. static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate)
  412. {
  413. __maybe_unused struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
  414. ulong ret = 0;
  415. debug("%s id:%ld rate:%ld\n", __func__, clk->id, rate);
  416. switch (clk->id) {
  417. case SCLK_SPI0 ... SCLK_SPI2:
  418. ret = rk3368_spi_set_clk(priv->cru, clk->id, rate);
  419. break;
  420. #if IS_ENABLED(CONFIG_TPL_BUILD)
  421. case CLK_DDR:
  422. ret = rk3368_ddr_set_clk(priv->cru, rate);
  423. break;
  424. #endif
  425. #if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC_SUPPORT)
  426. case HCLK_SDMMC:
  427. case HCLK_EMMC:
  428. ret = rk3368_mmc_set_clk(clk, rate);
  429. break;
  430. #endif
  431. #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
  432. case SCLK_MAC:
  433. /* select the external clock */
  434. ret = rk3368_gmac_set_clk(priv->cru, rate);
  435. break;
  436. #endif
  437. case SCLK_SARADC:
  438. ret = rk3368_saradc_set_clk(priv->cru, rate);
  439. break;
  440. default:
  441. return -ENOENT;
  442. }
  443. return ret;
  444. }
  445. static int __maybe_unused rk3368_gmac_set_parent(struct clk *clk, struct clk *parent)
  446. {
  447. struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
  448. struct rk3368_cru *cru = priv->cru;
  449. const char *clock_output_name;
  450. int ret;
  451. /*
  452. * If the requested parent is in the same clock-controller and
  453. * the id is SCLK_MAC ("sclk_mac"), switch to the internal
  454. * clock.
  455. */
  456. if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC)) {
  457. debug("%s: switching GAMC to SCLK_MAC\n", __func__);
  458. rk_clrreg(&cru->clksel_con[43], GMAC_MUX_SEL_EXTCLK);
  459. return 0;
  460. }
  461. /*
  462. * Otherwise, we need to check the clock-output-names of the
  463. * requested parent to see if the requested id is "ext_gmac".
  464. */
  465. ret = dev_read_string_index(parent->dev, "clock-output-names",
  466. parent->id, &clock_output_name);
  467. if (ret < 0)
  468. return -ENODATA;
  469. /* If this is "ext_gmac", switch to the external clock input */
  470. if (!strcmp(clock_output_name, "ext_gmac")) {
  471. debug("%s: switching GMAC to external clock\n", __func__);
  472. rk_setreg(&cru->clksel_con[43], GMAC_MUX_SEL_EXTCLK);
  473. return 0;
  474. }
  475. return -EINVAL;
  476. }
  477. static int __maybe_unused rk3368_clk_set_parent(struct clk *clk, struct clk *parent)
  478. {
  479. switch (clk->id) {
  480. case SCLK_MAC:
  481. return rk3368_gmac_set_parent(clk, parent);
  482. }
  483. debug("%s: unsupported clk %ld\n", __func__, clk->id);
  484. return -ENOENT;
  485. }
  486. static struct clk_ops rk3368_clk_ops = {
  487. .get_rate = rk3368_clk_get_rate,
  488. .set_rate = rk3368_clk_set_rate,
  489. #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
  490. .set_parent = rk3368_clk_set_parent,
  491. #endif
  492. };
  493. static int rk3368_clk_probe(struct udevice *dev)
  494. {
  495. struct rk3368_clk_priv __maybe_unused *priv = dev_get_priv(dev);
  496. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  497. struct rk3368_clk_plat *plat = dev_get_plat(dev);
  498. priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
  499. #endif
  500. #if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
  501. rkclk_init(priv->cru);
  502. #endif
  503. return 0;
  504. }
  505. static int rk3368_clk_of_to_plat(struct udevice *dev)
  506. {
  507. #if !CONFIG_IS_ENABLED(OF_PLATDATA)
  508. struct rk3368_clk_priv *priv = dev_get_priv(dev);
  509. priv->cru = dev_read_addr_ptr(dev);
  510. #endif
  511. return 0;
  512. }
  513. static int rk3368_clk_bind(struct udevice *dev)
  514. {
  515. int ret;
  516. struct udevice *sys_child;
  517. struct sysreset_reg *priv;
  518. /* The reset driver does not have a device node, so bind it here */
  519. ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
  520. &sys_child);
  521. if (ret) {
  522. debug("Warning: No sysreset driver: ret=%d\n", ret);
  523. } else {
  524. priv = malloc(sizeof(struct sysreset_reg));
  525. priv->glb_srst_fst_value = offsetof(struct rk3368_cru,
  526. glb_srst_fst_val);
  527. priv->glb_srst_snd_value = offsetof(struct rk3368_cru,
  528. glb_srst_snd_val);
  529. dev_set_priv(sys_child, priv);
  530. }
  531. #if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
  532. ret = offsetof(struct rk3368_cru, softrst_con[0]);
  533. ret = rockchip_reset_bind(dev, ret, 15);
  534. if (ret)
  535. debug("Warning: software reset driver bind faile\n");
  536. #endif
  537. return ret;
  538. }
  539. static const struct udevice_id rk3368_clk_ids[] = {
  540. { .compatible = "rockchip,rk3368-cru" },
  541. { }
  542. };
  543. U_BOOT_DRIVER(rockchip_rk3368_cru) = {
  544. .name = "rockchip_rk3368_cru",
  545. .id = UCLASS_CLK,
  546. .of_match = rk3368_clk_ids,
  547. .priv_auto = sizeof(struct rk3368_clk_priv),
  548. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  549. .plat_auto = sizeof(struct rk3368_clk_plat),
  550. #endif
  551. .of_to_plat = rk3368_clk_of_to_plat,
  552. .ops = &rk3368_clk_ops,
  553. .bind = rk3368_clk_bind,
  554. .probe = rk3368_clk_probe,
  555. };